JPS6444123A - Pll circuit - Google Patents

Pll circuit

Info

Publication number
JPS6444123A
JPS6444123A JP62199875A JP19987587A JPS6444123A JP S6444123 A JPS6444123 A JP S6444123A JP 62199875 A JP62199875 A JP 62199875A JP 19987587 A JP19987587 A JP 19987587A JP S6444123 A JPS6444123 A JP S6444123A
Authority
JP
Japan
Prior art keywords
clock signal
vco
input signal
reset
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62199875A
Other languages
Japanese (ja)
Other versions
JPH07101848B2 (en
Inventor
Hideaki Takada
Yoshimi Iso
Haruyuki Inohana
Masami Tsuchida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Pioneer Corp
Original Assignee
Hitachi Ltd
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Pioneer Electronic Corp filed Critical Hitachi Ltd
Priority to JP62199875A priority Critical patent/JPH07101848B2/en
Publication of JPS6444123A publication Critical patent/JPS6444123A/en
Publication of JPH07101848B2 publication Critical patent/JPH07101848B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To obtain a clock signal synchronously with an input signal stably by providing a reset circuit to a voltage controlled oscillator, and resetting the oscillator when the input signal and the output clock signal of the oscillator are not synchronized. CONSTITUTION:An input signal supplied to an input terminal 1 and an output clock signal of a voltage controlled oscillator VCO 4 are fed to a phase comparator 2, and the output signal of the phase comparator 2 is fed to the VCO 4 via a low pass filter 3 to apply PLL operation. A reset circuit is provided to the VCO 4 and when the input signal and the clock signal are not synchronized, the VCO 4 is reset by a reset pulse generated from a reset pulse generating circuit 5. Thus, even when the repetitive period of the output waveform of the comparator 2 is smaller than the time constant of the filter 3, the PLL does not reach a pseudo stable state and the clock signal synchronously with the input signal is obtained stably.
JP62199875A 1987-08-12 1987-08-12 PLL circuit Expired - Fee Related JPH07101848B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62199875A JPH07101848B2 (en) 1987-08-12 1987-08-12 PLL circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62199875A JPH07101848B2 (en) 1987-08-12 1987-08-12 PLL circuit

Publications (2)

Publication Number Publication Date
JPS6444123A true JPS6444123A (en) 1989-02-16
JPH07101848B2 JPH07101848B2 (en) 1995-11-01

Family

ID=16415074

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62199875A Expired - Fee Related JPH07101848B2 (en) 1987-08-12 1987-08-12 PLL circuit

Country Status (1)

Country Link
JP (1) JPH07101848B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6066988A (en) * 1997-08-20 2000-05-23 Nec Corporation Phase locked loop circuit with high stability having a reset signal generating circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4853656A (en) * 1971-11-06 1973-07-27
JPS5943695A (en) * 1982-09-03 1984-03-10 Olympus Optical Co Ltd Picture recorder and reproducer
JPS6239919A (en) * 1985-08-14 1987-02-20 Mitsubishi Electric Corp Phase locked loop oscillation circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4853656A (en) * 1971-11-06 1973-07-27
JPS5943695A (en) * 1982-09-03 1984-03-10 Olympus Optical Co Ltd Picture recorder and reproducer
JPS6239919A (en) * 1985-08-14 1987-02-20 Mitsubishi Electric Corp Phase locked loop oscillation circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6066988A (en) * 1997-08-20 2000-05-23 Nec Corporation Phase locked loop circuit with high stability having a reset signal generating circuit

Also Published As

Publication number Publication date
JPH07101848B2 (en) 1995-11-01

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees