JPS6239709B2 - - Google Patents

Info

Publication number
JPS6239709B2
JPS6239709B2 JP5066080A JP5066080A JPS6239709B2 JP S6239709 B2 JPS6239709 B2 JP S6239709B2 JP 5066080 A JP5066080 A JP 5066080A JP 5066080 A JP5066080 A JP 5066080A JP S6239709 B2 JPS6239709 B2 JP S6239709B2
Authority
JP
Japan
Prior art keywords
current
voltage
zero point
polarity
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP5066080A
Other languages
Japanese (ja)
Other versions
JPS56147078A (en
Inventor
Akira Morita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP5066080A priority Critical patent/JPS56147078A/en
Publication of JPS56147078A publication Critical patent/JPS56147078A/en
Publication of JPS6239709B2 publication Critical patent/JPS6239709B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/327Testing of circuit interrupters, switches or circuit-breakers
    • G01R31/333Testing of the switching capacity of high-voltage circuit-breakers ; Testing of breaking capacity or related variables, e.g. post arc current or transient recovery voltage
    • G01R31/3333Apparatus, systems or circuits therefor

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Circuit Breakers, Generators, And Electric Motors (AREA)

Description

【発明の詳細な説明】 本発明は交流しや断器の合成試験において、低
電圧大電流源からの電流によるアークを延長する
ための半波延長方式に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a half-wave extension method for extending an arc caused by a current from a low-voltage, large-current source in a synthetic test of an AC shield or breaker.

しや断器の容量を検証するためには大電流でか
つ高い電圧を必要とするが、これを直接ひとつの
電源から供給して実負荷の短絡試験を行わせるこ
とは一般に困難である。このため、これと同様な
結果を得るため等価試験が行われるがそのひとつ
として、低電圧大電流源と高電圧低電流源の2種
の電源を組合わせて行う合成試験が知られてい
る。
Verifying the capacity of a circuit breaker requires a large current and high voltage, but it is generally difficult to supply this directly from a single power source and perform a short circuit test with an actual load. For this reason, equivalent tests are performed to obtain similar results, and one known example is a synthetic test that is performed by combining two types of power sources: a low voltage, large current source and a high voltage, low current source.

合成試験の回路例を第1図に示し、その動作波
形を第2図に示す。第1図は並列形電流重畳方式
と呼ばれる合成試験回路で、Genは発電機、Lgは
リアクトル、Cgはコンデンサ、SHは補助しや断
器、Spは供試しや断器、Reは抵抗、Ceはコンデ
ンサ、Lvはリアクトル、Gはギヤツプ、Cvはコ
ンデンサ、Recは充電装置である。試験は次のよ
うにして行われる。まず発電機Genから大電流Ig
を供試しや断器SHに供給すると(第2図b)は
発電機電圧を第2図cは発電機電流の波形を示
す)、時間Toで第2図aに示すように供試しや断
器SHの主接点が開になる。電流Igの最初の零点
の時点をT1、2回目の零点の時点をT2とすると
T2の直前にギヤツプGを動作させて高電圧に充
電されたコンデンサCvからの小電流Ivを印加重
畳させ(第2図e)、この小電流Ivの零点で電流
がしや断されるとしや断器Spの極間には第2図
fで示すように再起電圧TRVが発生することに
なる。
An example of the circuit for the synthesis test is shown in FIG. 1, and its operating waveforms are shown in FIG. Figure 1 shows a synthetic test circuit called the parallel current superimposition method, where Gen is the generator, Lg is the reactor, Cg is the capacitor, S H is the auxiliary disconnector, Sp is the sample or disconnector, Re is the resistor, Ce is a capacitor, Lv is a reactor, G is a gap, Cv is a capacitor, and Rec is a charging device. The test is conducted as follows. First, from the generator Gen to the large current Ig
is supplied to the test sample or disconnector S H (Figure 2b) shows the generator voltage and Fig. 2c shows the waveform of the generator current), then at time To the test sample or disconnector S H The main contact of disconnector S H opens. Let T 1 be the time of the first zero point of current Ig, and T 2 be the time of the second zero point.
Assume that the gap G is activated just before T 2 to apply a small current Iv from the capacitor Cv charged to a high voltage (Fig. 2e), and the current is suddenly cut off at the zero point of this small current Iv. As shown in FIG. 2f, a re-electromotive voltage TRV is generated between the poles of the disconnector Sp.

上述の試験においてT2−T0はしや断器のアー
ク時間となるが、このアーク時間を保証するため
にはしや断器の接点開後の最初の電流零点の時点
T1で電流Igがしや断されないようにする必要が
あり、強制的にこの部分のアークを継続させる方
法として知られているのが半波延長方式である。
In the above test, T 2 −T 0 is the arc time of the chopper or breaker, but in order to guarantee this arc time, the point of the first current zero point after the contact of the chopper or breaker is opened is
It is necessary to prevent the current Ig from being cut off at T 1 , and the half-wave extension method is known as a method for forcibly continuing the arc in this part.

従来行なわれている半波延長方式では、第2図
dに示すように、電流Igの零点T1の直前に、電
流Igの極性と反対極性のパルス電流Ipを印加す
る。すなわち第3図にさらに詳しく示すように、
電流Igの零点T1のTpにおいて、そのときの電流
Igの極性と反対極性のパルス電流を印加重畳する
と、合成電流は(Ig+Ip)となり、(Ig+Ip)の
電流零点における電流傾斜がある程度大きいとし
や断器はIg+Ip=0の時点でも電流をしや断する
ことはできないので、電流Igの極性が零点T1
反転して次の電流零点T2になるまでの半波長に
わたり、アークは継続することになる。このよう
なパルス電流を得る従来の半波延長回路を第4図
に示す。なお第4図において、第1図と同一符号
のものは同一要素を表わす。
In the conventional half-wave extension method, as shown in FIG. 2d, a pulse current Ip having a polarity opposite to that of the current Ig is applied immediately before the zero point T1 of the current Ig. That is, as shown in more detail in Figure 3,
At Tp of zero point T 1 of current Ig, the current at that time
When pulsed currents with opposite polarity to Ig are applied, the resultant current becomes (Ig + Ip), and if the current slope at the current zero point of (Ig + Ip) is large to some extent, the breaker will not cut the current even when Ig + Ip = 0. Therefore, the arc continues for half a wavelength until the polarity of the current Ig reverses at zero point T 1 and reaches the next current zero point T 2 . A conventional half-wave extension circuit for obtaining such a pulse current is shown in FIG. In FIG. 4, the same reference numerals as in FIG. 1 represent the same elements.

上述のパルス電流を発生させるため、コンデン
サCp1,Cp2、抵抗Rp,Rp2から成る放電回路
が使用される。あらかじめコンデンサCp1とCp2
を充電しておき、電流零点T1の前Tpでギヤツプ
Gpを動作させることにより、電流Igに電流Ipを
重畳させる。開閉器Sは通常閉の状態にしてお
き、電流零点T1でアークの継続がなされると次
の電流零点T2までに開にされる。
To generate the above-mentioned pulse current, a discharge circuit is used consisting of capacitors C p1 and C p2 and resistors R p and R p2 . Capacitors C p1 and C p2 in advance
is charged, and a gap is established at T p before the current zero point T 1 .
By operating Gp, current Ip is superimposed on current Ig. The switch S is normally kept in a closed state, and when the arc continues at the current zero point T1 , it is opened by the next current zero point T2 .

このように従来の半波延長回路では抵抗とコン
デンサで構成される放電回路を使用するが、その
問題点は次の通りである。まず、時間Tpの検出
については、Tpの長い方が検出方法すなわちギ
ヤツプGpの動作精度面からみて容易である。し
かしTpを長くした場合には、重畳するパルス電
流Ipの波高値を大きくする必要があり、そのため
には抵抗Rp,Rp2を小さくするか、コンデンサ
p1,Cp2に充電する電圧を高くする必要があ
る。しかるに、コンデンサの充電電圧を高くする
ことは、通常リアクトルLgや発電機Genの耐電圧
は余り大きくないので限界がある。また抵抗
Rp,Rp2を小さくした場合は、放電回路の時定
数が小さくなるため、電流Igが零点に達するまで
に放電電流Ipが減少して実質上電流重畳の役目を
果たさなくなりアークの強制継続に失敗する場合
がある。動作余裕時間を表わすTpを大きくし、
抵抗Rp,Rp2を小さくしてなおかつ確実なアー
ク継続を行わせるには、コンデンサCp1,Cp2
大きくすることで達せられるが経済的な方法では
ない。
As described above, the conventional half-wave extension circuit uses a discharge circuit composed of a resistor and a capacitor, but the problems are as follows. First, regarding the detection of the time Tp, the longer Tp is, the easier it is from the viewpoint of the detection method, that is, the operational accuracy of the gap Gp. However, when Tp is lengthened, it is necessary to increase the peak value of the superimposed pulse current Ip, and for this purpose, the resistors Rp and Rp 2 must be made smaller, or the voltage charged to the capacitors C p1 and C p2 must be increased. There is a need. However, there is a limit to increasing the charging voltage of the capacitor because the withstand voltage of the reactor Lg and generator Gen is usually not very high. Also resistance
When Rp and Rp 2 are made smaller, the time constant of the discharge circuit becomes smaller, so the discharge current Ip decreases by the time the current Ig reaches the zero point, and it virtually no longer serves as a current superimposition, failing to force the arc to continue. There are cases where Increase Tp, which represents the operating margin time,
Although it is possible to reduce the resistances Rp and Rp 2 and still ensure arc continuation by increasing the capacitors Cp 1 and Cp 2 , this is not an economical method.

したがつて本発明の目的は経済的な構成で確実
なアーク継続を保証する半波延長方式を提供する
ことである。
It is therefore an object of the present invention to provide a half-wave extension scheme which guarantees reliable arc continuity in an economical construction.

本発明の特徴は、上述の電流Igの零点T1直前
において、そのときの電流Igの極性と同極性から
開始する振動電流を印加重畳するようにしたこと
である。従来方式のように電流Igに重畳すべき電
流を電流Igと逆極性にするかわりに同極性にする
ことにより経済的に半波延長をなし得ることが判
明した。
A feature of the present invention is that, just before the zero point T1 of the current Ig described above, an oscillating current starting from the same polarity as the current Ig at that time is applied and superimposed. It has been found that half-wave extension can be achieved economically by making the current to be superimposed on the current Ig have the same polarity as the current Ig instead of having the opposite polarity as in the conventional method.

以下、図面を参照して本発明の実施例を説明す
る。この実施例では、振動電流として矩形波振動
電流が使用される。この矩形波振動電流を得るた
めには、例えば第5図aに示すように、インダク
タンスLとコンデンサcをπ形に複数個直列に接
続した回路で構成される。第5図aの回路におい
て、コンデンサを電圧Eに充電しておき、開閉器
Sを閉じると開閉器Sには、第5図bに示すよう
に振幅E/Z(Eはコンデンサ充電電圧、Z=√
)、周期4T(T=√×N;NはL、c
のπ形回路の段数)の矩形波振動電流Ipが流れ
る。
Embodiments of the present invention will be described below with reference to the drawings. In this embodiment, a square wave oscillating current is used as the oscillating current. In order to obtain this rectangular wave oscillating current, for example, as shown in FIG. 5a, a circuit is constructed in which a plurality of inductances L and capacitors c are connected in series in a π shape. In the circuit shown in Figure 5a, when the capacitor is charged to voltage E and the switch S is closed, the switch S has an amplitude E/Z (E is the capacitor charging voltage, Z) as shown in Figure 5b. =√
), period 4T (T=√×N; N is L, c
A rectangular wave oscillating current Ip of (the number of stages of the π-shaped circuit) flows.

本発明によれば、この矩形波振動電流Ipを、低
電圧大電流源からの電流Igの零点T1の直前にお
いて、そのときの電流Igの極性と同極性になるよ
うにして印加開始させるのであるが、その利点を
説明するため、以下、電流Igと逆極性に矩形波電
流Ipを印加した場合と、同極性に印加した場合と
を説明し両者を比較する。
According to the present invention, application of this rectangular wave oscillating current Ip is started immediately before the zero point T1 of the current Ig from the low voltage large current source so that the polarity becomes the same as that of the current Ig at that time. However, in order to explain the advantages thereof, a case where the rectangular wave current Ip is applied with the opposite polarity to the current Ig and a case where the rectangular wave current Ip is applied with the same polarity will be explained below and the two will be compared.

第6図は電流Igの零点T1前の極性と逆に電流
Ipを印加した場合の波形図である。第6図におい
て、Tpmは電流Igの零点T1前を検出する際の最
大値で、△tは検出時間のばらつき範囲(第4図
のギヤツプGpの動作ばらつき範囲)を示す。合
成電流(Ig+Ip)が供試しや断器に流れる電流で
ある。この場合アーク継続が保証されるためには
矩形波電流の振幅E/Zや周期4T(第6図では
2TをTsで示してある)を次のように選定する必
要がある。
Figure 6 shows the zero point T of the current Ig.The current is opposite to the previous polarity.
FIG. 3 is a waveform diagram when Ip is applied. In FIG. 6, Tpm is the maximum value when detecting the current Ig before the zero point T1 , and Δt indicates the variation range of the detection time (operation variation range of the gap Gp in FIG. 4). The combined current (Ig + Ip) is the current that flows through the test specimen and disconnector. In this case, in order to guarantee arc continuation, the amplitude E/Z of the rectangular wave current and the period 4T (in Fig. 6
2T is indicated by Ts) must be selected as follows.

Ts=Tpm+τ (1) においてτ>Tpmである必要がある(ここでT2
は電流Igの零点T1から電流Ipの極性が反転する
までの時間である)。この理由は、電流Ipが印加
されてから半周期Ts後の極性反転時において、
合成電流(Ig+Ip)の極性が変化化してはならな
いからである。したがつて、矩形波電流Ipの半周
期Tsは Ts>2Tpm (2) に選定しなければならない。
Ts=Tpm+τ (1) It is necessary that τ>Tpm (here, T 2
is the time from the zero point T1 of current Ig until the polarity of current Ip is reversed). The reason for this is that when the polarity is reversed half a cycle Ts after the current Ip is applied,
This is because the polarity of the composite current (Ig+Ip) must not change. Therefore, the half period Ts of the square wave current Ip must be selected such that Ts>2Tpm (2).

また矩形波電流Ipの振幅E/Zとしては電流Ip
の印加開始時における電流Igの瞬時値よりも大き
くする必要がある。すなわち E/Z>TpmdIg/dt (3) となる(ここにdIg/dtは電流Igの零点近傍の電流
の 傾きを示す)。
Also, as the amplitude E/Z of the rectangular wave current Ip, the current Ip
It is necessary to make the value larger than the instantaneous value of the current Ig at the start of application of the current Ig. That is, E/Z>TpmdIg/dt (3) (here, dIg/dt indicates the slope of the current near the zero point of the current Ig).

第7図は本発明に従い電流Igの極性と同極性か
ら矩形波電流Ipを印加開始した場合の波形図であ
る。この場合、矩形波電流の半周期Tsは Ts>Tpm (4) であればよい。このことは、第(2)式と比較して矩
形波電流の周期を約半分に選定できることを示し
ている。また電流Ipの振幅E/Zとしては E/Z>{Ts−(Tpm−△t)}dIg/dt(5) であればよい。この理由は、検出時間のばらつき
△tを考慮して、電流Igの零点T1前(Tpm−△
t)で電流Ipを印加した場合に、半周期Ts後の
電流Ipの極性反転時において、電流Ipの振幅がそ
のときの電流Igの値より大であれば合成電流(Ig
+Ip)も反転し得るからである(第7図b)。
FIG. 7 is a waveform diagram when application of the rectangular wave current Ip is started from the same polarity as the current Ig according to the present invention. In this case, the half period Ts of the rectangular wave current should just be Ts>Tpm (4). This shows that the period of the rectangular wave current can be selected to be about half as compared to Equation (2). Further, the amplitude E/Z of the current Ip may be as long as E/Z>{Ts-(Tpm-Δt)}dIg/dt(5). The reason for this is that before the zero point T1 of the current Ig (Tpm−△
t), when the polarity of current Ip is reversed after half a cycle Ts, if the amplitude of current Ip is larger than the value of current Ig at that time, then the composite current (Ig
+Ip) can also be inverted (Figure 7b).

第6図と第7図を比較すると、第7図の方式で
は、矩形波電流Ipの振幅も周期も非常に軽減され
ていることがわかる。電流Ipの振幅を小さくでき
るということは第5図の回路において、コンデン
サの充電電圧を小さくすることができることを意
味し、また周期を短かくできることは全体の√
×Nを小さくすることができることを意味
し、全体として経済的になることにつながる。
Comparing FIG. 6 and FIG. 7, it can be seen that in the method of FIG. 7, both the amplitude and period of the rectangular wave current Ip are greatly reduced. Being able to reduce the amplitude of the current Ip means that the charging voltage of the capacitor can be reduced in the circuit shown in Figure 5, and being able to shorten the period also reduces the overall √
This means that ×N can be made smaller, which leads to overall economy.

上述の実施例では、低電圧大電流源からの電流
Igに重畳するアーク半波延長用の電流Ipとして矩
形波電流を選んで説明したが、全体としてアーク
継続の条件を満足するかぎりにおいてその他の振
動電流を使用できることは当然である。
In the embodiment described above, the current from the low voltage high current source
Although the rectangular wave current has been selected as the arc half-wave extension current Ip superimposed on Ig, it is natural that other oscillating currents can be used as long as the conditions for arc continuation as a whole are satisfied.

このように本発明では、従来方式と異なり、電
流Igの零点前において、そのときの電流Igの極性
と同極性から開始する振動電流を印加重畳するこ
とによつて、経済的で確実な半波延長を行うこと
ができる。
In this way, unlike the conventional method, the present invention applies an oscillating current that starts from the same polarity as the current Ig before the zero point of the current Ig, thereby producing an economical and reliable half-wave. Extensions can be made.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は交流しや断器の合成試験回路図、第2
図は第1図の回路の動作波形図、第3図は従来の
半波延長方式説明用の波形図、第4図は従来の半
波延長回路図、第5図は本発明に使用される半波
延長回路の主要部の実施例図、第6図は矩形波振
動電流を逆極性で印加開始した場合の波形図、第
7図は本発明に従い矩形波振動電流を同極性で印
加開始した場合の波形図である。 Sp:供試しや断器、Gen:発電機、L:インダ
クタンス、C:コンデンサ。
Figure 1 is a composite test circuit diagram of an AC circuit breaker, Figure 2
The figure is an operating waveform diagram of the circuit in Figure 1, Figure 3 is a waveform diagram for explaining the conventional half-wave extension method, Figure 4 is a conventional half-wave extension circuit diagram, and Figure 5 is used in the present invention. An example diagram of the main part of a half-wave extension circuit, Figure 6 is a waveform diagram when applying a rectangular wave oscillating current with opposite polarity, and Figure 7 is a waveform diagram when applying a rectangular wave oscillating current with the same polarity according to the present invention. FIG. Sp: test sample or disconnector, Gen: generator, L: inductance, C: capacitor.

Claims (1)

【特許請求の範囲】[Claims] 1 低電圧大電流源と高電圧小電流源を備えた交
流しや断器の合成試験回路に使用される半波延長
方式において、前記低電圧大電流源の所定の電流
零点の直前においてその極性と同一極性から開始
する振動電流を大電流に重畳する振動回路を設け
たことを特徴とする半波延長方式。
1. In a half-wave extension method used in a composite test circuit for an alternating current shield or breaker equipped with a low-voltage, large-current source and a high-voltage, small-current source, the polarity of the low-voltage, large-current source is determined immediately before a predetermined current zero point of the low-voltage, large-current source. A half-wave extension method characterized by having an oscillating circuit that superimposes an oscillating current starting from the same polarity on a large current.
JP5066080A 1980-04-17 1980-04-17 Half-wave extending system Granted JPS56147078A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5066080A JPS56147078A (en) 1980-04-17 1980-04-17 Half-wave extending system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5066080A JPS56147078A (en) 1980-04-17 1980-04-17 Half-wave extending system

Publications (2)

Publication Number Publication Date
JPS56147078A JPS56147078A (en) 1981-11-14
JPS6239709B2 true JPS6239709B2 (en) 1987-08-25

Family

ID=12865099

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5066080A Granted JPS56147078A (en) 1980-04-17 1980-04-17 Half-wave extending system

Country Status (1)

Country Link
JP (1) JPS56147078A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102759710B (en) * 2012-07-27 2016-04-20 胡小青 Modified checkout equipment

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS501820A (en) * 1973-04-26 1975-01-09

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS501820A (en) * 1973-04-26 1975-01-09

Also Published As

Publication number Publication date
JPS56147078A (en) 1981-11-14

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