JPS6238550A - Control signal generating circuit - Google Patents

Abstract

PURPOSE:To generate a high-level control signal accurately at a prescribed timing without performing the software processing of a CPU by changing a pointer with a latch pulse to change the address of a memory. CONSTITUTION:The pulse from a comparator 3 is supplied to a pointer 7, and the pointer 3 is incremented to designate the third data block, and the pulse from the comparator 3 is supplied to a counter 6 to reset and start the counter 6. The output timing of output data of the third data block is judged by the comparator 3, and outputs corresponding to the third output data are obtained in output terminals 151-15N. Hereafter, the pointer 7 is incremented to obtain outputs corresponding to output data of prescribed data blocks successively in output terminals 151-15N simultaneously at a prescribed timing similarly. Thus, the CPU is released from the interrupt processing, etc. to perform the other software processings.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control signal generating circuit used in, for example, a VTR, which generates a control signal of a high level in a predetermined period at a predetermined timing.

[Summary of the invention]

The present invention stores output data and comparison data indicating the output timing of the output data in a memory in a control example signal generation circuit that generates, for example, a high-level control signal in a predetermined period at a predetermined timing, and compares the comparison data with a reference. By determining the timing at which the latch pulse is generated based on the clock signal generated, the control signal can be obtained at the output terminal without going through software processing by the CPU.

[Conventional technology]

For 3mm VTR, ATF (＾utomatc Tr
A configuration is known in which tracking servo is performed using a tracking servo technique. In this method, pilot signals having different frequencies are cyclically recorded on each of four adjacent video tracks on a magnetic tape on which video signals are recorded. Tracking servo is performed based on the pilot signal that is reproduced together with the video signal from the video track during playback, and the pilot signal that is selectively obtained by controlling the switch circuit using the control signal from the control signal ordering circuit configured by a microcomputer. It is something. The control signal from the control signal generation circuit is generated by software processing of the CPU in a form corresponding to various modes by the CPU and a timer.

The control signal generation circuit is used not only for ATF but also for other controls such as generating pulses that define the timing of flying erase during post-recording of audio signals.
It outputs a plurality of various control signals through software processing.

However, the required control signal accuracy is 5 m5ec±
The accuracy is about 10 μsec or more, and if you try to achieve this accuracy by processing with CPU software, you will need advanced design technology.

For this reason, a latch circuit is provided between the CPU and the output terminal, as in the control signal generation circuit shown in Japanese Patent Application No. 60-64556, to secure time for software processing of the CPU during the lunch timing. A configuration has been proposed in which an interrupt is generated by the output of a timer activated by an external pulse, and a control signal is generated through software processing, thereby generating the control signal accurately at a predetermined timing.

[Problem that the invention seeks to solve]

However, since the number of signal lines connected to a microcomputer is large, for example, several to several dozen, in reality, software design is extremely difficult even for conventional control signal generation circuits.

Therefore, it is an object of the present invention to provide a control signal generation circuit that can generate a control signal, for example, a high level control signal, in a predetermined period at a precisely predetermined timing without intervening software processing by a CPU.

[Means for solving problems]

The output data being read out from the memory 1 read by the pointer 7 is output to the latch output terminal 2°15, ~15,
A launch pulse is generated by the clock signal and comparison data indicating the generation timing of the launch pulse during readout of the memory 1, and the latch output terminal 2.1 is supplied to the latch output terminal 2.1.
5. This control signal generating circuit is characterized in that the control signal is obtained by supplying the signal at an angle of .about.15 DEG and changing the pointer 7 by a latch pulse to change the address of the memory 1.

[Effect]

Output data and comparison data indicating the output timing of the output data are stored in the memory 1 read by the pointer 7, the output data is supplied to the latch circuit 2, and at the same time, count comparison data in the comparison data is supplied to the comparator 3. At the same time, select data in the comparison data is supplied to the switch circuit 4 and the selector 5, the clock signal selected by the selector 5 is counted by the counter 6, and the count data is supplied to the comparator 3.
The timing of the latch pulse is determined in , and the latch pulse is supplied to the latch circuit 2, thereby generating an output corresponding to the output data at the output terminals 15+ to 15N, and the latch pulse is supplied to the pointer 7 and counter 6. The same process is repeated again.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 is a memory, and the memory 1 is configured to output a data block stored in the memory 1 corresponding to an address designated by a pointer 7.

Each data block stored in memory 1 is
As shown in FIG. 2, it is composed of output data and comparison data, and the comparison data is further composed of selection data and count comparison data.

Pointer 7 specifies the first data block at the same time as the power is turned on, and N-bit output data (A,
, AZ, A3...AM-1,AN) are supplied to the latch circuit 2. At the same time, pointer 7
n-bit count comparison data (al-"Z+...) read from memory 1 according to the address specified by
a,, ) are supplied to the comparator 3, and the pointer 7
Select data is stored in memory 1 according to the address specified by
is output from.

The select data is data for controlling the switch circuit 4 and the selector 5. 1-bit control data ST is supplied from the memory 1 to the switch circuit 4, and, for example, 2-bit control data (Sl.

S2) is supplied from the memory 1 to the selector 5.

A flag is supplied to the input terminal 12 of the switch circuit 4 from an external port via the terminal 10.
A CPU (not shown) is connected to the input terminal 13 of the
The flags from

The switch circuit 4 is controlled and switched by the control data ST to selectively switch between the external board or the CPU.
The flag from is supplied to the counter 6 as a start signal.

The selector 5 receives a clock signal of synchronously different periods, for example, 1 μsec, 10, which is obtained by dividing the system clock for operating the microcomputer by a frequency divider 8.
Four types of clock signals are supplied: μsec, 100 μsec, and 1 m5ec. The selector 5 is controlled by the control data (S1, S2) to select one of the four types of clock signals, and the selected predetermined clock signal is supplied to the counter 6.

The counter 6 starts a counting operation when a flag supplied via the switch circuit 4 rises, for example, and counts the rise of a selected clock signal supplied from the selector 5, for example.

This count value is then supplied to the comparator 3 as N-bit count data corresponding to the count comparison data from the memory 1.

In the comparator 3, the count comparison data supplied from the memory 1 and the count data from the counter 6 are compared. When the count comparison data and the count data match, a pulse is generated from the comparator 3, and this pulse is supplied to the latch circuit 2 as a latch pulse, and this pulse is also supplied to the pointer 7 and the counter 6.

In the latch circuit 2, the output data (A1.At, A3'', AM-1,A,
4) Output data (A + , A z, A 3...AN-1, A
N outputs corresponding to M ) are generated, and each output is held until the next latch pulse is supplied.

The pointer 7 is incremented by the pulse from the comparator 3 and points to the second data block according to the set predetermined order. The output data of the designated data block is supplied to the latch circuit 2. At the same time, count comparison data is supplied to the comparator 3, and
Select data is output from memory 1 to control switch circuit 4 and selector 5, and a selected clock signal is supplied to counter 6.

The counter 6 is reset and restarted by the pulse from the comparator 3, the clock signal from the selector 6 is counted, the count data is supplied to the comparator 3, and in the comparator 3, the count comparison data and the count data are combined. Based on this, the timing at which the latch pulse is generated is determined. When the count comparison data and the count data match, a latch pulse is supplied to the latch circuit 2, and the output data constituting the second data block supplied to the latch circuit 2 is latched, and the output terminals 15, .
An output corresponding to the output data is generated and held for each of N.

The pulse from the comparator 3 is supplied to the pointer 7, so that the pointer is further incremented, and the third data block is specified, and the pulse from the comparator 3 is supplied to the counter 6, so that the pointer 6 is incremented. After being reset/started, the output timing of the output data of the third data block is determined by the comparator 3, and an output corresponding to the third output data is obtained at the output terminals 151 to 15s.

In this way, while the pointer 7 is incremented in the same manner, outputs corresponding to the output data of a predetermined data block are sequentially output to the output terminals 15 and 15 at a predetermined timing. ~1
5.4 can be obtained simultaneously. That is, output terminals 151-15
．． In this case, N control signals are obtained, each of which is synchronously and independently set to a high level, for example, in a predetermined period at a predetermined timing.

In one embodiment of the present invention, a configuration has been described in which four types of clock signals as a reference are supplied from the frequency divider 8 to the selector 5, but the types of clock signals are not limited to four types. The configuration may be such that the selection data has a corresponding number of bits as another number of types. Further, the number of bits of the count comparison data and the count data from the counter 6 is defined by the number of types of clock signals from the frequency divider 8, their cycle intervals, and the desired maximum output holding time.

〔Effect of the invention〕

In this invention, output data and comparison data indicating the output timing of the output data are stored in a memory read out by a pointer, and the generation timing of a latch pulse is determined based on the comparison data and a reference clock signal. By supplying the latch pulse to the launch circuit, an output corresponding to the output data is generated at the output terminal, and at the same time, the latch pulse is supplied to the pointer and counter. Therefore, according to the present invention, the CPU software processing It is possible to simultaneously obtain a plurality of control signals that are set to a high level in a predetermined period, for example, at exactly a predetermined timing, without intervening.

In addition, since the CPU's software processing is not involved in the generation of control signals, not only is the burden on the software reduced, but the CPU is also freed from processing such as CPU interrupts that was previously required, allowing it to perform other software processing. It is possible to do so.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the invention, and FIG. 2 is a route diagram used to explain data blocks stored in a memory in an embodiment of the invention. Explanation of main symbols in the drawings 1: Memory, 2 Nirafuchi circuit, 3: Comparator, 4: Switch circuit, 5: Selector, 6: Counter, 7
: pointer, 8: divider, 15, ~15. : Output terminal. Agent Patent Attorney Tadashi Sugiura Figure 1

Claims (1)

[Claims] Output data during read output of the memory read by the pointer is supplied to the output terminal with a latch, and a latch pulse is generated by the clock signal and comparison data indicating the timing of generation of the latch pulse during read output of the memory, and the latch pulse is generated by the clock signal. 1. A control signal generating circuit characterized in that the control signal is obtained by being supplied to an additional output terminal, and by changing the pointer by the latch pulse and changing the address of the memory.