JPH06103556B2 - Control signal generation circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control signal generation circuit for generating a high level control signal in a predetermined section at a predetermined timing used for a VTR or the like.

[Outline of Invention]

The present invention is a control signal generating circuit that generates a high level control signal in a predetermined section at a predetermined timing,
The output data and the comparison data indicating the output timing of the output data are stored in the memory, and the generation timing of the latch pulse is judged by the comparison data and the reference clock signal, so that the control is performed without the software processing of the CPU. The signal is obtained at the output terminal.

[Conventional technology]

The 8mm VTR is known to perform tracking servo by ATF (Automatic Tracking Finding) technology. This cyclically records pilot signals of different frequencies on each of four adjacent video tracks on a magnetic tape on which a video signal is recorded. Tracking servo is performed based on a pilot signal which is reproduced together with a video signal from a video track during reproduction and a pilot signal which is selectively obtained by controlling a switch circuit by a control signal from a control signal generating circuit configured by a microcomputer. It is a thing. The control signal from the control signal generation circuit is CP
It is generated by software processing of the CPU in a form corresponding to various modes by U and a timer.

The control signal generation circuit outputs a plurality of various control signals by software processing not only in ATF but also in other control, for example, in the case of generating a pulse stipulating the timing of the flying erase when the audio signal is post-recorded. Is.

However, the required control signal accuracy is 5 msec ± 10 μsec
It is considered to be more than a certain degree, and if it is attempted to be processed by the software of the CPU with this precision, it requires advanced design technology.

Therefore, like the control signal generating circuit shown in Japanese Patent Application No. 60-64556, a latch circuit is provided between the CPU and the output terminal to secure the CPU software processing time between the latch timings. A configuration has been proposed in which an interrupt is generated by the output of a timer activated by a pulse from the outside, software processing is performed to generate a control signal, and the control signal is accurately generated at a predetermined timing.

[Problems to be solved by the invention]

However, since the number of signal lines controlled by the microcomputer is large, for example, several to several tens, in practice, designing software was extremely difficult even in the conventional control signal generating circuit.

Therefore, an object of the present invention is to provide a control signal generation circuit capable of generating a high level control signal in a predetermined section at a predetermined timing accurately without intervening CPU software processing.

[Means for solving problems]

According to the present invention, in a control signal generation circuit for generating a control signal at a predetermined timing, addressing is performed according to the pointer 7, and data including output data and comparison data for defining the timing is generated. The stored memory 1, the output terminal with a latch to which the output data from the memory 1 is latched, the comparison means to which the comparison data from the memory 1 is supplied, and the lock signal are counted from the timing defined by the start signal. And counting means for supplying the counting output to the comparing means, wherein the comparing means latches the output data to the latched output terminal when the comparison data and the counting output of the counting means match. Is a control signal generating circuit.

[Action]

Output data and comparison data indicating the output timing of the output data are stored in the memory 1 read by the pointer 7, the output data is supplied to the latch circuit 2, and at the same time, the count comparison data in the comparison data is supplied to the comparator 3. At the same time, the select data in the comparison data is supplied to the switch circuit 4 and the selector 5, the lock signal selected by the selector 5 is counted by the counter 6, the count data is supplied to the comparator 3, and the comparator 3 latches it. When the timing of the pulse is judged and the latch pulse is supplied to the latch circuit 2, the output terminal 15
An output corresponding to the output data occurs at ₁ to 15 _N , and
The latch pulse is supplied to the pointer 7 and the counter 6, and the same processing is repeated again.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 1 is a memory, and the memory 1 is configured to output a data block stored in the memory 1 corresponding to an address designated by a pointer 7.

Each data block stored in the memory 1 is
As shown in FIG. 2, it is composed of output data and comparison data, and the comparison data is further composed of select data and count comparison data.

The pointer 7 designates the first data block at the same time when the power is turned on, and the N-bit output data (A ₁ , A ₂ ,
A ₃ ... A _N-1 , A _N ) are supplied to the latch circuit 2. At the same time, the n-bit count comparison data (a ₁ , a ₂ , ... An) read from the memory 1 according to the address designated by the pointer 7 is supplied to the comparator 3 and the pointer 7 is designated. The select data is output from the memory 1 according to the address.

The select data is data for controlling the switch circuit 4 and the selector 5, and the 1-bit control data ST is the memory 1
Are supplied from the memory 1 to the switch circuit 4 and, for example, 2-bit control data (S1, S2) are supplied from the memory 1 to the selector 5.

A flag is supplied from an external port to the input terminal 12 of the switch circuit 4 via the terminal 10, and a flag from a CPU (not shown) is supplied to the input terminal 13 of the switch circuit 4 via the terminal 11. . When the switch circuit 4 is controlled and switched by the control data ST, the flag from the external port or the CPU is selectively supplied to the counter 6 as a start signal.

A clock signal having a different cycle in synchronization is obtained by dividing the system clock for operating the microcomputer by the frequency divider 8 in the selector 5, for example, 1 μsec, 10 μsec, 10
Four kinds of clock signals of 0 μsec and 1 msec are supplied. The selector 5 is controlled by the control data (S1, S2) to select one of the four types of clock signals, and the selected predetermined clock signal is supplied to the counter 6.

The counter 6 starts the counting operation when the flag supplied through the switch circuit 4 rises, for example, and counts the rising edge of the selected clock signal supplied from the selector 5, for example. Then, this count value is supplied to the comparator 3 as N-bit count data corresponding to the count comparison data from the memory 1.

In the comparator 3, the count comparison data supplied from the memory 1 and the count data from the counter 6 are compared. When the count comparison data and the count data match, a pulse is generated from the comparator 3, the pulse is supplied to the latch circuit 2 as a latch pulse, and the pulse is supplied to the pointer 7 and the counter 6.

In the latch circuit 2, the output data supplied from the memory _{1 (A 1, A 2,} A 3 ··· A N-1, A N) is latched, the output terminal 15 ₁ to 15 _N in the output data (A ₁ , A ₂ , A ₃・ ・ ・ A _N-1 ,
_N outputs corresponding to A _N ) are generated, and the respective outputs are held until the next latch pulse is supplied.

The pointer 7 is incremented by the pulse from the comparator 3, and designates the second data block according to the set predetermined order. The output data of the designated data block is supplied to the latch circuit 2. At the same time, the count comparison data is supplied to the comparator 3,
The select data is output from the memory 1, the switch circuit 4 and the selector 5 are controlled, and the selected clock signal is supplied to the counter 6.

The counter 6 is reset and restarted by the pulse from the comparator 3, the clock signal from the selector 5 is counted, the count data is supplied to the comparator 3, and the comparator 3 converts the count comparison data into the count data. The generation timing of the latch pulse is determined based on this. Then, when the count comparison data and the count data match, a latch pulse is supplied to the latch circuit 2, the output data constituting the second data block supplied to the latch circuit 2 is latched, and the output terminals 15 ₁ to 15 15 An output corresponding to the output data is generated for each _N and held.

When the pulse from the comparator 3 is supplied to the pointer 7, the pointer is further incremented, the third data block is designated, and the pulse from the comparator 3 is supplied to the counter 6, so that the counter 6 is is reset / started, the output corresponding to the third output data is obtained to the third output timing of the output data of the data block is determined by the comparator 3 output terminals 15 ₁ to 15 _N.

In this way, similarly output pointer 7 corresponding to the output data of the sequential predetermined data blocks while being incremented simultaneously obtained at the output terminal 15 ₁ to 15 _N at a predetermined timing following. That is, the output terminal 15 ₁ to 15 _N, independently in the form of each is synchronized, N number of control signals are predetermined interval for example, a high level at a predetermined timing is obtained.

In the embodiment of the present invention, the configuration in which the four kinds of clock signals as the reference are supplied from the frequency divider 8 to the selector 5 has been described, but the kinds of the clock signals are not limited to four kinds. As another type, the select data may have a bit number corresponding to it. Also,
The number of bits of the count comparison data and the count data from the counter 6 is defined by the number of types of clock signals from the frequency divider 8, their cycle intervals, and the desired maximum output holding time.

〔The invention's effect〕

In this invention, the output data and the comparison data indicating the output timing of the output data are stored in the memory read by the pointer, and the generation timing of the latch pulse is determined by the comparison data and the reference clock signal. By supplying the latch pulse to the latch circuit, an output corresponding to the output data is generated at the output terminal, and the latch pulse is supplied to the pointer and the counter.

Therefore, according to the present invention, it is possible to simultaneously obtain a plurality of control signals that are at a predetermined interval, for example, at a high level, accurately at a predetermined timing without the intervention of software processing of the CPU.

Moreover, not only the software processing of the CPU does not intervene in the generation of the control signal, but the load on the software is not only reduced, but the CPU interrupt processing, which has been conventionally required, can also be performed.
The PU is released to allow other software processing.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a schematic diagram used for explaining a data block stored in a memory in an embodiment of the present invention. Description of the key symbols in drawings 1: Memory, 2: latch circuit, 3: comparator, 4: switching circuit, 5: Selector, 6: counter, 7: pointer, 8: divider, 15 ₁ to 15 _N: Output terminal.

Claims (1)

[Claims] 1. A control signal generation circuit for generating a control signal at a predetermined timing, wherein address designation according to a pointer is made, and data consisting of output data and comparison data for defining the timing is provided. The stored memory, the output terminal with a latch for latching the output data from the memory, the comparing means to which the comparison data from the memory is supplied, and the lock signal counting from the timing defined by the start signal And a counting means for supplying a counting output to the comparing means, wherein the comparing means outputs the output data to the latched output terminal when the comparison data matches the counting output of the counting means. A control signal generating circuit characterized by being latched.