JP3091536B2 - Video tape recorder field discrimination circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field discriminating circuit for a video tape recorder, and more particularly to a multi-system video tape recorder capable of reproducing both 60-field and 50-field video signals. The present invention relates to a field discriminating circuit of a video tape recorder for discriminating whether a video signal recorded on a tape is a 60-field system or a 50-field system.

[0002]

2. Description of the Related Art A conventional field discriminating circuit 1 of this kind.
As shown in FIG. 6, the horizontal synchronizing pulse signal output from the synchronizing separation circuit 2 is input to the clock of the counter circuit 3, the vertical synchronizing pulse signal is input to the reset terminal of the counter circuit 3, The number of horizontal synchronizing pulse signals during one cycle (one field) of the signal is counted. If the number is equal to or larger than a predetermined count value, the reproduced video signal is determined to be a 50-field system. Had been determined to be.

[0003] Specifically, a 50-field video signal has a horizontal synchronizing pulse signal of 312.
The number is 5 and 262.5 in the 60-field system. Therefore, the boundary value of the count number of the horizontal synchronization pulse signal is set to 287 near the middle. On the other hand, the counter circuit 3 is reset by the vertical synchronizing pulse signal, counts the horizontal synchronizing pulse signal, and is reset again by the next vertical synchronizing pulse signal, but before the reset, the count value exceeds the above boundary value. If so, the video signal is determined to be of the 50-field type, and if not, it is determined to be of the 60-field type.

[0004]

In the conventional field discriminating circuit, a vertical synchronizing pulse signal is used as a reset pulse of the counter circuit 3, and the counting of the horizontal synchronizing pulse signal is performed during the entire period of one field. Therefore, when the vertical synchronizing pulse signal or the horizontal synchronizing pulse signal is not accurately reproduced in the entire period of one field, a problem occurs. For example, the vertical sync pulse signal is not reproduced properly due to a large scratch on the tape, or a large noise occurs as in the case of a picture search and many horizontal sync pulse signals are lost. Also,
In the helical scan type, the video signal of one track, that is, one field is connected near the vertical synchronization pulse signal, so that the horizontal synchronization pulse signal in the vicinity is in an unstable state. In such a case, there is a problem that the reliability of the count value is extremely low and cannot be accurately determined.

SUMMARY OF THE INVENTION It is, therefore, a primary object of the present invention to provide a video tape recorder field discriminating circuit capable of accurately discriminating fields.

[0006]

SUMMARY OF THE INVENTION The present invention comprises counting means for counting the number of pulses of a horizontal synchronizing signal in a reproduced video signal, and counts the number of pulses of the horizontal synchronizing signal counted by the counting means on a video tape being reproduced. Determining whether a 60-field video signal is recorded or a 50-field video signal is recorded;
In the field discriminating circuit of the video tape recorder,
A field discriminating circuit for a video tape recorder, characterized in that the counting period of the counting means is restricted to a part of one field period, and the counting means is reset based on a head switching signal or a dropout signal. .

[0007]

In order to automatically determine whether a 60-field video signal or a 50-field video signal is recorded on a video tape being reproduced,
The number of pulses of the horizontal synchronizing signal in the reproduced video signal is counted by the counting means. For the counting operation of the counting means, a cylinder rotation pulse signal (hereinafter DFG pulse) used for controlling the rotation speed of the cylinder is, for example, 1/4
Frequency division is performed, and a reset pulse is generated every four periods of the DFG pulse using the frequency division. By this, the counting means becomes DF
The number of horizontal synchronization pulse signals in two periods of the G pulse is counted. Therefore, the count of the horizontal synchronizing pulse is a fraction of one field, and is continued to improve the discrimination accuracy. Also, since it is necessary to count the horizontal synchronization pulse signal for each field, a reset pulse is generated using a head switching pulse signal (hereinafter, RF SW pulse), and the counting operation of the horizontal synchronization pulse signal is performed at the end of one field. Reset. Further, when an accurate horizontal synchronization pulse signal cannot be obtained due to the occurrence of dropout or noise, the DOC (video) generated by the video circuit is generated when the dropout or noise occurs so that the horizontal synchronization pulse signal is not counted. Drop Out Compens
ator) A reset pulse is generated by using a pulse, so that when a dropout or noise occurs, the count of the horizontal synchronizing pulse signal is not performed so that a malfunction of the count is eliminated. Therefore, the horizontal synchronization pulse signal can be accurately obtained and counted.

[0008]

According to the present invention, the number of horizontal synchronizing pulse signals can be accurately counted.
It is possible to accurately determine whether the system is a 0-field system or a 50-field system. The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0009]

Referring to FIG. 1, a field discriminating circuit 10 of this embodiment includes input terminals 12a to 12d. An RF SW pulse is input from the input terminal 12a, and the input terminal 1
A DOC pulse is input from 2b. Then, a DFG pulse is input from the input terminal 12c,
From d, a horizontal synchronization pulse signal is input.

[0010] RF SW input from the input terminal 12a
The pulse is input to an XOR gate 14 constituting a differentiating circuit, and the output is input to an OR gate 16. The OR gate 16 further includes DO input from the input terminal 12b.
The C pulse is input, and the output is input to the reset terminal R of the DFG counter 18 composed of a 2-bit binary counter. The output of OR gate 16 is further OR gate 2
Input to 0.

The DFG counter 18 is provided for the XOR gate 14
Or by a DOC pulse signal from the input terminal 12b. That is, the DFG counter 18 is reset every time the head is switched, or reset when a dropout occurs. Then, a DFG pulse from the terminal 12c is applied to the clock input of the DFG counter 18. Therefore, from the Q ₀ terminal of the DFG counter 18, FIG. 2
As shown in ( ₁₎ , a signal obtained by dividing the DFG pulse by 出力 is output, and a signal obtained by dividing the DFG pulse by ４ is output from the Q1 terminal.

[0012] The output from the Q ₁ terminal of the DFG counter 18 (1/4 signal) is input to a data terminal of the D flip-flop 22 and is also input to AND gate 26 through a NOT circuit 24 . The output (１ ／ signal) from the Q ₀ terminal of the DFG counter 18 is further input to the AND gate 26. Accordingly, a signal as shown in FIG. 2 is output from the AND gate 26 and is input to the OR gate 20.

As described above, from the OR gate 20,
A reset pulse is applied to the reset terminal R of the fH counter 28 comprising a 6-bit binary counter for counting the horizontal synchronization pulse signal every time the head is switched, every time a dropout or noise occurs, or every one field is divided into four. A signal is provided. The horizontal synchronization pulse signal input from the input terminal 12d is input to the clock terminal CLK of the fH counter 28 through the monostable multivibrator 30 for removing noise. The fH counter 28 counts the horizontal synchronizing pulse signal. Basically, based on the output pulse from the AND gate 26 among the reset pulse signals input to the reset terminal of the fH counter 28, four cycles of the DFG pulse signal half portion i.e., counts the section C of the output from the Q ₁ terminal of the DFG counter 18 shown in FIG. However, when the DOC pulse appears in the reset pulse signal, the counting operation is reset once, and starts counting again from the beginning. The count data counted by the fH counter 28 in this manner is output to the output terminals Q ₀ -Q of the fH counter 28.
₅ and the outputs Q _{0 to} Q ₅ are AND
It is provided to an individual input of gate 32. AND gate 32
Determines whether the count value of the fH counter 28 is above or below a predetermined boundary value.

The boundary value is set as the number of horizontal synchronization pulse signals in two DFG pulse periods. Generally, the DFG pulse is set so as to generate 30 pulses per rotation of the cylinder. At this time, the horizontal synchronizing pulse is 1 per DFG pulse in a 60-field video signal.
There are 7.5 and 20.8 in a 50-field video signal. When performing rewind playback or fast forward playback,
The number of horizontal sync pulse signals per field is ± 5%
The closest values are 18.4 and 1 respectively.
9.8 pieces. Therefore, the closest approach value of the horizontal synchronization pulse in two periods of the DFG pulse is 36.8 for a 60-field video signal and 3 for a 50-field video signal.
It becomes 9.6 pieces. From this, the boundary value is set to 38. Therefore, the outputs Q ₀ , Q ₃ of the fH counter 28
And Q ₄ are inverted and outputs Q ₁ , Q ₂ and Q
₅ is supplied to the AND gate 32 as it is. Therefore, when the count value of the fH counter 28 becomes "38", the AND gate 32 outputs a high level or "1".

The reason why the number of horizontal synchronizing pulse signals is counted in two periods of the DFG pulse is as described above when counting the number of horizontal synchronizing pulse signals in one period.
Since the interval between the closest approach values of the 0-field video signal and the 50-field video signal is as small as 1.4 and has no margin, if the field is determined with 19 boundary values, the possibility of malfunction is extremely high. Because it is expensive.
For this reason, in this embodiment, the DFG pulse signal is
The FG counter 18 divides the frequency by 1/4, counts the horizontal pulse signal in the latter half of the four cycles, and gives a margin to the closest approach value to the boundary value.

The boundary value output from the AND gate 32 is input to the clock terminal of the D flip-flop 22. For example, when a 50-field video signal is being reproduced, the clock is set in the high level period of the data input signal of the D flip-flop 22, that is, in the latter half of the four periods of the DFG pulse signal divided by 1/4. That is, a boundary value output signal appears. Therefore, the non-inverted output of the D flip-flop 22 becomes high level, whereby it can be determined that the reproduced video signal is of the 50-field type. On the other hand, when the reproduced video signal has a 60-field system, a clock appears during the low level period of the data input signal of the D flip-flop as shown in FIG. Therefore, the non-inverted output of the D flip-flop 22 becomes low level, and the inverted output becomes high level. This makes it possible to determine that the video signal being reproduced is of the 60-field type.

When the DOC pulse is generated, the DFG counter 18 and the fH counter 28 are set to 1 as described above.
However, at this time, since there is no boundary value output, the determination result in the D flip-flop 22 does not change.
Based on this, the video signal of each field system is reproduced. Such a field discriminating circuit 10 is incorporated in a video tape recorder as shown in FIG. 5, and forms a multi-system video tape recorder 40. The field determination circuit 10 receives an RF SW pulse signal from the cylinder motor 42 and a DFG pulse signal from a DFG pulse generator 44 connected to the cylinder motor 42. The DOC pulse signal is input from a video reproduction circuit 46, and the horizontal synchronization pulse signal is input from a sync separation circuit 48 connected to the video reproduction circuit. Then, a discrimination output indicating whether the reproduced video signal is of the 60-field system or the 50-field system is input to the video reproducing circuit 46 and the servo circuit 50 to switch between them. Then, a video signal is output from the video reproduction circuit 46.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart showing signals of respective units showing an operation in the embodiment of FIG. 1;

FIG. 3 is a timing chart showing input / output signals of a D flip-flop when a reproduced video signal has a 50-field system.

FIG. 4 is a timing chart showing input / output signals of a D flip-flop when a reproduced video signal has a 60-field system.

5 is a block diagram showing a multi-system video tape recorder incorporating the field discriminating circuit of the embodiment of FIG.

FIG. 6 is a block diagram showing a conventional technique.

[Explanation of symbols]

 10 Field discriminating circuit 18 DFG counter 22 D flip-flop 28 fH counter

Claims (1)

(57) [Claims] A counting means for counting the number of pulses of a horizontal synchronizing signal in a reproduced video signal. A 60-field video signal is recorded on a video tape being reproduced based on the number of pulses of the horizontal synchronizing signal counted by the counting means. In a field discriminating circuit of a video tape recorder for discriminating whether a signal is recorded or a 50-field video signal is recorded, a counting period of the counting means is restricted to a part of one field period, and the counting means Is reset based on a head switching signal or a dropout signal.