JPS58190845U - Recording mode discrimination circuit - Google Patents
Recording mode discrimination circuitInfo
- Publication number
- JPS58190845U JPS58190845U JP8964782U JP8964782U JPS58190845U JP S58190845 U JPS58190845 U JP S58190845U JP 8964782 U JP8964782 U JP 8964782U JP 8964782 U JP8964782 U JP 8964782U JP S58190845 U JPS58190845 U JP S58190845U
- Authority
- JP
- Japan
- Prior art keywords
- output
- recording mode
- mode discrimination
- discrimination circuit
- shift register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の回路ブロック図、第２図は本考案の一実
施例を示す回路ブロック図、第３図は要部波形説明図を
それぞれ示す。
主な図番の説明、２・・・カウンタ、４・・・第２モノ
マルチ、５・・・シフトレジスタ、６・・・多数決論理
回路、ＭＣ・・・キャプスタンモータ。FIG. 1 is a conventional circuit block diagram, FIG. 2 is a circuit block diagram showing an embodiment of the present invention, and FIG. 3 is a diagram illustrating waveforms of main parts. Explanation of main figure numbers, 2...Counter, 4...Second monomulti, 5...Shift register, 6...Majority logic circuit, MC...Capstan motor.
Claims (1)
パルスを計数するカウンタの計数出力に基き、記録時の
テープ速度を判定し、キャプスタンモータの回転速度を
切換えるビデオテープレコーダのテープ速度切換機構に
於て、 。 前記再生コントロール信号に同期して前記計数出力をシ
フトするシフトレジスタと、該シフトレジスタの各ビッ
ト出力を入力とする多数決論理回路とを付加し、該多数
決論理回路出力を判定出力として導出することを特徴と
する記録モード判別回路。[Claim for Utility Model Registration] A video tape recorder that determines the tape speed during recording based on the count output of a counter that counts rotation detection pulses of the capstan every cycle of a playback control signal, and switches the rotation speed of the capstan motor. In the tape speed switching mechanism of. A shift register that shifts the counting output in synchronization with the playback control signal and a majority logic circuit that receives each bit output of the shift register as input are added, and the output of the majority logic circuit is derived as a judgment output. Features a recording mode discrimination circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8964782U JPS58190845U (en) | 1982-06-15 | 1982-06-15 | Recording mode discrimination circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8964782U JPS58190845U (en) | 1982-06-15 | 1982-06-15 | Recording mode discrimination circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58190845U true JPS58190845U (en) | 1983-12-19 |
| JPH045060Y2 JPH045060Y2 (en) | 1992-02-13 |
Family
ID=30098246
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8964782U Granted JPS58190845U (en) | 1982-06-15 | 1982-06-15 | Recording mode discrimination circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58190845U (en) |
-
1982
- 1982-06-15 JP JP8964782U patent/JPS58190845U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH045060Y2 (en) | 1992-02-13 |
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