SU1205180A1 - Device for discriminating magnetic disk reproduction signals - Google Patents

Description

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The invention relates to instrumentation, and can be used in digital magnetic recording devices - playback. In particular, in magnetic disk drives.

The purpose of the invention is to increase the fidelity of the reproduction result.

Fig. 1 shows the structural scheme of the device proposed; Fig. 2 shows temporary dz-programs that explain its operation.

The device (figure 1) contains the counter 1 position, the arithmetic unit 2, enabling the trigger 3, the counter 4 gating intervals, the driver 5, the shift register 6, the decoder 7, the analysis block 8, the output register 9, the element OR 10, the synchronization input bus 11, input bus 12 initial installation., input bus 13 information and output bus 14 information.

The arithmetic unit 2 for detecting the playback signals recorded by the code 2/7 can be performed with a permanent memory 15 (ROM) containing a second shift register 16, a multiplier 17, a counter 18 and a D-flip-flop 19.

The synchronization input bus 11 is connected to the synchronous inputs of the position counter, the arithmetic unit 2 (the synchronous input of the second shift register 16 and the input of the multiplier 17), enabling trigger 3 and the shift register 6.

The input bus 12 of the initial installation is connected to the reset inputs of the counter 1 position, the arithmetic unit 2 (the reset inputs of the second shift register 16 and the counter 18), the shift register 6 and the output register 9.

The input information bus 13 is connected to the control inputs of the analysis unit 8 and the output register 9. The address inputs of the arithmetic unit 2 (ROM 15) are connected to the outputs of the 1 position counter, and to the control input of this ROM (to the control input of the ROM 15 and to the inverse the information input of the second counter 18) is connected to the code of the enabling trigger. The output of the arithmetic unit 2 (the output of the D-flip-flop 19) is connected to the synchronous input of the counter 4 atrobing intervals, the outputs of which are linked to information

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the inputs of the analysis unit 8, the outputs connected to the information inputs of the output register 9, the first, second and third outputs of which are connected to the element OR 10, the fourth output - to the output information bus 14 and to the information input of the shift register 6.

Element output OR 10 connected

d to the information input of the enabling trigger 3 and to the input of the imaging unit 5, the output connected to the clock input of the arithmetic unit 2 (the synchronization input of the D-flip-flop 19)

JJ and the reset input of the counter 4 strobing intervals.

The outputs of the register 6 shift connected to the first, second, third and fourth inputs of the decoder

2Q 7, the inputs of which are from fifth to eighth are connected to the outputs of the output register 9. The output of the decoder 7 is connected to another reset input of the counter 1 positions.

25 In the arithmetic unit 2, the ROM outputs are connected to the information inputs of the second shift register 16, the output of which is connected to the D input of the trigger 19. The output of the multiplier 17 is connected to the synchronous input of the counter 18, the output of which is connected to the zero address input of the ROM 15.

The device works in the following way.

Counter 1 position, arithmetic

 block 2, shift register 6, output register 9 are set to the zero state (Fig. 2o), then during playback of the previously recorded coded information (Fig. 2 a) J corresponds to the initial information sequence 100000010 received for recording with the beat T 2t) A signal is generated in the linear part of the playback channel (Fig. 28) and a sync signal (Fig. 26), the number of clock cycles of which is counted on a 1 position counter, the conditional signal from the output of which is shown in Fig. 2 g, the maximum

 coefficient 1) The recalculation factor of the counter of 1 positions is equal to the maximum length of the code word. From the output of the enabling trigger 3, the control signals (Fig. 22) are fed to the input of the arithmetic unit 2, which generates a sequence of gating intervals (Fig. 2g) depending on the position number of the coded word, which is determined by the counter 1 position The signals from the outputs of the counter 4 gating intervals determine the number of gating intervals (Fig. 2d). The input information bus 13 sends a signal (Fig. 2i) to the control inputs of the output register 9 and analysis unit 8, when the pulse peak lags from the middle of the clock signal determining its nominal position, the signal from the output of the analysis unit 8 goes to the first information output output register 9 (FIG. 2k), at the nominal position of the pulse peak relative to the center of the sync signal, determining its nominal position, the signal from the output of the analysis unit 8 is fed to the second information input of the output register 9 (Fig. 2A); ezhenii mid-pulse peak timing determined kmtsih its nominal position, the signal output from the analysis unit 8 is supplied to a third data input of the output register 9 (Figure 2). From the outputs of the output register 9, the signals arrive at the fifth, sixth, seventh and eighth inputs of the decoder 7 and

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the inputs of the SHS 10 element, the signal from the fourth output of the output register 9 is fed to the output information bus 14 (FIG. 2i). 5, FIG. 2 e shows an intermediate (generated in the arithmetic unit e 2) a sync signal whose frequency is higher than the sync signal frequency.

10 Application of the invention in magnetic disk drives, for example when upgrading a commercially available EC-5080 drive with replacing the MFM code used in this drive

15 by code 2/7, allows to increase the accuracy of the result of reproducing information, since it provides an opportunity to set the optimal duration of gating 20 intervals when playing back code 2/7, which is a code with a variable word length. Optimizing the duration of gating intervals and realizing it, depending on the measure of the position of the code word in which the playback pulse and on the current position number result in a reduction in the probability of error upon detection of the reproduced signal.

Application of the invention in magnetic disk drives, for example, when upgrading a commercially available EU-5080 drive with replacing the MFM code used in this drive

by code 2/7, it allows to increase the fidelity of the result of reproducing information, since it provides the opportunity to set the optimal duration of the gating intervals when playing the code 2/7, which is a code with a variable length of the word. Optimizing the duration of gating intervals and realizing it, depending on the position number of the codeword in which the playback pulse was received, and on the current position number, results in a decrease in the probability of error when detecting the reproduced signal.

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Claims (1)

(5'4) A MAGNETIC DISPLAY SIGNAL DETECTION DETECTION DEVICE, comprising a position counter that enables a trigger, an arithmetic unit, a gating interval counter, input synchronization buses, information, an initial setting bus and an output information bus, the input synchronization bus being connected to the sync input clocks. , enabling trigger and arithmetic unit, to the address inputs of which the outputs of the positions are connected, to the control input is the output of the enabling trigger, and to the installation input is the input bus at the initial installation, which is also connected to the reset input of the position counter, the output of the arithmetic block is connected to the clock input of the counter of the gating intervals, characterized in that, in order to increase the fidelity of the playback result, a shaper, a shift register, a decoder, an analysis unit, an output register, and OR element, wherein the input synchronization bus is connected to the shift register clock input, the initial setup bus is connected to the reset inputs of the shift register and output register, the input information bus is connected to the control inputs of the analysis unit and the output register, the information inputs connected to the outputs of the analysis unit, the first, second and third outputs - with the inputs of the OR element, and the fourth output - with the output information bus and the information input of the shift register, the output of the OR element is connected with information input enabling trigger and with the input of the shaper, the output of which is connected to the clock input of the arithmetic unit and to the reset input of the counter of the strobe intervals, the outputs of the shift register are connected to the first, w ring, third and fourth inputs of the decoder, fifth, sixth, seventh and eighth inputs which are connected to the outgoing register outputs, the decoder output is connected to another input of the reset position counter, and outputs counter gating intervals are connected to data inputs of the analysis unit.