JPS6194577A - Digital servo device - Google Patents

Abstract

PURPOSE:To control a plurality of motors by one counter by providing means for reading out the value of counter reset by a phase reference signal according to a speed detection pulse and a phase detection pulse. CONSTITUTION:A counter 11 counts a signal of a reference clock signal genera tor 12, and is reset by the output of a phase reference signal generator 6. latch circuits 141, 142 read out the counted value of the counter 11 synchronously with a speed detection pulse FG. A comparator 15 counts the difference of the outputs of the latch circuits 141, 142 to apply a speed error signal to a sample-holding circuit 20a. On the other hand, a latch circuit 16 reads out the counted value of the counter 11 synchronously with a phase detection pulse PG, and applies a phase error signal to a sample-holding circuit 20b. An adder 21 adds the outputs of the holding circuits 20a, 20b, and applies to a driver 22.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a digital servo device that performs phase control and speed control of a motor used in a video tape recorder (hereinafter referred to as VTRJ) or the like.

(b) Conventional technology.

The conventional digital servo device is as shown in Fig. 25 on page 191 and Fig. 26 on page 192 of Matsushita Technical Report VOL 2843 June 1982.
For each motor, two counters are used, one each for speed control and phase control.

Next, a conventional general digital servo device will be explained with reference to the block diagram shown in FIG. (1)
is the motor to be controlled, and the speed detection pulse generation circuit (
1a) and a phase detection pulse generation circuit (1b). The first counter (21) counts the output of the reference clock signal generation circuit (3), and counts the output of the reference clock signal generation circuit (3).
The i-th D/A converter (3λ) is reset by outputting the counted value to the second D/A converter (32) in synchronization with the output (FC, pulse) of 1a) (see FIG. 6). The analog output of is held in the first sample and hold circuit (4a) until the next FG pulse rises and is input to the adder (5) as a speed error signal.On the other hand, the second counter (2b) is connected to the phase reference signal generator. In synchronization with the output (■ pulse) of (6), counting of the output signal of the reference clock signal generator (3) is started, and one output (PC pulse) of the phase detection pulse generation circuit (1b) is synchronized. Then, calculate the counted value to the second D/A.
The analog output of the second D/A converter (3b) is held in the second sample and hold circuit (4b) until the next PC pulse rises. and the adder (
5). The output of the adder (5) is input to a drive circuit (7) to control the motor (1).

However, when such a digital servo device as described above is configured using a single-chip microcombiner, the microcombiner has one or two counters in one chip.
Since only one motor is usually built in, one chip has the disadvantage that it can control the speed and phase of at most one motor. That is, in order to control a plurality of motors, the number of microcombiners must be increased accordingly.

(c) Problems to be solved by the invention In the prior art, when a digital servo device is constructed using a one-chip microcomputer, the microcomputer has only one or two counters built into one chip. Therefore, there is a drawback that one chip can control the speed and phase of at most one motor. The present invention overcomes this drawback.

B) Means for Solving the Problems The present invention provides a counter that is reset only by a phase reference signal, and a reading comparison system that sequentially reads the values of the counter and compares adjacent values using a speed detection pulse of a rotating body. and reading means for reading the value of the counter using a phase detection pulse of the rotating body.

Item) Effect: In the read comparison means, the values of adjacent counters read by the speed detection pulse are compared,
The output is a speed error signal, and the value of the counter read by the phase detection pulse in the reading means is the phase error/effect signal. FIG. 1 shows a block diagram of a digital servo device for one motor as a first embodiment of the present invention. ,
αO) is a motor and is equipped with a speed detection pulse generator (10a) and a phase detection pulse generator (10b) as in the conventional example. The counter (111 is the reference clock signal generator (2)
) is counted and reset in synchronization with the output (■ pulse) of the phase reference signal generator (13) (see Figure 9J2). Two latch circuits (141) and (142) sequentially read the counted values of the counter (W) in synchronization with the output (FG pulse) of the speed detection pulse generator (10a), and these values are transferred to the comparator mark. and the difference between the two is calculated,
On the other hand, the latch circuit 0e receives the output (PG pulse) of the phase detection pulse generator (10b), which will later become a speed error signal.
The count value of the counter circle is read in synchronization with the phase error signal, and the output thereof later becomes a phase error signal. As shown in Fig. 2, the speed detection pulse generator (10a) and the phase detection pulse are used in advance so that the FC pulse and the PC pulse do not overlap in time near the set speed and set phase of the controlled motor (1). Since the generator (10b) is set (and the same counter (11) is used as a reference, the comparator α
The maximum values of the respective digital outputs of 9 and the latch circuit (161) are the same.In other words, the maximum operating ranges of the DA converters are the same, and as shown in FIG.
By using the demultiplexer (19), the D/A converter 0 seconds can be shared by the output of the comparator 4 and the output of the latch circuit Oe.

The output of the comparator represents the increase in the number of counts between adjacent FG pulses. Therefore, the multiplexer (1
71, DA converter ball, D through demultiplexer 09
The A-converted speed error signal is held by the sample Hall Bi circuit (20a) controlled by the FG pulse until a new speed error signal is generated in synchronization with the next FG pulse, and its output is sent to the adder C1J. is input. The output of the latch circuit 0e is P for the V pulse.
This represents the time lag of the G pulse. Therefore, it passes through the multiplexer f17) 1DA converter α and the demultiplexer (19) and is converted into a phase error signal.
A sample and hold circuit (20b) controlled by the PG pulse holds the phase error signal until a new phase error signal is generated in synchronization with the next PG pulse, and its output is input to the adder. In order to control the series of signal processing described above, an FC pulse and a PG pulse are applied to each of the multiplexer (1η, demultiplexer α9, and adder C21).The output of the adder C21 is input to the drive circuit and the drive circuit The output of is led to the motor (10), and speed control and phase control are performed.

Note that ◎ is the starter, and when starting the motor, the adder (2
Send a start signal to the drive circuit ■ via υ.

The comparator ■ usually has two latch circuits (141).
(142) The difference between adjacent data (number of counts) read in synchronization with the FG pulse is calculated.

That is, as shown in FIG. 2, a series of FC pulses FG+,
The counter value at each rise of FeF2 is N1.
．． If N2, calculate N2-N1. However, a series of FC pulses FG5. The phase base between the two, such as FG4 (counter values N3 and N4, respectively).

When pulse v1, which is the output of the quasi-signal generator (13), is generated, the counter 01) is reset, so speed control cannot be performed if the comparator (fence) is operating as described above. In the embodiment, a comparator (15) t-
After the pulse (2) is generated, the comparator a9 calculates N4+NM-N3 at the rising edge of the next FC pulse. However, N is the maximum value of the counter αD. Also,
In Fig. 1, even if one FC pulse is canceled after the V pulse is generated in the sample hold circuit (20a) that holds the speed error signal, and the previous speed error signal is held, the above The problem will be resolved.

Here, the operation of the block diagram in FIG. 1 will be briefly explained using FIG. 2. The FG pulse and PG pulse in the figure show the output when the motor α■ is in the set speed and set phase state. In each case, the horizontal axis represents t (time), and the vertical axis represents the magnitude of output. From the above state, as the rotational speed of the motor increases, the period of the FC pulse becomes shorter, and the increase in the number of counts between adjacent pulses becomes smaller.
The speed error signal becomes small, and since the PG pulse operates to the left in the drawing with respect to the V pulse, the value of the latch circuit α■ becomes small, and the phase error signal becomes small.

As the rotation speed decreases, contrary to the above, both the speed error signal and the phase error signal become large.

That is, since the speed control and phase control change the error signal in the same direction with respect to changes in the rotational speed of the motor, it operates as a digital servo device.

Note that the period of the FG pulse in the set speed state must be set to be smaller than the period of the V pulse, and the period of the PC pulse in the set phase state must be set to be the same as the period of the V pulse. This is clear from the description and FIG.

The first embodiment has been described above, but in the case where a one-chip microcomputer is used, speed control and phase control can be performed with one counter, so it can be configured with one chip.

Note that the latch circuit is an internal register or an external register.

Various controls are configured by microcomputer programs, etc.

Next, as a second embodiment of the present invention, a block diagram of a digital servo device provided for the herad motor and capstan motor, that is, the two motors of a B-positive VTR, is shown in FIG. 3 is a head motor, which is equipped with a speed detection pulse generator (30a) (output is FGH pulse) and a phase detection pulse generator (30b) (output is PGH pulse). 01) is a capstan motor, which is similarly equipped with a speed detection pulse generator (31) (output is FCC pulse) and a phase detection pulse generator (31b) (output is PGC pulse). Phase reference signal (V pulse) ) as 8
++ When recording an IVTR, the output of the synchronization separation circuit ■ which separates the vertical synchronization signal from the video signal is divided by the divider country, and the frequency is divided to 30 Hz. When reproducing, the crystal oscillator (to) is used.
A 3QHz signal obtained by frequency-dividing the output of the signal by a divider (to) is selected by a switch (to) according to the recording or reproduction mode, and is input to a counter (to). The counter □□□ counts the signal from the reference clock signal generator, and is reset in synchronization with the ■ pulse. (See Figure 4) Speed control and phase control of each motor share the counter (9),
This is carried out in the same manner as in the first embodiment. The speed error signal of the digital value of the head motor ■ is generated by two latch circuits (
391) (392) , the two latch circuits (39
1) A comparator (392) that compares the value latched to
(1) Considering the resetting of the counter by the pulse, the comparator (41) which controls the comparator (41) takes into account the input of the FGH pulse and the V pulse. The word is a latch circuit (which reads the count value of the counter in synchronization with the PGH pulse).
Made by 42J.

On the other hand, the speed error signal of the digital value of the capstan motor (9) is sent to two latch circuits (4, 51) (43) that sequentially read the count value of the counter (support) in synchronization with the FCC pulse.
2) A comparator (44) that compares the values latched by the two latch circuits (431) and (432), inputs the FCC pulse and the V pulse, and takes into consideration the resetting of the counter by the pulse.The first embodiment Similarly, a digital phase error signal is produced by a controller (a) which controls the comparator (I), and a digital phase error signal is produced by a latch circuit (punishment) which reads the count value of the counter (9) in synchronization with the PCC pulse. The error signal of each digital value is sent to a multiplexer (47),
It is converted into an analog value via a D/A converter (48) and a demultiplexer (+47), and held in each sample and hold circuit. In other words, the output of the comparator (4a1) is converted to DA and sent to the FG as the speed error signal of the head motor
Controlled by H pulse. The sample and hold circuit (50a) includes a latch circuit (the output of the mouth is DA converted, and the sample and hold circuit (50a) is controlled by the PGH pulse as a phase error signal of the head motor (2).
In b), the output of the comparator (44) is converted to DA and sent to the FCC as a speed error signal of the capstan motor (31J).
Sample and hold circuit controlled by pulse (
In 51a), the output of the latch circuit (46) is converted to DA and output as a phase error signal of the head motor C31).
Each is held in a sample and hold circuit (51b) controlled by a GC pulse. In addition, the multiplexer (47) and demultiplexer each have FGH.
Pulses, PGH pulses, FGC pulses, and PGC pulses are supplied as control signals, and error signals of each digital value are shared by the D/A converter by time division.

The reason why such a configuration is possible is the same as in the first embodiment, and the details will be omitted.

The speed error signal held in the sample hold circuit (50m) and the phase error signal held in the sample hold circuit (sob) both control the head motor (2) via an adder [Co., Ltd.] and a drive circuit ω.

(Incorporated) is a starter that sends a start signal to the drive circuit (Inc.) via an adder (support) when starting. On the other hand, the speed error signal held in the sample hold circuit (51λ) and the phase error signal held in the sample hold circuit (sib) both control the capstan motor (31) via the adder (to) and the drive circuit side. Do this.

(support) is a starter, which sends a start signal to the drive circuit side via an adder at the time of starting. However, the above is the case when recording with BwaVTR, and during playback, the output of the pilot IC (581) is used as the phase error signal of the capstan motor CIl], so it is necessary to switch with the switch ■. )
In this method, a tracking control signal is generated using four pilot signals recorded for each video track of a tape. The control using this pilot signal is described in detail in Japanese Patent Laid-Open No. 116120/1983.

FIG. 4 shows the FGH pulse when the head motor and capstan motor are at the set speed and set phase, respectively.
The output of PGH pulse, FGC pulse, and PGC pulse is shown. In each case, the horizontal axis represents time and the vertical axis represents the magnitude of output. The basic operation of the block diagram shown in Figure 3 is that the counter (support) is connected to the head motor ■ and the capstan motor (
It is almost the same as the first embodiment except that the speed control and phase control of (to) are shared, the inputs of the multiplexer +47 are 4, and the outputs of the demultiplexer (49) are 4, etc. Therefore, detailed explanation will be omitted.

Note that speed control is performed using the amount of increase in the counter count value between two adjacent pulses of the FGH pulse or FCC pulse, so the period of each pulse in the set speed state is determined by the reference phase signal (V pulse ) can be set arbitrarily as long as it is smaller than the period of PG
Since this is performed directly using the counter count value at the rising edge of the H pulse or PGC pulse, the period of each pulse in the set phase state must be the same as the period of the V pulse. Therefore, in order to perform phase control of two motors with different speeds as in the second embodiment, a branching unit or the like is provided in each phase detection pulse generator, and the period of each output pulse is set to the period of the phase reference signal. It needs to be the same as.

Although the second embodiment has been described above, in the present invention, the number of motors to be controlled is not limited to two, but can be implemented. That is, by sharing one counter that is reset by a phase reference signal, and increasing the number of speed detection pulse generators, phase detection pulse generators, and channels for each motor,
One counter can control the speed and phase of multiple motors.

(G) Effects of the Invention According to the digital servo device of the present invention, speed control and phase control of a plurality of motors can be performed with one counter, so only one or two counters are built in. The advantage is that a digital servo device that controls a plurality of motors can be realized with a simple configuration centered on one single-chip microcomputer.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a digital servo device embodying the present invention, and FIG. 2 is an explanatory diagram of its operation. FIG. 3 is a block diagram of a digital servo device showing another embodiment of the present invention, FIG. 4 is an explanatory diagram of its operation, FIG. 5 is a block diagram of a conventional digital servo device, and FIG.
! ! FIG. 7 is an explanatory diagram of the speed control and phase control operations in FIG. 5. (10)...Motor, (10m)...Speed detection pulse generator, (10b)...Phase detection pulse generator, α
X)...Counter, 03)...Phase reference signal generator, (141) (142) (16)...U/Tsuchi circuit, 05)...Comparator, 0 seconds...D/ A converter,■
...Drive circuit.

Claims (3)

[Claims] (1) a phase reference signal generator, a counter that counts reference clock signals and is reset by the output of the phase reference signal generator, and a first signal generator that outputs a signal representing speed information of the rotating body; a reading comparison means for sequentially reading the values of the counter using the output of the first signal generator and comparing adjacent values; a speed error signal generator receiving the output of the reading comparison means; and a speed error signal generator for receiving the output of the reading comparison means; a second signal generator that outputs a signal exhibiting phase information; reading means for reading the value of the counter based on the output of the second signal generator; and phase error signal generation having the output of the reading means as input. 1. A digital servo device, comprising: a drive circuit that receives the output of the speed error signal generator and the output of the phase error signal generator as input, and controls the rotating body. (2) The read comparison means comprises two latch circuits that sequentially latch the values of the counter, and a comparator that compares the outputs of the two latch circuits. The digital servo device described. (3) A plurality of the rotating bodies, first and second signal generators, reading comparison means, speed error signal generators, reading means, phase error signal generators, and drive circuits are present;
2. The digital servo device according to claim 1, wherein one counter and one phase reference signal generator are provided so that they are commonly used to control a plurality of rotating bodies.