JPS60123130A - Programmable pulse generator - Google Patents

Abstract

PURPOSE:To adjust the generation timing and the width of a pulse without complicating the constitution of a microcomputer and programs by providing a programmable pulse generator in the microcomputer. CONSTITUTION:A programmable pulse generator 1 is used in, for example, a system control computer of a VTR and is provided with a data set register 3, a pulse wide latch circuit 8, a programmable timer 9, a pulse generation control circuit 10, etc. When a reference pulse is inputted to a reference pulse input circuit 12, a control circuit 10 causes the timer 9 to measure a time designated by delay quantity data from the register 3 and generates an output pulse when this time elapses. Thereafter, the timer 9 measures a time designated by the pulse width from the latch circuit, and generation of said output pulse is stopped when this time elapses.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to a new programmable pulse generator, and in particular, it is possible to freely change pulse generation timing and pulse width without unnecessarily complicating the configuration or program of a microcomputer. The present invention aims to provide a new programmable pulse generator that can

More specifically, the present invention provides a programmable pulse generator installed in a microcomputer for system control of, for example, a video tape recorder.

Background Art and Problems Therein As shown in FIG. 1, a signal S is delayed by a certain time td from a certain signal S+ and has a predetermined pulse width tw.

If this is to be obtained by a special circuit, a circuit as shown in FIG. 2, for example, is required. In FIG. 2, ANDI to AND3 are AND circuits, and the input terminals of the first and second AND circuits ANDI and AND2 are connected to an input signal S.
i is input, and its two AND circuits AND 1 and A
The output signals sb and Scl of ND2 are input to a third AND circuit AND3, from which a signal SO is obtained. INVI and INV2 are inverters, and the first inverter INVI receives the input signal Si at its input terminal, and its output terminal is connected to one end of the first variable resistor vR1 and the input terminal of the second inverter INv2. . The other end of the first variable resistor VRI is connected to the anti-ground terminal of the capacitor C1, one end of which is grounded, and one end of the first resistor R1.
The other end is connected to the other input terminal of the first AND circuit ANDI. The output terminal of the second inverter INV2 is connected to one end of a second variable resistor VR2, and the other end of the variable resistor VR2 is connected to a capacitor C whose one end is grounded.
2 and one end of the second resistor R2. The other end of the resistor R2 is connected to the other input terminal of the second AND circuit AND2.

FIG. 3 is a time chart for explaining the operation of the circuit shown in FIG. 2.

As is clear from FIG. 3, the first AND circuit AND
The signal Sa applied to the other input terminal of l (the input terminal opposite to the terminal to which the input signal Si is applied) is equal to the input signal S
When i is "low", "/\i" is maintained. Then, when the input signal St is inverted from "low" to "high", the signal Sa
The level gradually decreases. Therefore, the output signal sb of the first AND circuit AND1 is such that the input signal Si is "low".
When you stand up from ``high'', you stand up -1-. Then, when the level of the signal Sa reaches a certain value or less, the signal Sb is inverted from "high" to "low". The pulse width tb of this signal sb is determined by the time constant of the capacitor C1 and the variable resistor vR1.

Further, the signal Sc at the other input terminal of the second AND circuit AND2 (the input terminal opposite to the input terminal to which the input signal St is input) remains "low" when the input signal Si is "low", When the input signal Si becomes "high J", the level of the signal Sc gradually increases. Then, when the level of the signal Sc reaches a certain level, the output signal Sd of the second AND circuit AND2, which was "low" is reversed to "high". After this input signal Si rises to "high", the signal Sd changes to "
The time td until it rises to "high" is the second variable resistor V
It is determined by the time constant of R2 and the second capacitor C2. Therefore, - the third AND circuit AND3 outputting the AND signal of the above-mentioned signals sb and Sd has a rising pulse width tw(t
b-td) output signal SO can be generated.

In this way, the signal to, which is delayed by a certain period of time td from a certain signal St and has a predetermined pulse width tw, can be realized by a circuit as shown in FIG. However, when configuring such a circuit, in addition to the AND circuit and the inverter logic circuit, relatively expensive components such as resistors and variable resistors are required, resulting in an increase in cost. Of course, a fixed resistor can be used instead of a variable resistor, but
In order to make the times td and tw highly accurate, a variable resistor for adjusting igI is essential, and an increase in cost cannot be avoided. Further, adjustment work is required, and the time and effort involved in that work cannot be ignored.

Therefore, it is conceivable to use a microcomputer instead of using the above-mentioned hardware circuit. in this case,
In order to obtain the desired pulse signal SO, it is necessary to add a program as shown in FIG. 4 to the microcomputer software. This program (a)
~(NU) The complete explanation is as follows.

(b) “Set SO to Lj.” As an initial condition, the output signal So is reset to [LJ.

(b) RTD data set” Data specifying the delay time td is set in the timer.

(c) Has RSI started up? It is determined whether the input signal St has risen from "r low" to "high". If the judgment result is “Know”, “Yes”
The determination is repeated until the determination result is obtained.

(d) "Start timer" If the determination result in step (c) is "yes", the timer starts measuring time.

(E) Has the RTD time elapsed? ” Determine whether the timer value has reached td. If the determination result is [No J, repeat the determination until a "yes" determination result is obtained.

(e) "Stop timer" If a "yes" determination result is obtained in step (e), the timer is stopped.

(1.) “Set SO to “H”” Raise the output signal SO to "high".

(H) rtw data set” Set data specifying the pulse width tw in the timer.

(S)rtw Has time passed? ” Determine whether the timer value has reached tw. If the determination result is "no", the determination is repeated until a "yes" determination result is obtained.

(nu) "Set SO to 1'Lj" Drop the output signal SO to "low".

With such a program, it is possible to obtain a signal SO having a desired delay time and time width based on the signal Si. However, in this case, td, tw
In order to measure accurately, the timer in the microcomputer is occupied for a long time, and in order to accurately grasp the rising and falling edges of the input signal Si, for example, an external interrupt input port must be used. Soft Ste.
This forces an increase in the number of pumps. The fact that a timer must be used for a long period of time just to obtain such an output signal SO is necessary for microcontrollers that require a lot of work to control the entire circuits of electronic devices such as video tape recorders. This is not a good thing for the computer, and can interfere with general system control work for all devices.

Purpose of the Invention The present invention has been made to solve the above problems.
The present invention aims to provide a new programmable pulse generator that can freely change pulse generation timing and pulse width without unnecessarily complicating the configuration and program of a microcomputer.

Further, as a specific purpose of use of the programmable pulse generator of the present invention, for example, when creating a pseudo vertical synchronizing signal using an RF switching signal as a reference signal for variable speed playback in a video tape recorder, the programmable pulse generator of the present invention may be used to control the video tape recorder. It is conceivable to obtain a pseudo vertical synchronization signal by using the pulse generator of the present invention in a computer.

SUMMARY OF THE INVENTION To achieve the above object, the present invention provides a programmable pulse generator inside a microcomputer. The programmable pulse generator of the present invention includes a reference pulse input circuit that receives a reference pulse, a data setting register, a pulse wide latch circuit that latches pulse width data received from the data setting register, a data setting register, and a pulse wide latch circuit that latches pulse width data received from the data setting register. Measure the time specified by the data transmitted from the launch circuit i'1l1
1, and a pulse generation rate control circuit that controls the programmable timer. When a reference pulse is input to the reference pulse input circuit, the pulse generation rate control circuit causes the programmable timer to receive a delay from the data setting register. The programmable timer measures the time specified by the pulse width data from the pulse wide latch circuit, and generates an output pulse when the time has elapsed. The invention is characterized in that the generation of the output pulse is stopped when the output pulse is turned off.

EXAMPLES Below, the programmable pulse generator of the present invention will be explained in detail according to examples shown in the accompanying drawings.

FIG. 5 is a circuit block diagram showing an embodiment of the programmable pulse generator of the present invention applied to a system control system of a video tape recorder.

1 is a microcomputer for controlling a video tape recorder incorporating the programmable pulse generator of the present invention; 2 is a CPU in the microcomputer 1; 3 is an accumulator in the iJ CPU 2; It functions as a data setting register that sends data and sends pulse width data to a pulse wide latch circuit, which will be described later. However, this microcomputer 1 performs various controls as a system controller of a video tape recorder, and therefore, the accumulator 3 functions as a data setting register only during a very limited and short period of one program cycle. Only.

4 is a ROM, 5 is a RAM, 6 is an input circuit, 7 is an output circuit, 8 is a pulse width latch circuit that temporarily records pulse width data specifying pulse width, 9 is a programmable timer, 10 1 is a pulse generation rate control circuit that controls the pulse wide latch circuit 8 and the programmable timer 9; 11 is a flag register that indicates whether or not one output pulse has been output; 12 is a reference pulse input circuit; 13 is a reference pulse input circuit; It is an AND circuit.

Next, the operation of this microcomputer 1 to generate a nonorus will be explained.

When performing variable speed reproduction of a video signal, an operation permission signal is sent from the CPU 2 to the pulse generation rate control circuit IO.

Then, the pulse generation rate control circuit 10 becomes operational. Note that when performing normal playback, there is no need to create a pseudo vertical synchronization signal (details will be described later), so the operation permission signal is not transmitted to the control circuit 10.6 Next, from the accumulator 3 of the CPU 2 to the programmable timer 9 Delay amount data specifying the delay amount (td) is sent to the programmable timer 9, and the programmable timer 9 enters a state in which the delay amount data is stored. Then accumulator 3
Pulse width data specifying a pulse width (tw) is sent from the pulse wide latch circuit 8 to the pulse width latch circuit 8.

On the other hand, the reference pulse input circuit 12 has R as a reference pulse.
The F switching pulse Rf is input, and a start signal is sent from the reference pulse input circuit 12 to the pulse generation rate control circuit 1 at the rising and falling edges of the reference pulse Rf.
0. Therefore, when the reference pulse (RF switching pulse) Rf rises, an activation signal is sent from the reference pulse input circuit 12 to the pulse generation rate control circuit 10. Then, the pulse generation rate control circuit 10 sends a timing permission signal to the AND circuit 13. This AND circuit 13 is configured to receive a clock signal of, for example, 6 MHz from a clock/clock generator (not shown) in the CPU 2 at one input terminal, and has a clock signal at one input terminal. When the allow signal is received, the clock pulse received at the other input terminal is sent to the programmable timer 9. When the programmable timer 9 receives a clock pulse, it starts counting down.

Then, after starting the countdown, the accumulator 3
When the delay time td specified by the delay amount data received from the programmable timer 9 has elapsed, the programmable timer 9 becomes "0", and at the same time, an overflow signal is sent to the Norms generation rate control circuit IO. Bottom, pulse generation rate control circuit 1
0 raises the output pulse (pseudo vertical synchronization signal) Sv,
At the same time, a control signal is sent to the pulse wide latch circuit 8 and the programmable timer 9, and the pulse width data latched in the pulse wide launch circuit 8 is loaded into the programmable timer 9. When the pulse width data is input to the programmable timer 9, the programmable timer 9 immediately starts a time measurement operation in which the value counts down by one for each cycle of the clock pulse. Then, after the time equal to the pulse width tw has passed after the start of countdown, the count value of the programmable timer 9 becomes rQJ,
An overflow signal is sent to the pulse generation rate control circuit IO. Then, the pulse generation rate control circuit IO lowers the output pulse Sv. This completes the operation of outputting one output pulse Sv. When this operation is completed, the contents of the flag register 11 change from "0" to "1".
The CPU 2 reads the contents of the flag register 11 to confirm that it can start the operation of sending out the next pulse of the output pulse. Then, the next pulse of the output pulse Sv is output by the same operation as described above.

In this embodiment, such operation is repeated every half cycle of the reference pulse. Of course, this operation may be repeated at the same cycle as the reference pulse.

By changing the contents of the data sent from the accumulator 3 to the programmable timer 9 and pulse wide latch circuit 8, the delay amount and pulse width of the output pulse from the reference pulse can be changed to td, td, and pulse width for each pulse, as shown in FIG.
, td2, td3, td4 and twl, t w 2,
It can be replaced with tw3 and tw4. A specific example in which this is necessary will be explained in detail.

In a video tape recorder, depending on the playback speed of the video tape, the 1f raw head may not scan the recording track, causing track misalignment. For example, in high-speed playback mode, the playback head scans across a plurality of recording tracks, and a so-called jumping noise is generated each time the playback signal from the playback head jumps over a track. If this noise occurs at the position of the vertical synchronization signal of the T-variable signal, the reproduced signal from the video tape recorder will disturb the vertical synchronization signal circuit in the television monitor. In such a case, if a pseudo vertical synchronization signal Sv is inserted in place of the vertical synchronization signal disturbed by noise, synchronization errors will not occur in the screen reproduced on the television. In order to create such pseudo vertical pulses (pulses having various timings and widths depending on the playback speed mode), it is best to use a program pulse generator provided in the microcomputer of the present invention.

FIG. 7(A) hypothetically reproduces a reproduction signal in a variable speed reproduction mode of a video tape recorder, and shows a case where tracking noise is generated in the vicinity of the vertical synchronization signal due to track deviation of the reproduction head. FIG. 7(B) shows the pseudo vertical synchronization signal Sv generated by the microcomputer of the present invention.
shows. FIG. 7(C) shows a signal waveform when the reproduced signal in FIG. 7(A) is replaced by a pseudo vertical synchronization signal Sv, and the television monitor is synchronized with this pseudo vertical pulse synchronization signal Sv. .

FIG. 8 is a schematic block diagram of a video tape recorder to which the present invention is applied.

The output signals from the video playback devices Ha and Hb are supplied to a switcher 16 via playback amplifiers 14 and 15.

On the other hand, in synchronization with the motor 17 for rotating the head, 1 rotation is made every rotation.
This one rotation 4<l phase signal PG is obtained from the head I (pg. This signal PG becomes the reference phase signal for forming the RF switching signal Rf in the waveform shaping circuit 18. Furthermore, (
i4'i Rf is supplied to the microcomputer 1 to form the pseudo vertical synchronization signal Sv as described above.

The output of the switcher 16 is passed through a limiter circuit 19 to an FM demodulator 20 that demodulates the FM-modulated luminance signal.
supplied to The video signal demodulated by the FM demodulator 20 is supplied to a clamp circuit 22 via a delay circuit 21 that provides a predetermined amount of delay time for each track, for example. A part of this clamped signal is replaced with a pseudo vertical synchronizing signal by a mixer (or replacement circuit) 23 to obtain a video signal as shown in FIG. 7(C).

Incidentally, although not described, arbitrary outputs of the microcomputer 1 are supplied to various system control circuits.

A programmable pulse generator like the one above is a good idea.
By slightly increasing the program of the system control microcomputer, it is possible to generate an output pulse having a desired pulse width at an arbitrary timing.

According to such a programmable pulse generator,
A microcomputer for system control has a built-in pulse wide latch circuit 8, a programmable timer 9, a pulse generator control circuit 10, etc., and by slightly increasing the microcomputer program, an arbitrary amount of delay can be created for input pulses. It is possible to obtain an output pulse with a pulse width of . In addition, it is not necessary to use a variable resistor or the like to adjust the delay value and pulse width of the output pulse accurately. Further, since a programmable timer, a pulse wide latch circuit, and a pulse generation rate control circuit are specially provided for generating pulses, there is no fear that a large amount of the microcomputer will be occupied for pulse generation.

Effects of the Invention As described above, the programmable pulse generator of the present invention includes a reference pulse input circuit receiving a reference pulse;
A data setting register, a pulse wide latch circuit that latches the pulse width data received from the data setting register, and a programmable timer that measures the time specified by the data transmitted from the data setting register and pulse wide launch circuit. and a pulse generation rate control circuit that controls the programmable timer, and when a reference pulse is input to the reference pulse input circuit, the pulse generator control circuit controls the programmable timer to be specified by the delay amount data from the data setting register. When the time elapses, an output pulse is generated, and then the programmable timer measures the time specified by the pulse width data from the pulse wide latch circuit.
1, and when that time has elapsed, the generation of output pulses is stopped.

Therefore, according to the present invention, the amount of delay of the output pulse from the reference pulse and the pulse width of the output pulse can be arbitrarily set depending on the content of the data sent from the data setting register circuit to the programmable timer and the pulse wide latch circuit. Moreover, the setting contents can be changed for each pulse.

In the embodiment described in 1-1, the present invention was applied to a programmable pulse generator having pseudo vertical synchronization 4B''5 for playback used in the variable speed mode of a video tape recorder, but the programmable pulse generator of the present invention The use of is not limited to this.

[Brief explanation of drawings]

Figures 1 to 4 are for explaining the background technology.
Fig. 1 is a time chart showing an input signal and an output signal to be obtained based on it, Fig. 2 is a circuit diagram showing the first conventional example, and Fig. 3 is a time chart of the circuit shown in Fig. 2. Flowchart I of a program showing an example of a 9th grade 4H program, FIG. 5 is a block diagram showing an example of implementing the programmable pulse generator of the present invention, and FIG. 6 shows an example of the reference pulse and output pulse. The time chart shown in FIG. 7 (A) is a reproduction signal in the variable speed reproduction mode of the video tape recorder, (B) is a pseudo vertical synchronization signal generated by the programmable pulse generator of the present invention, (
C) shows the waveform of a signal obtained by replacing the vertical synchronizing signal of the reproduced signal in (A) with a pseudo vertical synchronizing signal, and FIG. 8 is a schematic block diagram of a video tape recorder to which the present invention is applied. Description of symbols 3 fist/Φ data setting register, 8eeΦ pulse wide latch circuit, 9... fist programmable timer, 10... Φ
Pulse generator 1- Control J'D circuit, 12...Reference pulse input circuit Fig. 1 Fig. 3 Fig. 4

Claims (1)

[Claims] (1)7. (A reference pulse input circuit that receives a quasi-pulse,
a data setting register, a pulse wide latch circuit that latches the pulse width data received from the data setting register, and a programmable timer that measures a time specified by the data transmitted from the data setting register and the pulse wide latch circuit; and a pulse generation rate control circuit that controls the programmable timer, and when a reference pulse is input to the reference pulse input circuit, the pulse generation rate control circuit causes the programmable timer to receive data specified by the delay amount data from the data setting register. Measures the time and generates an output pulse when the time elapses,
A programmable pulse generator characterized in that the programmable timer is then configured to measure a time specified by pulse width data from a pulse wide latch circuit, and stops generating output pulses when the time has elapsed.