JPH0320113B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a magnetic recording/reproducing apparatus that performs recording phase alignment between a recording signal and a head switching signal.

In a magnetic recording/reproducing device (hereinafter referred to as a VTR), it is generally necessary to accurately match the writing phase of a recorded video signal and the rotational phase of a video head to a certain relationship.

The first block diagram of the servo circuit of a conventional VTR
As shown in the figure. Further, the main waveforms are shown in FIGS. 2, 1 to 9.
The vertical synchronization signal a (FIG. 2 1) separated from the recorded video signal in FIG.
This is further input to a monostable multivibrator (hereinafter referred to as monomulti) 2. This monomulti 2 sets the recording phase of the reference synchronization signal b to a predetermined offset with respect to the rotational phase of the video head.
In order to adjust to To, the delay amount t is made variable by the variable resistor 3. Furthermore, the delayed reference signal c (FIG. 2, 3) which is the output of the monomulti 2 passes through the next stage pulse generator 4, and becomes the latch pulse d shown in FIG. 2, 4.

On the other hand, the phase of the video head 6 rotated by the drum motor 5 is detected by the phase detector 7 as a tack pulse e as shown in FIG. This tack pulse e is delayed and shaped by the next-stage monomulti 8 to become the delayed signal f shown in FIG. 2, and further passes through the signal generator 9 to become the head switching signal g with a duty ratio of 50% (FIG. 2, 7). This head switching signal g and the aforementioned latch pulse d are input to a phase comparator circuit 10 composed of a detection counter 13, a latch circuit 14, and a pulse width modulation (hereinafter abbreviated as PWM) circuit 15, as shown in FIG. A pulse width modulation signal (hereinafter referred to as
PWM signal) h is output. This PWM signal h is smoothed by a low-pass filter 11 at the next stage and then applied to the drum motor 5 via a drive circuit 12. Although not shown, the head switching signal g is also supplied to a signal system.

The operation of the phase comparator circuit 10 will be described in detail below. A head switching signal g is input to the reset terminal R of the detection counter 13, and counting of the clock signal i starts at the time of the rise of this signal g. At this time, the count of the detection counter 13 is schematically shown in a trapezoidal waveform as shown in FIG. The detection counter 13 is configured to start counting and automatically stop counting when the maximum value of the dynamic range (countable range of the counter) is reached.

Now, during normal control operation, the control loop operates so that the latch pulse d is located at the center of the dynamic range of the detection counter 13. On the other hand, as a servo device, it is necessary to maintain the writing phase of the recording signal in a constant relationship. Normally, a VTR is set so that the head switching signal g appears at the bottom of the playback screen. As shown in FIG. 3, this means that the vertical synchronizing signal B (signal a in FIG.
The rotational phase of the video head 6 is controlled so that the data is written. This means that both ends of the head switching signal g, which coincides with the rotational phase of the video head 6, occur a certain time before the vertical synchronizing signal a (for example, T ⁰ =6.5H).
= 413 μs before). Therefore, the delay amount t of monomulti 2
was adjusted to set T ⁰ above. Here, the reference synchronization signal b is simultaneously recorded on the tape 16 by a fixed control head and becomes a control pulse 18. The monomulti 8 is provided to match the rotational phase of the task pulse e and the video head 6, and to correct mechanical variations in the mounting position of the phase detector 7, etc.

In the conventional technology described above, after assembling the VTR, a recording signal is input to operate the entire servo device in the recording state, and after reaching a stable state, the monomulti 2 is adjusted to adjust both ends of the head switching signal g. It was necessary to make very complicated recording phase adjustments such as setting ⁰ before the vertical synchronizing signal a.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art described above, and to provide a servo device having a structure with fewer adjustment points and eliminating the need for recording phase adjustment.

The main focus of the present invention is to use a digital phase comparator that operates with an accurate clock signal so that the recording phase of the video signal and the rotational phase of the video head have a predetermined offset phase _T0 without any adjustment. It's about synchronizing.

Examples of the present invention will be described in detail below. An embodiment of the present invention is shown in a block diagram in FIG. 4, and main waveforms of the same figure are shown in FIGS. 1 to 9. In FIG. 4, circuit blocks designated by the same reference numerals as in FIG. 1 have the same functions.

First, the vertical synchronization signal a (Fig. 5 1) passes through the frequency divider circuit 1, becomes the reference synchronization signal b shown in Fig. 5 2, is directly input to the pulse generator 4, and becomes the latch pulse d shown in Fig. 5 3. . On the other hand, the tack pulse e (FIG. 5, 9) from the phase detector 7 passes through the monomulti 8 and becomes the delayed signal f shown in FIG. 5, 8. Here, the delayed signal f is input to the reset terminal R of the expanded tack counter 16. This tack counter 1
6 has both the function of the detection counter 13 shown in FIG.
4 and is applied to the switching signal generator 17. The output of the latch circuit 14 is applied to the next-stage PWM circuit 15, which outputs the PWM signal h (FIG. 5, 4) similarly to FIG.

Here, the output of the PWM circuit 15 is the gate circuit 1
8 and becomes the PWM signal h. Since the detection counter 16 continues counting operation for approximately the period _T3 as shown in FIG. 5, its operation as a detection counter becomes a sawtooth waveform as shown by the broken line in FIG. In this state, there will be a plurality of synchronous phases, which is not preferable. For this purpose, a gate circuit 18 is provided, and a tack counter 17
The output of the PWM circuit 15 is appropriately gated by the output of the upper bit of , and the synchronization phase is set at one point.

Now, the tack counter 16 and the switching signal generator 17
As shown in FIG. 5, the tack counter 16 is first reset by the delay signal f (FIG. 5, 8). At this time, head switching signal g (fifth
In FIG. 7, it is at "H" level. Now, as the delay signal f falls, the tack counter 16 starts counting the input clock signal i. On the other hand, the latch pulse d (Fig. 5 3) has a dynamic range (Fig. 5 5).
The control loop operates so as to be phase-locked to the center of the slope (the slope of the slope). Therefore, if the width of the dynamic range is ^2T2 , the time ^T1 from when the tack counter 17 starts operating until the head switching signal g falls is expressed by the following equation.

T ¹ =T ² -T ⁰ However, T ⁰ is a predetermined time from both ends of the head switching signal g to the vertical synchronizing signal a, as in the conventional circuit.

Therefore, as shown in FIG. 5, when the count value of the tack counter 16 reaches an amount corresponding to ^T1 ,
The head switching signal g may be lowered.
On the other hand, the rising edge of the head switching signal g must similarly be set before ^T0 of the vertical synchronizing signal a. The rising edge of this head switching signal g is a time T ³ (one cycle period of the vertical synchronizing signal a) from the falling edge of the same signal g.
Just delay it.

Next, one embodiment of the tack counter 16 and the switching signal generator 17 is shown in FIG. 6, and the main waveforms of the same figure are shown in FIGS. 1 to 8. In FIG. 6, a clock signal i is input to the r input of the tack counter 16 via an AND gate 19. Now delay signal f
As shown in FIG. 7, the tack counter 16 is reset, and the flip-flop (hereinafter abbreviated as FF) 20 is also set. As a result, the output of the FF 20 becomes a clock gate signal j as shown in FIG. 7b, and the AND gate 19 is opened.

Next, when the delay signal f becomes "L", the tack counter 16 is reset and starts counting. Each bit output of the tack counter 16 is input to AND gates 21 and 22, respectively, which output coincidence pulses k and l at the timings shown in FIGS. 4 and 5, respectively. Therefore, a coincidence pulse k is first output from the AND gate 21, and the FF 23 is reset.
In other words, the head switching signal g is inverted to "L". When the count of the tack counter 16 further advances, a coincidence pulse l is output from the AND gate 22, and the FF20
Reset and set FF23. Therefore
The output j of FF20 becomes “L” and AND gate 19
Close. Further, the head switching signal g (FIG. 7) is inverted to "H". Here, the time from coincidence pulse k to l is set to one cycle ^T3 of the vertical synchronization signal a. Therefore, the tack counter 16
By inverting the head switching signal g at the timing of the above equation ^T1 after starting counting, and then inverting it again after ^T3 has elapsed, both ends of the head switching signal g are always kept at the fixed time ^T0 of the vertical synchronizing signal a. It's in front.

As described above, the latch pulse d is generated directly from the reference synchronizing signal b obtained by dividing the vertical synchronizing signal a, and this latch pulse d is the falling edge T ⁰ of the head switching signal g.
By controlling the phase synchronization later, the first
By removing the monomulti 2 shown in the figure, it is possible to eliminate the need for recording phase adjustment.

In the above embodiment, the start of operation of the tack counter 16 and the falling phase of the head switching signal g are different; however, assuming that the dynamic range 2T ² of the tack counter 16 is 2T ² = 2T ⁰ , T ¹ = 0, that is, the tack counter 16 is The start of operation 16 and the falling phase of the head switching signal g may be made to coincide with each other.

As described above, according to the present invention, the head switching signal is generated by a tack counter, and by using servo control so that the vertical synchronizing signal and the head switching signal have a constant phase relationship, the vertical synchronizing signal, which was conventionally complicated, can be generated. It is possible to provide a magnetic recording device that eliminates the need for recording phase adjustment and establishes an accurate and stable recording phase without adjustment.

Furthermore, since the configuration does not require one monomulti for delay time adjustment, it is possible to provide a magnetic recording device with a configuration that requires fewer external parts such as capacitors and fewer pins, which is suitable for semiconductor integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a servo device according to the prior art, FIGS. 2 1 to 9 are waveform diagrams of main parts for explaining the operation of FIG. 1, and FIG. 3 is a plan view of a tape pattern showing a recording state. FIG. 4 is a circuit configuration diagram showing one embodiment of the servo device according to the present invention, FIGS. 5 1 to 9 are waveform diagrams of the main parts of FIG. 4, and FIG. 6 is a concrete diagram of the switching signal generator of FIG. 4. A circuit diagram showing an example of a configuration, Fig. 7 1
-8 are main part waveform diagrams of FIG. 1... Frequency divider circuit, 2... Mono multi, 10...
Phase comparison circuit, 16... Tack counter, 17...
...Switching signal generator.

Claims (1)

[Scope of Claims] 1. A frequency dividing circuit that divides the frequency of a vertical synchronizing signal in a recorded video signal by two to generate a frequency-divided output having a frequency that is half the frequency of the vertical synchronizing signal, and rotation of a motor that rotates the video head. A detector that detects the phase, a counter that starts counting based on the detection output from the detector, a latch circuit that latches the count value of the counter when the frequency divider circuit generates the frequency divided output, and a counter that is latched by the latch circuit. a control circuit that controls the rotational phase of the motor by generating a pulse width modulation signal having a pulse width according to the latched count value so that the count value becomes a predetermined value; A magnetic recording device comprising: a switching signal generator that generates one cycle of pulses having the same frequency as the frequency divider output as a head switching signal when the counter counts values separated by a certain value.