JPH0648566B2 - Magnetic recording / reproducing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic recording / reproducing apparatus such as a rotary head type video tape recorder in which the rotation of a cylinder motor is digitally controlled by a microcomputer.

[Conventional technology]

Conventionally, a rotary head type magnetic recording / reproducing apparatus such as a video tape recorder and a rotary head type digital audio tape recorder has a plurality of rotary heads, for example, two rotary heads.
The magnetic tape is sequentially helically scanned, and at this time, the head switching based on the head switching signal synchronized with the scanning is used to switch and connect the head in the scanning to a recording circuit or a reproducing circuit to record and reproduce the magnetic tape. .

Further, since this type of magnetic recording / reproducing apparatus controls the speed and phase of the cylinder motor for rotationally driving each head, the speed and phase of the cylinder motor are detected by a detection circuit and the detection signals of both detection circuits. , It is equipped with a cylinder servo circuit that controls the phase.

The speed detection circuit outputs a speed detection pulse signal called an FG signal, that is, a signal whose frequency changes in proportion to the rotation speed of the cylinder motor to the cylinder servo circuit, and the phase detection circuit outputs the PG signal as a PG signal. A so-called phase detection pulse signal, that is, a signal whose phase changes in proportion to the rotation phase of the cylinder motor, is output to the cylinder servo circuit.

Further, the cylinder servo circuit detects a frequency fluctuation of the FG signal to generate an error signal for speed control, that is, a speed error signal (speed error signal), and detects a phase shift of the PG signal to detect a phase shift. An error signal, that is, a phase error signal (phase error signal) is generated, and both error signals are supplied to the drive circuit of the cylinder motor to control the rotation of the cylinder motor.

The FG signal is formed, for example, by shaping a pulse obtained by detecting a magnetic pole change on the peripheral surface of the magnetic plate axially attached to the cylinder motor with a frequency generator, and the frequency is sufficiently higher than the rotation frequency of the cylinder motor. It becomes a high frequency.

For the PG signal, for example, one or more magnetic pieces called PG magnets are attached to the upper surface of the cylinder motor at equal intervals, and the passage of the PG magnets is detected to shape the pulse obtained in the pulse generator coil. The frequency of the PG signal is usually the same as the rotation frequency of the cylinder motor or several times as high as the frequency depending on the number of PG magnets. Normally, two PG magnets are mounted at opposite positions. Is a pulse signal of 50% duty-actor whose level is inverted in a half rotation cycle of the cylinder motor.

By the way, in the case where both the error signals are generated by digital processing and the rotation of the cylinder motor is digitally servoed, for example, as described in the specification and drawings of the application of Japanese Patent Application No. 59-214954, a cylinder is used. The servo circuit is formed by using one micro computer.

Then, in the case where one counter is provided in the microcomputer to form both error signals,
A free-running counter whose count content does not change by reading is provided, and by the counter, the FG signal,
A reference clock signal having a frequency higher than that of the PG signal is counted, and both the leading edge and the trailing edge of the phase reference pulse signal (hereinafter referred to as the REF signal) set to one rotation cycle of the cylinder motor or the cycle of the PG signal, or Either of them resets the free running counter at the cycle of the PG signal.

In addition, the central processing unit (CP
U) is provided with a speed control calculation means and a phase control calculation means, and the speed control calculation means detects a frequency shift of the FG signal from the difference between the count values of the free running counter at the leading edge or the trailing edge of the pulse of the FG signal. Then, the velocity error signal is generated, and the phase control calculation means immediately after the pulse before and / or after the pulse of the PG signal (hereinafter P
It is referred to as "immediately after G signal") from the count value of the free running counter at the leading or trailing edge of the pulse of the FG signal
A phase error of the signal is detected and a phase error signal is generated.

That is, the count value of the free running counter is
The value between the pulse leading edge and the trailing edge of the FG signal becomes the value of each cycle of the FG signal, and the value at the pulse leading edge or trailing edge of the FG signal immediately after the PG signal is the reset timing reference. Is the value of the phase shift amount of the PG signal.

Therefore, the speed control calculating means generates a digital speed error signal from the difference between the count values obtained for each pulse leading edge or trailing edge of the FG signal, and the phase control calculating means calculates the FG signal immediately after the PG signal. A digital phase error signal is generated from the count value at the leading or trailing edge of the pulse.

Then, the speed of the cylinder motor is controlled by the speed error signal, and the phase of the cylinder motor is controlled by the phase control signal.

The speed and phase error signals generated by the speed and phase calculation means are converted into analog signals and supplied to the drive circuit of the cylinder motor.

By the way, if the rotation of the motor fluctuates due to fluctuations in power supply voltage, fluctuations in temperature, fluctuations in load on the cylinder motor, fluctuations in characteristics, or switching of the regeneration mode,
The frequency of the FG signal fluctuates and the pulse leading or trailing edge of the FG signal is input during the reset of the free running counter by the REF signal, or the speed and phase error signals based on the leading or trailing edge of the pulse of the FG signal. A situation occurs in which the REF signal is input during the generation of.

Since the microcomputer cannot perform two types of processing at the same time, the reset of the free running counter and the generation of the speed or phase error signal cannot be performed at the same time, and the reset or the speed or phase error signal is generated. There is a delay in reading the numerical values, making it difficult to accurately control the rotation of the cylinder motor.

Therefore, conventionally, a DC offset signal according to the reproduction mode or the like is added to the phase error signal, and the lock position of the phase of the cylinder motor is set to the reset of the free running counter by the REF signal and the pulse leading edge or trailing edge of the FG signal. Are adjusted so that they do not overlap.

[Problems to be solved by the invention]

By the way, even if the lock position of the phase of the cylinder motor is adjusted by the DC offset signal, the rotation speed of the cylinder motor becomes high and the frequency of the FG signal becomes high, and the processing speed of the microcomputer is compared. In the case of extremely slow time, the phase of the FG signal shifts due to the shift of the lock position of the phase based on the frequency fluctuation of the FG signal, and the reset of the free running counter by the REF signal and the leading or trailing edge of the pulse of the FG signal. There is a problem that the rotation of the cylinder motor cannot be controlled stably and accurately because the overlap easily occurs and the servo is easily disturbed.

In addition, when switching the reproduction mode, it is necessary to adjust the DC offset signal, which makes the operation complicated.

[Means for solving problems]

The present invention has been made with the above points in mind, in which a magnetic tape is sequentially helically scanned by a plurality of rotary heads, and the frequency is proportional to the speed of the cylinder motor for rotational drive of each head. A cylinder servo circuit to which a changing speed detection pulse signal and a phase detection pulse signal whose phase changes in proportion to the phase of the motor are input, while counting a reference clock signal having a higher frequency than the both detection pulse signals, A free running counter reset at the timing of either or both of the pulse front and rear edges of the phase reference pulse signal for phase reference of the motor, and the counter of the pulse leading edge or trailing edge of the speed detection pulse signal. A speed control calculation means for generating a speed error signal of the motor from a numerical value difference; A phase control calculation means for generating a phase error signal of the motor from the count value of the pulse leading edge or trailing edge of the speed detection pulse signal immediately after either or both of the leading edge and the trailing edge, In a magnetic recording / reproducing apparatus for controlling the speed and phase of the motor based on the both error signals, the servo circuit resets the counter at approximately the center between the leading edge or the trailing edge of the speed detection pulse signal. The count value of the counter corresponding to the limit value of the target range of phase control is preset as the upper and lower limit values, and the count value of the counter and the counter value are taken every time the count value of the counter is taken into the phase control calculating means. Phase shift detecting means for detecting a shift of the phase of the motor from the target range based on comparison with upper and lower limit values; From the phase control calculation means, correction signal generation means for repeatedly adding and subtracting a phase fine adjustment value set in advance according to the direction of deviation of the motor phase from the target range, and generating a correction signal for phase control, A magnetic recording / reproducing apparatus, comprising: an adding unit that adds the correction signal to the output phase error signal and outputs the added signal.

[Action]

Therefore, by correcting the phase error signal by the correction signal, the phase of the cylinder motor is always automatically pulled within the target range, and at this time, the pulse of the phase reference signal before and after the pulse of the phase reference signal that resets the free running counter is reset. Either one or both of them are located in the approximate center between the pulse leading edge or trailing edge of the speed detection pulse signal, and the reset of the counter and the generation of the speed and phase error signals do not overlap, and the rotation of the cylinder motor is stable. And it is controlled accurately.

〔Example〕

Next, the present invention will be described in detail with reference to FIGS. 1 to 4 showing one embodiment thereof.

FIG. 1 shows a case where the invention is applied to a video tape recorder or a digital audio tape recorder in which a magnetic tape is alternately helically scanned by two rotating heads separated by 180 °. In the figure, (1) and (2) Is the FG signal, P
Fig. 2 (a), (b) formed by shaping the output pulses of the frequency generator and the pulse generator, which are input terminals for each of the G signals and are provided in the vicinity of the cylinder motor for driving both rotary heads. FG signal and PG signal are input.

The frequency of the FG signal changes in proportion to the speed of the cylinder motor, and the phase of the PG signal changes in proportion to the phase of the cylinder motor.

The level of the PG signal is inverted every half rotation of the cylinder motor.

Further, the frequencies of the FG signal and the PG signal change in accordance with the specified number of revolutions when the specified number of revolutions of the cylinder motor is changed by switching the reproduction mode.

Reference numeral (3) is an input terminal of the REF signal, and the signal output from the reference signal generating circuit, that is, the REF signal having the same cycle as the PG signal is input.

(4) is a one-chip micro computer provided in the cylinder servo circuit, and (5) is a free-running counter built in the computer (4), which outputs the reference clock signal formed inside the computer (4). It is constantly counted and reset by the leading edge of the pulse leading edge of the REF signal at the input terminal (3). (6) is a latch circuit that reads and outputs the count value of the counter (5).
Every time the leading edge of the pulse of the G signal rises, the count value of the counter (5) is read.

(7) is a phase control timing setting circuit to which the FG signal and PG signal of the input terminals (1) and (2) are input, and the phase is set at the timing of the pulse leading edge of the FG signal immediately after the pulse leading edge of the PG signal. Outputs control timing pulse.

Reference numeral (8) is a speed control calculation circuit forming a speed control calculation means, which generates a speed error signal of the cylinder motor from the difference between the count values of the latch circuit (6) and outputs it to the output terminal (9).

(9) is a phase control arithmetic circuit forming the phase control arithmetic means, and generates a phase error signal of the cylinder motor from the count of the latch circuit (6) when the timing pulse of the setting circuit (7) is input. Output.

(10) is a phase error detection circuit forming a phase shift detection means, and when the timing pulse of the setting circuit (7) is input, that is, the count value of the latch circuit (6) is taken into the arithmetic circuit (9). The latch circuit (6) is loaded with the count value, and based on the comparison between the loaded count value and the preset upper and lower limit values, which will be described later, the phase of the cylinder motor from the target range described later. Detect the deviation.

(11) is a correction signal output circuit to which the detection signal of the detection circuit (10) is input, which forms a correction signal generation means, and identifies the direction of the phase shift based on the input detection signal Depending on the phase shift direction, addition and subtraction of a preset constant phase fine adjustment value are repeated to generate a phase control correction signal.

(12) is an adder circuit forming an adder, and an arithmetic circuit
The correction signal of the output circuit (11) is added to the phase error signal of (9), and the phase error signal corrected by the correction signal is output to the output terminal (13).

The reference clock signal formed inside the computer (4) is a signal having a higher frequency than the FG signal and the PG signal.

In addition, the arithmetic circuits (8) and (9) are operated by the computer.
This is performed by software processing of the processing unit (CPU) included in (4).

The counter (5) is configured to count the reference clock signal, the pulse leading edge of the REF signal at the input terminal (3), t _r of FIG. 2 (c), is reset at the timing of t _r ', the At this time, the count value of the counter (5) is reset to 0 at the timings of t _r and t _r ′, as shown in FIG.

Further, the latch circuit (6) is provided at each of the pulse leading edge timings t ₁ , t ₂ , t ₃ , t ₄ , t ₅ , t ₆ , t ₇ , t _{8 of the} FG signal shown in FIG. 2 (a). Operation circuit that captures the count value of the counter (5)
(8), (9), output to the detection circuit (10) and (b) in the same figure.
At the timing t ₃ of the pulse leading edge of the FG signal immediately after the pulse leading edge t ₂ ′ of the PG signal shown in FIG.
(9) Outputs the phase control timing pulse to the detection circuit (10).

Then, the arithmetic circuit (8) is output from the latch circuit (6).
A speed variation of the cylinder motor is detected from the difference between the count values of t ₁ , t ₂ , ..., T ₈ to generate a digital speed error signal, and the digital speed error signal is output to the output terminal (9).

The arithmetic circuit (9), based on the count value output to t ₃ immediately before the pulse of the PG signal edge t ₂ 'from latch (6), digital phase by detecting the phase variation of the cylinder motor An error signal is generated and the error signal is output.

By the way, when the counter (5) is reset by the REF signal and the speed and phase error signals are generated by the FG signal, the computer is controlled by the REF signal and the FG signal.
Since the central processing unit of (4) is interrupted, the computer (4) does not accept other processing for each of the reset and speed of the counter (5) and the processing time required for generating the phase error signal.

That is, the processing time required for resetting the counter (5),
Assuming that the processing time required to generate the velocity error signal and the processing time required to generate the velocity and phase error signals are τ _r , τ _f, and τ _fp, respectively, as shown in FIG. 2 (e),
Between the shaded parts of τ _r from t _r , t _r ′, t ₁ , t ₂ ,
The computer (4) accepts other processing between the shaded portions of τ _f from t ₄ , t ₅ , t ₆ , t ₇ , and t ₈ and between the shaded portions of τ _fp from t ₃ , respectively. Absent.

Note that τ _r , τ _f , and τ _fp are periods that are determined based on the processing speed of the computer (4), and are usually shorter than the half synchronization of the FG signal.

Then, when the rotation of the cylinder motor is controlled by the speed and phase error signals of the arithmetic circuits (8) and (9), the rotation of the cylinder motor fluctuates due to load fluctuation, switching of the regeneration mode, etc. The frequency changes, the lock position of the phase of the PG signal shifts thereafter, the phase of the FG signal shifts from the original phase, and the pulse leading edge of the FG signal and the pulse leading edge of the REF signal match and the servo of the cylinder motor Is disturbed.

Therefore, in this embodiment, as described below, PG
The range of the lock position of the phase of the signal, that is, the target range of the phase control of the cylinder motor is predetermined, and the lock position of the phase of the PG signal is always pulled within the target range regardless of the frequency fluctuation of the FG signal, and the pulse of the REF signal is pulsed. The leading edge is automatically adjusted and controlled approximately at the center between the pulse leading edges of the FG pulse signal so that the pulse leading edge of the REF signal and the pulse leading edge of the FG signal do not overlap.

First, the upper and lower limits of the target range set in the detection circuit (10) will be described.

Now, the REF signal is a t _a the locking position of the phase of the normal PG signal, or pulse leading edge of the REF signal is in the middle between the pulses leading edge of the substantially FG signal position of the third view falls (a), At this time, if the count value of the counter (5) is No as shown in FIG. 7B, if the pulse leading edge of the REF signal and the FG
The range of the phase shift of the PG signal at which the pulse leading edge of the signal does not match and the processing times τ _r and τ ^f and τ _fp do not overlap can be grasped in advance, and this range is t _a
Is within one cycle of the FG signal.

Assuming that the positions of th and tl in FIG. 3 (b) are the positions of the limit of the phase shift of the PG signal, the position of the th where the count value is larger than No, that is, the position of the delay phase is the upper limit. As the position becomes, the position of tl where the count value becomes smaller than No, that is, the position of the lead phase becomes the lower limit position, and th ~
The range of tl becomes the target range of phase control, and th, tl
The count values Nh and Nl at the positions of are the upper and lower limits, respectively.

The upper and lower limits are set in the detection circuit (10) in advance, and the detection circuit (10) causes the setting circuit to set.
Every time the phase control timing pulse of (7) is input, that is, every time the count value of the latch circuit (6) is taken into the arithmetic circuit (9), the count value of the latch circuit (6) and the set value are set. , The lower limit value is compared, and the deviation of the current PG signal phase, that is, the current cylinder motor phase from the target range is detected.

Further, the detection circuit (10) outputs a detection signal indicating the detected phase shift direction to the output circuit (11), and the output circuit (11)
The phase shift direction is grasped at.

By the way, in the output circuit (11), a phase fine adjustment value equal to the variable amount of the phase error signal necessary to shift the phase of the PG signal by a unit amount sufficiently smaller than the target range is set in advance.

Then, when there is a phase shift in the delayed phase direction, the output circuit (11) repeats addition of the phase fine adjustment value for each input of the detection signal and accumulates the phase fine adjustment value until the phase shift becomes zero. The formed phase correction signal is output.

Further, in the case of phase shift in the advance direction, the output circuit (11) repeats subtraction of the phase fine adjustment value for each input of the detection signal until the phase shift becomes 0, and the phase fine adjustment value is gradually reduced. The formed phase correction signal is output.

Then, the addition circuit (12) adds the phase correction signal of the output circuit (11) to the phase error signal of the arithmetic circuit (9), and at this time, the phase of the PG signal is always within the target range by the phase correction signal. The phase is automatically pulled into and finely adjusted.

That is, the detection circuit (10), the correction circuit (11), the addition circuit (12)
Operates according to the flow chart of FIG. 4, and every time the output of the phase control timing pulse, the count value of the counter (5) is compared with the lower limit value and then with the upper limit value. The phase fine adjustment value ΔE is subtracted from the current phase correction signal Ei to form a new phase correction signal Ei,
If it is larger than the upper limit value, the phase fine adjustment value ΔE is added to the current phase correction signal Ei to form a new phase correction signal Ei. In the target range, the fine adjustment value ΔE is not added or subtracted, and the current phase correction signal Ei is held.

Furthermore, the phase correction signal Ei is added to the phase error signal Ep,
The phase of the cylinder motor is controlled by the signal formed by the addition, that is, the corrected phase error signal (Ep + Ei), and the PG signal is pulled into the target range.

In addition, in the case of FIG. 1, based on the setting of the target range, P
The phase of the G signal is locked at the position shown in FIG. 2 (b), that is, the pulse leading edge of the REF signal is pulled to t ₂ 'which coincides with the trailing edge of the FG signal.

Then, since the phase of the PG signal is always pulled into the target range, the pulse leading edge of the REF signal is always located approximately in the center between the pulse leading edges of the FG signal. If the pulse leading edge of the REF signal and the pulse leading edge of the FG signal do not match, the counter
The reset of (5) and the generation of the speed and phase error signals do not overlap with each other, so that the disturbance of the servo can be eliminated and the cylinder motor can be stably and accurately controlled.

Also, even if the playback mode is switched, the lock position of the phase of the cylinder motor is automatically adjusted, and the reset of the counter (5) and the generation of the speed and phase error signals do not overlap.
The conventional DC offset signal eliminates the need for adjustment and simplifies the operation.

When resetting the counter (5) and reading the count value by the trailing edge of the REF signal or FG signal, or when resetting the counter (5) both before and after the pulse of the PG signal, etc. Of course, it can be applied.

Further, it is needless to say that the present invention can be applied to the case where the cycle of the REF signal is different from that of the embodiment and the case where the number of the rotating heads is different from that of the embodiment.

〔The invention's effect〕

As described above, according to the magnetic recording / reproducing apparatus of the present invention,
By correcting the phase error signal with the correction signal,
The phase of the cylinder motor is always automatically pulled within the target range, and at this time, the free running counter is reset. Before the pulse of the phase reference signal, the trailing edge, or both, is before the pulse of the speed detection pulse signal. It is located approximately in the center between the edge or the trailing edge, and the reset of the counter and the generation of the speed and phase error signals do not overlap with each other, so that the cylinder motor can be stably and accurately controlled.

[Brief description of drawings]

1 to 4 show a magnetic recording / reproducing apparatus 1 according to the present invention.
FIG. 1 shows a block diagram of an embodiment, and FIG. 2 (a).
~ (E) is a timing chart for explaining the operation, Fig. 3 (a),
(b) is a timing chart for explaining the target range, and FIG. 4 is a flow chart for explaining the operation. (5) …… Free running counter, (8) …… Speed control arithmetic circuit, (9) …… Phase control arithmetic circuit, (10) …… Phase error detection circuit, (11) …… Correction signal output circuit, ( 12) …… Adding circuit.

Claims (1)

[Claims] 1. A magnetic tape is sequentially helical-scanned by a plurality of rotary heads, and a speed detection pulse signal whose frequency changes in proportion to the speed of a cylinder motor for rotational driving of each head and a phase of the motor. A cylinder servo circuit to which a phase detection pulse signal whose phase changes proportionally is input, and a pulse of a phase reference pulse signal for counting the phase of the motor while counting a reference clock signal having a higher frequency than the detection pulse signals. A speed error signal of the motor is generated from the difference between the count value of the free running counter reset at the timing of either or both of the leading edge and the trailing edge and the counter value of the pulse leading edge or trailing edge of the velocity detection pulse signal. And a speed control calculation means for controlling the phase detection pulse signal And a phase control calculation means for generating a phase error signal of the motor from the count value of the counter at the pulse leading edge or trailing edge of the speed detection pulse signal, and the speed and phase of the motor based on the both error signals. In the controlled magnetic recording / reproducing apparatus, the servo circuit is provided with a counter of the counter corresponding to a limit value of a target range of phase control in which the counter is reset at approximately the center between the pulse leading edge or trailing edge of the speed detection pulse signal. The count value is preset as upper and lower limits, and every time the count value of the counter is taken into the phase control computing means, the phase of the motor is changed based on the comparison between the count value of the counter and the upper and lower limits. Phase shift detecting means for detecting a shift from the target range, and a phase shift detecting means for detecting the shift of the phase of the motor from the target range for each detection of the phase shift detecting means. And a subtraction of a preset phase fine adjustment value are repeated to generate a correction signal for phase control, and a correction signal is added to the phase error signal output from the phase control calculation means. A magnetic recording / reproducing apparatus, comprising: