JPH0779455B2 - Video tape recorder playback device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproducing apparatus for a novel video tape recorder, and more particularly, to a pulse generation timing and a pulse width without unnecessarily complicating a microcomputer configuration and a program. The present invention aims to provide a novel video tape recorder reproducing apparatus that can be changed to

More specifically, the present invention provides a reproducing apparatus provided in a microcomputer for controlling a reproducing system of a video tape recorder.

2. Background Art and its Problems When a signal So having a predetermined pulse width tw after being delayed by a certain time td from a certain signal Si as shown in FIG. 1 is obtained by a special circuit, for example, a circuit as shown in FIG. Need. In FIG. 2, AND1 to AND3 are AND circuits, and the input signal Si is input to one input terminal of each of the first and second AND circuits AND1 and AND2.
The output signals Sb and Sd of AND2 and AND2 are input to the third AND circuit AND3, and the signal So is obtained from the AND circuit AND3. INV1 and INV2 are inverters, the first inverter INV1 receives the input signal Si at its input terminal, and the output terminal is connected to one end of the first variable resistor VR1 and the second inverter INV2.
Connected to the input terminal of. The first variable resistor
The other end of VR1 is connected to the anti-ground side terminal of the capacitor C1 whose one end is grounded and one end of the first resistor R1, and the other end of the resistor R1 is the other input of the first AND circuit AND1. It is connected to the terminal. The output terminal of the second inverter INV2 is connected to one end of a second variable resistor VR2, and the other end of the variable resistor RV2 has a second resistor and a terminal on the anti-ground side of a capacitor C2 whose one end is grounded. It is connected to one end of R2. The other end of the resistor R2 is connected to the other input terminal of the second AND circuit AND2.

FIG. 3 is a time chart for explaining the operation of the circuit shown in FIG.

As is clear from FIG. 3, the signal Sa applied to the other input terminal of the first AND circuit AND1 (the input terminal on the side opposite to the terminal to which the input signal Si is applied) is the input signal Si being “low”.
Keeps "high" when. Then, when the input signal Si is inverted from “low” to “high”, the level of the signal Sa gradually decreases. Therefore, the output signal Sb of the first AND circuit AND1
Rises when the input signal Si rises from "low" to "high". Then, when the level of the signal Sa reaches a certain value or less, the signal Sb is inverted from “high” to “low”. The pulse width tb of this signal Sb is determined by the time constant of the capacitor C1 and the variable resistor VR1.

Also, the other input terminal of the second AND circuit AND2 (input signal
Signal Sc of the input terminal on the opposite side of the input terminal where Si is input)
Keeps "low" when the input signal Si is "low", and gradually increases the level of the signal Sc when the input signal Si becomes "high". Then, when the level of the signal Sc exceeds a certain value, the output signal Sd of the second AND circuit AND2 which is "low"
Flips to "high". Time td from when the input signal Si rises to "high" to when the signal Sd rises to "high"
Is determined by the time constant of the second variable resistor VR2 and the second capacitor c2. Then, the third AND circuit AND3 that outputs the logical product signal of the signals Sb and Sd is
The rising pulse width is tw (tb−
The output signal So of td) can be generated.

As described above, the signal to having a predetermined pulse width tw delayed by a certain time td from a certain signal Si can be realized by the circuit shown in FIG. However, in the case of configuring such a circuit, a relatively expensive component such as a resistor and a variable resistor is required in addition to an AND circuit and a logic circuit of an inverter, which causes an increase in cost. Of course, a fixed resistor can be used instead of the variable resistor, but the time td, tw
A variable resistor for adjustment is indispensable for achieving high accuracy, and an increase in cost cannot be avoided. Moreover, adjustment work is required, and the labor of the work cannot be ignored.

Therefore, it is conceivable to use a microcomputer without using the above hardware circuit. in this case,
In order to obtain the target pulse signal So, it is necessary to add a program as shown in FIG. 4 as software of the microcomputer. This program (a)
The explanation of (nu) is as follows.

(A) “So is set to“ L ”.” The output signal So is reset to “L” as an initial condition.

(B) “Data set for td” Set the data that specifies the delay time td in the timer.

(C) “Did Si rise?” It is determined whether the input signal Si has risen from “low” to “high”. If the determination result is “NOW”, the determination is repeated until the determination result of “YES” is obtained.

(D) "Timer start" When the result of the determination in step (c) is "yes", the time measurement by the timer is started.

(E) "Is td time passed?" It is determined whether the timer value has reached td. When the determination result is “NOW”, the determination is repeated until the determination result of “YES” is obtained.

(F) "Timer stop" When the judgment result of "yes" is obtained in step (e), the timer is stopped.

(G) “Set So to“ H ”” Output signal So is raised to “high”.

(H) “Data set for tw” Set the data that specifies the pulse width tw in the timer.

(I) "Is tw time passed?" It is determined whether the timer value has reached tw. If the determination result is “NOW”, the determination is repeated until the determination result of “YES” is obtained.

(Nu) "Set So to" L "" Output signal So falls to "low".

With such a program, a signal So having a desired delay time and time width can be obtained based on the signal Si. However, in this case, the timer in the microcomputer is occupied for a long time in order to accurately measure td and tw, and in order to accurately grasp the rising edge of the input signal Si, for example, an external interrupt is required. It is necessary to increase the number of steps of software, such as having to use a built-in input port. The fact that there is an operation in which the timer is used exclusively for a long time only to obtain such an output signal So means that a microcomputer that requires a lot of work for controlling each circuit of electronic equipment such as a video tape recorder. However, it may hinder the general system control work of the entire device.

OBJECT OF THE INVENTION The present invention has been made to solve the above problems,
RF switching signal for variable speed reproduction by freely changing the pulse generation timing and pulse width without complicating the structure and program of the microcomputer for controlling the system for reproducing the video tape recorder. It is an object of the present invention to provide a novel video tape recorder reproducing apparatus capable of obtaining a pseudo vertical synchronizing signal using the reference signal as a reference signal.

SUMMARY OF THE INVENTION To achieve the above object, a reproducing apparatus for a video tape recorder of the present invention receives a reference pulse input circuit for receiving a reference pulse synchronized with a head switching signal, a data setting register, and a data setting register. A pulse wide latch circuit for latching pulse width data, one programmable timer for measuring a time designated by the data transmitted from the data setting register and the pulse wide latch circuit, and pulse general rate control for controlling the programmable timer At least a circuit, the pulse generator control circuit, when the reference pulse is input to the reference pulse input circuit, causes the programmable timer to measure a time designated by the delay amount data from the data setting register, Suspected output pulse when time passes Generates a similar vertical sync signal, then causes the programmable timer to measure the time specified by the pulse width data sent from the pulse wide latch circuit, and when that time has elapsed, generates a pseudo vertical sync signal which is an output pulse. And the pseudo vertical sync signal is replaced with the vertical sync signal in the reproduced video signal during variable speed reproduction of the video tape recorder, and the reference pulse input circuit, the data setting register circuit, and the pulse wide The latch circuit, the programmable timer, and the pulse-selenate control circuit are provided in a microcomputer for a reproducing system controller.

Embodiment Hereinafter, a reproducing apparatus of a video tape recorder of the present invention will be described in detail according to an embodiment shown in the accompanying drawings.

FIG. 5 is a circuit block diagram showing one embodiment of the reproducing apparatus of the video tape recorder of the present invention applied to the system control system of the video tape recorder.

1 is a video tape recorder control microcomputer with a built-in programmable pulse generator,
Reference numeral 2 is a CPU in the microcomputer 1, 3 is an accumulator in the CPU 2, and the accumulator 3 sends delay amount data to a programmable timer described later, or sends pulse width data to a pulse wide latch circuit described later. Function as a data setting register. But,
The microcomputer 1 performs various controls as a playback system controller of a video tape recorder, and therefore the accumulator 3 functions as a data setting register for a very short period of time in one program cycle. Only inside.

4 is a ROM, 5 is a RAM, 6 is an input circuit, 7 is an output circuit, 8 is a pulse wide latch circuit for temporarily storing pulse width data designating a pulse width, 9 is a programmable timer,
Reference numeral 10 is a pulse generator control circuit for controlling the pulse wide latch circuit 8 and programmable timer 9, 11 is a flag register indicating whether or not one output pulse 1 has been output, 12 is a reference pulse input circuit, and 13 is a reference pulse input circuit. And circuit.

Next, the operation of the microcomputer 1 for generating a pseudo vertical pulse will be described.

When the variable speed reproduction of the video signal is performed, an operation permission signal is sent from the CPU 2 to the pulse generator control circuit 10. Then, the pulse generator control circuit 10 becomes operable. In the case of normal reproduction, there is no need to generate a pseudo vertical synchronizing signal (details will be described later), so the operation permission signal is not transmitted to the pulse generator control circuit 10.
Next, the delay amount data designating the delay amount (td) is sent from the accumulator 3 of the CPU 2 to the programmable timer 9,
The programmable timer 9 is in a state of storing the delay amount data. Thereafter, pulse width data designating the pulse width (tw) is sent from the accumulator 3 to the pulse wide latch circuit 8.

On the other hand, the RF switching pulse Rf is input to the reference pulse input circuit 12 as a reference pulse.
A starting signal is sent from the reference pulse input circuit 12 to the pulse generator control circuit 10 when Rf rises and falls. Therefore, when the reference pulse (RF switching pulse) Rf rises, a start signal is sent from the reference pulse input circuit 12 to the pulse generator control circuit 10.
Then, the pulse generator control circuit 10 to the AND circuit 13
Sends a time measurement permission signal to. This AND circuit 13 is configured to receive a clock pulse of, for example, 6 MHz from a clock pulse generator (not shown) in the CPU 2 at one input terminal, and at the other input terminal when receiving a time-allowing signal at that one input terminal. The received clock pulse is sent to the programmable timer 9.

The programmable timer 9 counts down when receiving a clock pulse. When the delay time td designated by the delay amount data received from the accumulator 3 has elapsed after the countdown was started, the programmable timer 9 is set to "0".
At the same time, the overflow signal is sent to the pulse generator control circuit 10. Then, the pulse general control circuit 10 raises the output pulse (pseudo vertical synchronizing signal) Sv, and at the same time, sends a control signal to the pulse wide latch circuit 8 and the programmable timer 9 to be latched in the pulse wide latch circuit 8. The pulse width data is loaded into the programmable timer 9.

Immediately after the pulse width data is input, the programmable timer 9 starts the time measurement operation in which the value counts down by one for each cycle of the clock pulse. Then, when the same time as the pulse width tw elapses after the countdown is started, the count value of the programmable timer 9 becomes “0”,
An overflow signal is sent to the pulse generator control circuit 10. Then, the pulse generator control circuit 10 causes the output pulse Sv to fall.

This completes the operation of outputting the one-pulse output pulse Sv. When this operation is completed, the content of the flag register 11 is switched from "0" to "1", and the CPU 2 can start the operation of sending the next one pulse of the output pulse by reading the content of the flag register 11. To confirm. Then, the output pulse Sv
The next one pulse of is output.

Such an operation is repeated every half cycle of the reference pulse in this embodiment. Of course, this operation may be repeated at the same cycle as the cycle of the reference pulse.

By changing the contents of the data sent from the accumulator 3 to the programmable timer 9 and the pulse wide latch circuit 8, as shown in FIG. 6, the delay amount and pulse width of the output pulse from the reference pulse are td ₁ , T
It can be changed to d ₂ , td ₃ , td ₄ and tw ₁ , tw ₂ , tw ₃ , tw ₄ . A specific example that needs to be done in this way will be described in detail.

In the video tape recorder, the reproducing head may not scan the recording track and a track shift may occur depending on the reproducing speed of the video tape. For example, in the high-speed reproduction mode, the reproduction head scans over a plurality of recording tracks, and so-called jumping noise is generated every time the track jumps over the reproduction signal from the reproduction head. When this noise occurs at the position of the vertical synchronizing signal of the reproduced signal, the reproduced signal from the video tape recorder disturbs the vertical synchronizing signal circuit in the television monitor. In such a case, if the pseudo vertical synchronizing signal Sv is inserted in place of the vertical synchronizing signal disturbed by noise, periodic disturbance does not occur in the screen reproduced by the television. The present invention is to create such pseudo vertical pulses (pulses having various timings and widths according to the reproduction speed mode).

FIG. 7 (A) shows a case where a reproduction signal in the variable speed reproduction mode of the video tape recorder is hypothesized, and tracking noise is generated in the vicinity of the vertical synchronization signal due to track deviation of the reproduction head. FIG. 7B shows the pseudo vertical synchronizing signal Sv generated by the microcomputer of the present invention. FIG. 7C shows a signal waveform when the reproduction signal of FIG. 7A is replaced by the pseudo vertical synchronizing signal Sv, and the television monitor is synchronized with the pseudo vertical pulse synchronizing signal Sv.

FIG. 8 is a schematic block diagram of a video tape recorder to which the present invention is applied.

The output signals from the video playback heads Ha and Hb are playback amplifiers 1
It is supplied to the switcher 16 via 4 and 15. On the other hand, the rotation phase signal PG is obtained from the head Hpg once for each rotation in synchronization with the motor 17 for rotating the head. This signal PG serves as a reference phase signal that forms the RF switching signal Rf in the waveform shaping circuit 18. Further, the signal Rf is supplied to the microcomputer 1 to form the pseudo vertical synchronizing signal Sv as described above.

The output of the switcher 16 is supplied via a limiter circuit 19 to an FM demodulator 20 which demodulates the FM modulated luminance signal. The video signal demodulated by the FM demodulator 20 is, for example, a delay circuit that gives a predetermined delay time for each track.
It is supplied to the clamp circuit 22 via 21. A part of this clamped signal is fed to the mixer (or replacement circuit) 23.
Is replaced with the pseudo vertical synchronizing signal by FIG. 7 (C).
To obtain a video signal such as

Although not described, any output of the microcomputer 1 is supplied to various system control circuits.

According to the reproducing apparatus of the video tape recorder as described above,
An output pulse having a desired pulse width can be generated at an arbitrary timing by slightly increasing the program of the microcomputer for system control.

Further, the system control microcomputer 1 is provided with a pulse wide latch circuit 8, a programmable timer 9, a pulse generator control circuit 10 and the like, and by increasing the program of the microcomputer a little, an arbitrary delay amount with respect to an input pulse can be obtained. The output pulse having any pulse width can be obtained.

Then, it is not necessary to use a variable resistor or the like to adjust the delay amount and pulse width of the output pulse and to adjust it.

In addition, since a programmable timer, a pulse wide latch circuit, and a pulse general control circuit are specially provided to generate a pulse, there is no fear that the microcomputer will be largely occupied for the pulse generation.

As described above, according to the present invention, the data setting register circuit is changed to the programmable timer and the pulse wide latch circuit without complicating the structure and program of the reproducing system controller microcomputer. The amount of delay of the pseudo vertical synchronizing signal, which is an output pulse, from the reference pulse synchronized with the head switching signal and the pulse width of the pseudo vertical synchronizing signal can be arbitrarily set according to the content of the data to be sent, and each pulse You can also change the settings.

[Brief description of drawings]

1 to 4 are for explaining the background art,
FIG. 1 is a time chart showing an input signal and an output signal to be obtained based on it, FIG. 2 is a circuit diagram showing a first conventional example, and FIG. 3 is a time chart of the circuit shown in FIG. FIG. 4 is a flow chart of a program showing a second conventional example, FIG. 5 is a block diagram showing an example of an embodiment of a reproducing apparatus for a video tape recorder of the present invention, and FIG. 6 shows an example of a reference pulse and an output pulse. 7A is a time chart, FIG. 7A is a reproduction signal in the variable speed reproduction mode of the video tape recorder, FIG. 7B is a pseudo vertical synchronizing signal generated by the reproduction apparatus of the video tape recorder of the present invention, and FIG. FIG. 8 is a schematic block diagram of a video tape recorder to which the present invention is applied, showing the waveforms of signals obtained by replacing the vertical sync signal of the reproduction signal with the pseudo vertical sync signal. Explanation of symbols 3 ... Data setting register, 8 ... Pulse wide latch circuit, 9 ... Programmable timer, 10 ... Pulse generator control circuit, 12 ... Reference pulse input circuit

Claims (1)

[Claims] 1. A reference pulse input circuit for receiving a reference pulse synchronized with a head switching signal, a data setting register, a pulse wide latch circuit for latching pulse width data received from the data setting register, and the data setting register. And at least one programmable timer for measuring a time designated by the data transmitted from the pulse-wide latch circuit, and a pulse-generate control circuit for controlling the programmable timer. When the reference pulse is input to the pulse input circuit, the programmable timer is caused to measure the time specified by the delay amount data from the data setting register, and when that time has elapsed, a pseudo vertical synchronization signal that is an output pulse is generated. , Then on the programmable timer above The time specified by the pulse width data sent from the pulse wide latch circuit is measured, and when that time has elapsed, the generation of the pseudo vertical sync signal that is the output pulse is stopped, and the pseudo vertical sync signal is transferred to the video tape recorder. The reference pulse input circuit, the data setting register circuit, the pulse wide latch circuit, the programmable timer, and the pulse general rate control circuit are adapted to replace the vertical synchronizing signal in the reproduced video signal during variable speed reproduction. A reproducing apparatus for a video tape recorder, which is provided in a microcomputer for a reproducing system controller.