JPH02237487A - Digital servo equipment - Google Patents

Abstract

PURPOSE:To widen the lead-in range of an apparatus by making the amplitude of a phase error signal larger than that of a speed error signal, by dividing said phase error signal into 1/n, and thereafter by combining sid phase error signal with said speed error signal. CONSTITUTION:An inputted FG signal is divided in half by software to generate a speed error signal, and further divided in half to generate a phase error signal. Then, said phase error signal and speed error signal are combined to output the control signal of a cylinder motor. That is, said control signal is generated so that the amplitude of said phase error signal becomes larger. Also, conversion gains {the ratio of the change of an error signal level to the change of a phase difference (time difference)} at the time of generating both error signals are the same, i.e., the lead-in range of an apparatus can be set widely.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a digital servo device for controlling the rotation of a capstan motor and a cylinder motor in a video tape recorder (VTR) or the like.

(Example) Conventional technology, for example, Japanese Patent Application Laid-open No. 63-211408 (GO5D 13
/62) shows an example of a digital servo device used in VTRs and the like. In this example, the configuration is as shown in Figure 2. (1) is a means for creating a phase error signal, and (2) is a means for creating a speed error signal.
Outputs an error signal with bit amplitude. (3) is a division voltage (18)'\- stage to make the conversion gain (change in amplitude/change in phase difference) in the phase error signal smaller than that in the speed error signal, and (・1) is the addition It is a means.

That is, the phase error signal created with 11 bits is divided into 18 by taking the upper 8 bits, added to the 11-bit speed error signal, and output.

(c) Problems to be Solved by the Invention In the above configuration, the phase error signal is created with the same number of bits as the speed error signal, and then the voltage is divided and added to the speed error signal in order to reduce the conversion gain. In some cases, the amplitude of the error signal becomes small, and the phase pull-in range becomes narrow.

(2) Means for Solving the Problems In the present invention, the amplitude of the phase error signal is created to be larger than that of the speed error signal, and the amplitude is divided into 8 parts and added to the speed error signal.

(E) Effect Therefore, by dividing the voltage to stabilize the servo, the conversion gain of the phase error signal can be made smaller than that of the speed error signal, and the amplitude of the phase error signal can be prevented from becoming too small. . Therefore, the pull-in range can be widened.

(f) Example Embodiments of the present invention will be described below with reference to the drawings.

As an example, regarding a cylinder servo device of a VTR,
explain. This device is composed of a one-chip microcomputer (HD6305Z).

The microcomputer (20) has C as shown in Figure 3.
P U (21), ROM (22), register (or R
AM) (23), an input/output port (24), a first timer counter (25), a second timer counter (reference counter) (26), and the like. Figure 3 shows a cylinder motor microcomputer, in which the FG signal of the cylinder motor is input to the input capture interrupt terminal (2
7) is an interrupt terminal (2) that allows the vertical synchronization signal to be masked.
8), the PG signal of the cylinder motor is also applied to the non-mascarable interrupt terminal (29). Also, VTR
A signal indicating the mode of operation is also provided.

A control signal supplied to the drive circuit of the Schilling motor is applied from the input/output port (24) to the D/A conversion circuit (14).

The counts of the first and second timer counters (25) and (26) change at a cycle of 1 μsec in relation to the clock (4MHZ) of the microcomputer (20). and the first
The timer counter (25) is related to the input capture interrupt, and the second timer counter (26) generates an interrupt when the set value and the counted value match (counter match interrupt), and is reset to prevent its overflow. It is now possible to change the cycle.

Further, during recording, the second timer counter (26) is preset to a predetermined value by the vertical synchronization signal so that the count of the second timer counter (26) has a predetermined relationship with the vertical synchronization signal.

Next, creation of a phase error signal and a speed error signal will be explained with reference to FIGS. 4 to 7. Both the phase error signal and the speed error signal are created based on the motor's FG signal.

When the FG signal (a) (related to the rotational speed of the motor) falls, an input capture interrupt is performed.

That is, the count value (a) of the first timer counter (25) at that time is first stored in an input capture register (not shown). This is because the microcomputer (20) cannot specify what operation it is performing at the falling edge of the FG signal (a), and the first
This is because if the count value of the timer counter is memorized, it is not possible to accurately measure the phase difference.

When the operation being performed at the falling edge of the FG signal (A) is completed, interrupt processing of the FG signal is performed. In this interrupt processing, the first timer counter (25) is reset when this interrupt processing is started, and the timer data (b) at that time is stored in register R2 (71
) Also, the data (a) of the input capture register is stored in register R1, and the count value (g) of the reference timer (26) at the timing of resetting the first timer counter (25) is stored in register R5 (72). (73)
.

Phase difference data (TP) between the phase reference (c) (reset timing of the reference timer (26)) and the falling edge of the FG signal (a) can be obtained as shown in the following equation using the above data.

TP"g- (ba-a) ...... (1
) A phase error signal is created from this phase difference data (TP) as follows. As shown in (2), phase bias (TCP). Phase lock range (TS
P), phase error signal (DPI) (n bits), then T P< T When CP, DPI=OT P> T
DP+T When SP DPH=2”-1TDP+TS
When P≧TP≧TDP (2) This operation is shown in (75) to (79) in FIG. In the example, n is 13.

The speed error signal is generated by measuring the period (TFG) of the FG signal (a) (FIG. 6) by the first timer counter (25) and based on this data.

In the case of a speed error signal, one piece of data is created by two falling edges of the FG signal. That is, as shown in FIG. 6, the period (TFG) of the FG signal (a) can be determined as shown in the following equation.

TFG = (C-0) + (ba-a) = (3) In other words, in the same way as when calculating the phase difference data (TP), at the falling timing of the FG signal (a), write the following information to the input capture register: The first at this falling timing
The count value of the timer counter (25) is stored. FG
When the operation of the microcomputer (20) at the time of the signal falling ends, an interrupt operation is performed by the FG signal. By performing the operations shown in FIG. 7 (9l) to (94), the FG period (TFG) can be accurately measured regardless of the operating state of the microcomputer.

As shown in Figure 6, velocity bias (TDS),
Speed lock range (TSS), speed error signal (D
SP), the phase error signal is created from the FG period data (TFG) as follows (in the example, m=11
).

T FG< When T DS DSP=OT FG>
When T os+”r ss, D SP=2”-1T
DS ten T When 55≧TFG≧TDS (4
) This operation is shown in (95) to (99) in FIG. After creating the speed error signal DSP, the data (c) and (d.) are transferred to registers R3 and R4, respectively, for use in the next FG interrupt process (see Fig. 7).
100) (101)). Then, return to the original process (10
2).

In practice, the frequency of the manually inputted FG signal is divided into 8 to create a speed error signal, and the frequency is further divided into 18 to create a phase error signal. Assuming that the FG frequency at steady state is 720Hz, it is 360Hz for the velocity system and 180Hz for the phase system.
Servo will be performed at the sampling frequency of

Then, the phase error signal and speed error signal created as described above are combined to output a control signal for the cylinder motor.

Here, as described above, the phase error signal has an amplitude of 13 bits, and the speed error signal has an amplitude of 11 bits. In other words, the amplitude of the phase error signal is created to be larger. The conversion gain (ratio of change in error signal level to change in phase difference (time difference): slope in FIGS. 4 and 6) when creating both error signals is the same (see FIG. 3).

This phase error signal has an amplitude of 18 by using the upper IO bits, and the conversion gain also decreases (the slope becomes gentler). In other words, as in the conventional example, even if the voltage is divided by '8', the phase error signal still has an amplitude of 10 bits, and a wide pull-in range can be set.

Then, the error signal after adding the phase error signal and the speed error signal is clipped to a 12-bit signal ((1 2
``-1), the level is set to (1211-1)), it will be output from the CPU.

(G) Effects of the Invention As described above, according to the present invention, the phase error signal is created to have a larger amplitude than the speed error signal, and then the voltage is divided and added to the speed error signal. Therefore, the amplitude of the phase error signal after voltage division can be made sufficiently large, and the pull-in range can be expanded.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional example, FIG. 3 is an explanatory diagram showing the relationship between phase error and speed error signals, and FIGS. Figure 6,
FIG. 7 is an explanatory diagram illustrating creation of an error signal. (1)...Phase error signal creation means, (2)...Speed error signal creation means, (4)...Addition means.

Claims (1)

[Claims] (1) In a digital servo device that creates a phase error signal and a speed error signal by measuring the phase difference or period using the count value of a counter that counts a predetermined clock signal, the amplitude of the phase error signal is calculated as the amplitude of the speed error signal. A digital servo device is created by dividing the phase error signal into 1/n and then combining it with the speed error signal.