JPH0557831B2 - - Google Patents

Description

[Detailed description of the invention] (b) Industrial application fields The present invention relates to a phase control device.

(b) Prior Art A video tape recorder (VTR) for recording and reproducing video signals is equipped with a cylinder motor that drives a rotating head and a capstan motor that transports a magnetic tape. The speed and phase of the rotation of these cylinder motors and capstan motors are controlled. In particular, phase control during reproduction is important for tracking of the rotating head.

However, in special situations, various characteristics may be improved by not performing phase control. For example, in a helical scan VTR, in an intermittent slow playback mode in which the tape is moved intermittently and still playback and normal playback are alternately repeated, the cylinder motor only performs speed control and does not perform phase control. This is because the period of the horizontal synchronization signal reproduced differs between still reproduction and normal reproduction (because the relative speed changes), so if this is not done, the reproduced image will be subject to lateral wobbling. To prevent this lateral vibration, phase control is canceled and
The rotational speed of the cylinder motor is accelerated or decelerated in accordance with the still playback and normal playback conditions.

In such a case, a problem arises when there is a transition from a mode in which phase control is performed to a mode in which it is not performed, or vice versa. In other words, when changing the mode from normal playback mode to intermittent slow playback mode (or vice versa),
The problem is how to set the phase error voltage supplied to the motor drive circuit.

Conventionally, when starting the motor,
Similar to the method adopted in Publication No. 40650 (G05D13/62), a signal at a predetermined level is applied as a phase error signal when phase control is not performed.

However, in such a conventional example, discontinuity occurs in the phase error signal, and it takes time to achieve phase lock when the mode changes between normal playback and intermittent slow playback as described above, and the color synchronization of the video circuit may be lost. .

(c) Problems to be solved by the invention In other words, in a configuration in which only a signal at a predetermined level is applied as a phase error signal when phase control is not performed, phase control cannot be performed from the mode in which phase control is being performed. When the mode is changed, the phase error signal becomes discontinuous, and the rotation of the cylinder motor is disturbed. Also, if you switch from a mode that does not perform phase control to a mode that performs phase control,
It takes a long time (about 2 to 3 seconds) to achieve phase lock, and color synchronization may be lost, resulting in an extremely unsightly playback screen.

(d) Means for solving the problems The phase control device of the present invention is a digital servo, and uses counter means, latch means, etc. The present invention is a control device that creates a phase error signal based on the phase difference between a pulse signal related to the rotational phase of a rotating body and a phase reference counter,
When changing from a mode that performs phase control to a mode that does not perform phase control, the previous phase error signal continues to be output, and when returning from a mode that does not perform phase control to a mode that performs phase control, The present invention is a phase control device that causes a phase reference counter to preset data related to the immediately preceding phase error signal at the timing of the pulse signal immediately after returning to a phase control mode.

(E) Effect When transitioning from a mode in which phase control is performed to a mode in which phase control is not performed, the immediately preceding phase error signal is retained, so discontinuity in the phase error signal does not occur. Furthermore, when transitioning from a mode in which no phase control is performed to a mode in which phase control is performed, data related to the immediately preceding phase error signal is set in the phase reference counter at the timing of the pulse signal regarding the rotational phase. and this pulse signal have a predetermined phase relationship. In other words, since the phase control starts from a state in which the phase is locked, the rotation is not disturbed as in the conventional example.

(f) Examples Examples of the present invention will be described below with reference to the drawings.

Fig. 1 is a block diagram of the embodiment, Fig. 2 is an explanatory diagram for explaining the operation, Fig. 3 is a block diagram when the present invention is realized by a microcomputer, and Fig. 4 is the same as that shown in Fig. 3. An explanatory diagram for explaining the operation, FIG. 5 is a flowchart.

First, a first example will be described. In FIG. 1, 1 is an input terminal for a predetermined clock signal;
2 and 3 are input terminals for a PG signal indicating the rotational phase of the cylinder motor, 4 is an input terminal for a slow control signal that becomes H level when the VTR is in slow playback mode, 5 is a counter for counting clock signals, and 6 is a counter. A latch circuit that latches the output of 5 at the timing of the PG signal, 7 a phase error signal creation circuit that creates a phase error signal based on the latched phase difference data, 8 a latch 6, a counter 5, and a phase error signal. The operation of the creation circuit 7 is controlled by the PG signal,
This is a control circuit that is controlled by a slow control signal.
A phase error signal is output from terminal 9,
It is added to a speed error signal based on the FG signal of the cylinder motor (not shown) to control the cylinder motor.

The phase control of the cylinder motor is performed so that it is synchronized with the vertical synchronization signal of the video signal to be recorded during recording, and with a reference signal of a predetermined cycle during reproduction. Therefore, the counter 5 is set by a vertical synchronizing signal inputted to the terminal 10 during recording. During reproduction, the counter 5 counts the clock signal and repeats overflow at a predetermined period (vertical synchronization period).

Further, the counter 5 operates to preset the data held in the latch circuit 6 in response to a preset signal from the control circuit 8.

The latch circuit 6 normally latches the output of the counter 5 at the timing of the PG signal. However, the control circuit 8
If a hold signal is being output from , the latched data will continue to be held regardless of the PG signal.

The control circuit 8 outputs a holding signal when the VTR enters the slow playback mode and a slow control signal is applied. And this holding signal is the PG signal after the VTR is changed from slow playback mode to normal playback mode.
Output until the signal input timing. On the other hand, a preset pulse is output to the counter 5 at the timing of the PG signal after the slow reproduction mode is changed to the normal reproduction mode.

Next, the operation will be explained based on FIG. In normal playback mode, the data of counter 5 is latched at the timing of the PG signal, and the data of counter 5 is latched from the phase reference (timing of overflow of counter 5) to PG.
Data related to the phase difference to the signal is obtained.
The phase error signal creation circuit 7 creates a phase error signal based on this phase difference data and outputs it.

When the slow control signal A becomes H level and the VTR enters slow playback mode, a holding signal is output.
The phase difference data immediately before entering the slow playback mode will be held during the slow playback mode. Therefore, the phase error signal during the slow reproduction mode is the same as that in the immediately preceding normal reproduction mode. Therefore, discontinuity of the phase error signal does not occur when changing modes.

When the slow control signal A changes to L level, the latch circuit 6 is activated at the timing of the PG signal C immediately after.
The data held in the counter 5 is preset. Counter 5 continues counting, but the phase relationship between the phase reference and the PG signal is the same as in the normal playback mode before the slow playback mode, so the phase error signal created thereafter will be Same as when in mode. Therefore, the rotation of the cylinder motor will not be disturbed. Incidentally, the speed control is executed even during the slow playback mode.

FIG. 3 shows a schematic configuration of a microcomputer when the digital servo according to the present invention is implemented by the microcomputer. The microcomputer 20 includes a CPU 21, a ROM 22,
A register 23, an input/output port 24, a first timer counter 25, a second timer counter 26, etc. are provided, and operations are performed according to a program set in the ROM 22.

The first and second timer counters 25 and 26 are clock signals (period: 1 μsec) from the microcomputer 20.
In particular, the second timer counter 26 has a preset function so as to serve as a phase reference.

The PG signal and vertical synchronization signal are input to the CPU,
Interrupt processing for each corresponding program is performed. Further, a slow control signal is also applied to the CPU 21.

An error signal (a phase error signal and a speed error signal are internally added together) for controlling the cylinder motor is output from the input/output port 24, and is supplied to the cylinder motor drive circuit.

During the operation of the microcomputer 20, a phase error signal is created as shown in FIG. The second timer counter 26 repeatedly overflows at a predetermined period so as to serve as a phase reference. A PG signal interrupt occurs at the falling timing of the PG signal, but since the microcomputer may be performing other processing at that time, the data a of the first timer counter 25 at that time is input captured. Set in register. Thereafter, after the current processing is completed, a PG signal interrupt is performed. In the PG signal interrupt, the first timer counter 25 is reset, and data b of the first timer counter 25 and data g of the second timer counter 26 at the time of the reset are stored in a register,
The phase difference data T is calculated based on the formula T=g−(ba).

A phase error signal is created as shown in D based on the obtained phase difference data T. Here, T _D is the bias period and Ts is the lock range.

Now, when a mode change from normal playback mode to slow playback mode to normal playback mode occurs, and the mode shifts to a mode in which phase control of the cylinder motor is not performed, the operation of the flowchart shown in FIG. 5 is performed.

That is, when the PG signal interrupt processing is performed, the slow control signal is checked, and if the mode is normal playback mode, data g is set in register R1, phase difference data T is set in register R2, and the phase error signal is set. Create and output and return to the main routine.

If the slow playback mode is selected when the PG signal is input, a phase error signal is created using the phase difference data T stored in the register R2, and the process returns to the output main routine.

When the PG signal is input, if the slow playback mode has just been changed to the normal playback mode, the register R is stored in the second timer counter 26.
The data g stored in register R2 is preset, a phase error signal is generated and output based on the phase difference data T stored in register R2, and the process returns to the main routine. Subsequent PG interrupts will be in normal playback mode.

According to the above operation, no discontinuity occurs in the phase error signal when transitioning from a mode in which no phase control is performed to a mode in which phase control is performed, and a transition from a mode in which no phase control is performed to a mode in which phase control is performed does not occur. Even if it returns, the relationship with the phase reference is set the same as before, so the rotation of the cylinder motor will not be significantly disturbed.

In the above embodiments, the PG signal is used as a signal representing the rotational phase of the controlled object, but a plurality of FG signals output per rotation may also be used.
At this time, the frequency of the signal serving as the phase reference may also be increased. Furthermore, although the slow playback mode of a VTR is taken as an example of a mode in which phase control is not performed, other modes such as cue mode, review mode, etc. may also be used.

(G) Effects of the Invention As described above, according to the present invention, when the mode shifts to a mode in which no phase control is performed and returns to the original mode,
The effect is great because the servo is not disturbed greatly.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the first embodiment, Fig. 2 is an explanatory diagram of Fig. 1, Figs. 3 to 5 relate to the second embodiment, and Fig. 3 is a block diagram of a microcomputer. FIG. 4 is an explanatory diagram of the operation, and FIG. 5 is a flowchart. 5... Phase reference counter, 6... Latch circuit, 7...
Phase error signal generation circuit, 8...control circuit.

Claims (1)

[Claims] 1. A phase reference counter; a holding means for inputting and holding a value of the phase reference counter when a pulse signal related to the phase of a controlled object is generated; and a phase error detection unit based on the value held in the holding means. a phase error signal generating means for generating a signal; and a control means to which a control signal is applied indicating whether the mode is a mode in which phase control is performed or a mode in which phase control is not performed, and the control means is provided with a mode in which the phase control is not performed. The holding means continues to hold the value held in the holding means regardless of the generation of the pulse signal after the control signal indicating the mode is applied until the control signal indicating the mode in which the phase control is performed is input. and controlling the phase reference counter so as to preset the value held in the holding means at the timing of the pulse signal generated immediately after a control signal indicating a mode for performing the phase control is input. Characteristic phase control device.