JPS63196911A - Position controller - Google Patents

Abstract

PURPOSE:To eliminate the disturbance of servo by holding the just preceding phase error signal at the time of switching from the phase control state to the phase control release state and presetting the just preceding related data to a counter at a prescribed timing at the time of reverse switching. CONSTITUTION:In the normal reproducing mode, data of a phase reference counter 5 is latched at the timing of a PG signal (c) and data related to the phase difference between a phase reference and the signal (c) is obtained. A phase error signal generating circuit 7 generates a phase error signal on the basis of this data and outputs this signal. When a slow control signal (a) goes to the high level to set the slow reproducing mode, a holding signal is outputted, and phase difference data just before setting of this mode is held as long as this mode is set. Then, the phase error signal is in the same state as the normal reproducing mode and is not discontinuous for switching. When the signal (a) is changed to the low level, data held in a latch circuit 6 is preset to a counter 5 at the timing of the just following signal (c). Counting of the counter 5 is continued, and the phase error signal is in the same state as the slow reproducing mode and motor rotation is not disturbed.

Description

[Detailed description of the invention] (b) Industrial application field The present invention relates to a phase control device.

(b) Conventional technology Video tape recorder (V
TFI) is equipped with a cylinder motor that moves the rotating head tm and a capstan motor that transports the reef tape. The speed and phase of the rotation of these cylinder motors and capstan motors are controlled. In particular, phase control during reproduction is difficult due to tracking of the rotating head.

However, under special circumstances, canceling the phase control may change the characteristics of each element. For example, in a helical scan VTR, in an intermittent slow playback mode in which the tape is moved intermittently and still playback and normal external playback are played back repeatedly, the cylinder motor is controlled only at high speed and phase control is canceled. are doing. This is because the period of the horizontal synchronizing signal reproduced during still reproduction and normal reproduction differs (because the relative speed changes), and if left as is, the reproduced image will be swayed laterally. In order to prevent this lateral vibration, phase control is completely canceled and the rotation speed of the cylinder motor is accelerated to match the still playback and normal playback conditions.
It's slowing down.

In such a case, a problem arises when a transition occurs from a state in which phase control is performed to a state in which it is released, or vice versa. That is, how to set the phase error voltage to be supplied to the motor drive circuit when changing the mode from the normal regeneration mode to the intermittent slow regeneration mode (or vice versa).

Conventionally, when starting the motor,
Similar to the method adopted in Publication No. 50 (GO5D13/621), a signal at a predetermined level is applied as a phase error signal when phase control is released.

However, in such a conventional example, discontinuity occurs in the phase error signal, and it takes time to achieve phase lock when the mode changes between normal playback and intermittent slow playback as described above, and the color synchronization of the video circuit may be lost. be.

(c) Problems to be solved by the invention: In a configuration in which a signal at a predetermined level is simply applied as a phase error signal when phase control is canceled, phase control must be canceled from the state in which phase control is being performed. Then, the phase error signal becomes discontinuous, and the rotation of the cylinder motor becomes disordered. Also, when transitioning from phase control release state to phase control state, it takes time (2 to 2 to
(about 3 seconds), the color synchronization may be lost, resulting in a very unsightly playback screen.

B) Means for Solving the Problems The phase control device of the present invention utilizes a) counter means, latch means, etc. in a digital servo. The present invention is a control device that creates a phase error signal based on the phase difference between a pulse signal related to the rotational phase of a rotating body and a phase reference counter, and which changes from a state in which phase control is performed to a state in which phase control is canceled. When transitioning, the previous phase error signal continues to be output, and when returning from a phase control release state to a state where phase control is performed, the phase reference counter is output immediately after returning to a state where phase control is performed. The phase control device presets data related to the immediately preceding phase error signal at the timing of the pulse signal.

(E) Operation When transitioning from the phase control state to the phase control release state, the previous phase error signal is retained, so discontinuity of the phase error signal does not occur. Furthermore, when transitioning from the phase control release state to the phase control state, data related to the immediately preceding phase error signal is set in the phase reference counter at the timing of the pulse signal regarding the rotational phase, so that the reference phase and this pulse signal has a predetermined phase relationship. In other words, since phase control starts from a phase-locked state, rotation is not disturbed as in the conventional example.

(f) Example Embodiments of the present invention will be described below with reference to the drawings.

Fig. 1 is a block diagram of the Fi embodiment, Fig. 2 is an explanatory diagram for explaining the operation, Fig. 3 is a block diagram when the present invention is realized by a microcomputer, and Fig. 4 is the operation in Fig. 5. An explanatory diagram for explanation, FIG. 5 is a flowchart.

First, a first example will be described. In FIG. 1, (llu predetermined clock signal input terminal, +21+3
1 is an input terminal for a PG multiplied signal indicating the rotational phase of the cylinder motor, (41#1 is an input terminal for a slow control signal that becomes H level when the VTR is in slow playback mode, (5) is a counter for counting clock signals, (6) ) is a latch circuit that latches the output of the counter (5) at the PG double signal timing,
(7) is a phase error (error HFI signal generation circuit) that generates a phase error signal based on the latched phase difference data;
8) is a control tautology in which the operations of the latch (6), counter (5), and phase error signal generation circuit (7) are controlled by the PG multiplied signal slow control signal. A phase error signal is output from the terminal (9), and is added to a speed error signal based on an FG flaw signal of the cylinder motor (not shown) to control the cylinder motor.

The phase control of the cylinder motor is performed so that it is synchronized with the vertical synchronization signal of the video signal to be recorded during recording, and with a reference signal of a predetermined cycle during reproduction. Therefore, the counter (51 is reset by the vertical synchronization signal input to the terminal (1α) during recording. During playback, the counter (51)
5) counts clock signals and repeats overflow at a predetermined period (vertical synchronization period).

Further, the counter (5) performs an operation of presetting the data held in the latch circuit (6) in response to a preset signal from the control circuit (8).

The latch circuit (6) normally latches the output of the counter (5) at the timing of the PG signal. However, if a holding signal is output from the control circuit (8), the latched data continues to be held regardless of the PG flaw signal.

The control circuit (8) outputs a holding signal when the VTR enters the slow reproduction mode and a slow control signal is applied. This holding signal is output until the PG flaw signal input timing after V'I'R is changed from the slow playback mode to the normal playback mode. On the other hand, at the timing of the PC) signal after changing from slow playback mode to normal playback mode,
Output the preset pulse to the trigger (5).

Next, the operation will be explained based on FIG. In the normal reproduction mode, data of the counter (5) is latched at the timing of the PG flaw signal, and data related to the phase difference in the PG flaw signal is obtained from the phase reference (timing of overflow of the counter (5)).

A phase error signal creation circuit (7) creates a phase error signal based on this phase difference data and outputs it.

When the slow control signal (a) becomes H level and the VTR enters the slow playback mode, a holding signal is output, and the phase difference data immediately before entering the slow playback mode is used when changing the slow playback mode. Therefore, the phase error signal during the slow reproduction mode is the same as that in the immediately preceding normal reproduction mode. Therefore, discontinuity of the phase error signal does not occur when changing modes.

When the slow control signal 0) changes to L level, the 9 data held in the latch circuit (6) is preset in the counter (5) at the timing of the PG scratch signal immediately after. Then, the counter (5) continues counting, but the phase relationship between the phase reference and the PG flaw signal is the same as in the normal playback mode before the slow playback mode, so the phase error signal created thereafter is Same as when in slow playback mode. Therefore, the rotation of the cylinder motor will not be disturbed. Incidentally, the speed control is executed even during the slow playback mode.

FIG. 5 shows a schematic configuration of a microcomputer when the digital servo according to the present invention is implemented by the microcomputer. Microcomputer Q)K
4dc P U1211. Ro M (221, v register ■, input/output boat Q4, 1st timer counter ■, 2nd
A timer counter ■ etc. are provided, 80M1221
The operation is performed according to the program set in .

pJl, the second timer counter (2511261 is the clock signal of the microcomputer (20) (period: 1 μse)
c), and in particular, the second timer counter (2) has a preset function so as to serve as a phase reference.

The PG flaw signal is input to the vertical synchronization signal tiapu, and interrupt processing of the corresponding programs is performed. A slow control signal is also applied to opu(2]J.

An error signal C for controlling the cylinder motor (which is the sum of a phase error signal and a speed error signal) is output from the heel of the input/output capo 1 and is supplied to the cylinder motor drive circuit.

During the operation of microcomputer 4, a phase error signal line is created as shown in FIG. Second timer counter 12
e repeats overflow at a predetermined period so as to serve as a phase reference. PG at the falling edge timing of PG flaw signal
A signal interrupt is performed, but since the microcomputer may be performing another process at that time, the data (a) of the first timer counter (2) at that time is set in the input capture register. After the current processing is completed, PG damage signal input is performed.

In the PG signal interrupt, the first timer counter is reset, and the data (b) of the first timer counter G and the data (y) of the second timer counter (2) at the time of the reset are stored in a register, and the phase difference data is stored. T to T”?-(b
-a) Calculate based on the formula.

A phase error signal is created as shown in ) based on the obtained phase difference data T. Here, TD is a bias period and Ts is a lock range.

Now, when a mode change from normal reproduction mode to slow reproduction mode to normal reproduction mode occurs and the phase control of the cylinder motor is canceled, the operation shown in the flowchart shown in FIG. 5 is performed.

In other words, when PG double signal interrupt processing is performed, the slow control signal is checked, and if it is in normal playback mode, data ψ) is set in register B1, phase difference data T is set in register B2, and then the slow control signal is checked. Create and output a phase error signal and return to the main routine.

If the 2-slow playback mode is selected when the PG multiplied signal is input, a phase error signal is created and output based on the phase difference data TK stored in the register R2, and the process returns to the main routine.

When the PG double signal is input, if the slow playback mode has just been changed to the normal playback mode, the data (P) stored in the register B1 is preset to the second timer counter 128, and the data (P) stored in the register B1 is preset. A phase control 2- signal is generated and output based on the phase difference data T stored in R2, and the process returns to the main routine.

Subsequent PG interruptions result in normal playback mode.

According to the above operation, discontinuity in the phase error signal does not occur when phase control is canceled, and even when the phase control is canceled and returns to the original state, the relationship with the phase reference is set as before. Therefore, the rotation of the cylinder motor will not be greatly disturbed.

In the above embodiment, a PG multiplied signal is used as a signal representing the rotational phase of the controlled object, but a plurality of PG multiplied signals output per one rotation may also be used.

At this time, the frequency of the signal serving as the phase reference may also be increased. In addition, although the slow playback mode of a VTR is used as an example of the mode for releasing the phase control tube, other modes such as cue,
It may also be in review mode.

(G) Effects of the Invention As described above, according to the present invention, when phase control is canceled and then restored, the servo is not disturbed significantly, so the effect is great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the first embodiment, FIG. 2 is an explanatory diagram of FIG. 1, FIGS. 3 to 5 relate to the second embodiment, and FIG. 3 is a block diagram of a microcomputer. FIG. 4 is an explanatory diagram of the operation, and FIG. 5 is a flowchart. (5)...Phase reference counter (6)...Launch circuit (7)...Phase error signal creation circuit (8)...
・Control circuit.

Claims (1)

[Claims] (1) In a phase control device that creates a phase error signal based on the phase difference between a pulse signal related to the phase of a controlled object and a phase reference counter, when transitioning from a phase control state to a phase control release state, the immediately preceding phase error signal is used. and when returning to the phase control state, the phase reference counter is preset with data related to the immediately preceding phase error signal at the timing of the pulse signal after returning to the phase control state. Phase control device.