JPS6235957A - Buffer control system - Google Patents

Abstract

PURPOSE:To transfer data at a high speed by accessing a buffer memory from a host or subordinate device without interrupting the processing of a microprocessor when the microprocessor is in the instruction read state or the operation processing state in an input/output controller. CONSTITUTION:When transmission data reaches a device interface 18 from a magnetic disc device 3, the access request to the buffer memory is transmitting to a testing circuit 19. The testing circuit 19 checks the operation state of a microprocessor 11; and if the microprocessor 11 is in the instruction read state or the operation state, a gate 110 is cut off to divide an internal bus 16 into parts which connect the microprocessor 11, a direct memory access mechanism 12, a program memory 13, and a work memory 14 and parts which connect a buffer memory 15, a processor interface 17, and the device interface 18, and an access permission signal (s) to the buffer memory 15 is transmitted to the direct memory access mechanism 12.

Description

[Detailed Description of the Invention] [Summary] In an input/output control device that controls data transfer between a higher-level device and a lower-level device, when an access request to a buffer memory is received, a microprocessor changes to an instruction reading state and an arithmetic processing state. By allowing data transfer to and from the buffer memory, transfer efficiency is improved.

[Industrial application field]

The present invention relates to a buffer control method in an input/output control device that connects a lower device such as a magnetic disk device to a higher device such as a central processing unit or a main storage device to perform data transfer.

In general, the input/output control device is connected to a processor bus of a central processing unit or under a data channel, and controls input/output devices that are lower-level devices.

This type of input/output control device is desired to efficiently control data transfer between a higher-level device and a lower-level device as quickly as possible.

[Conventional technology]

FIG. 5 is a diagram showing an example of a conventional input/output control device, and FIG. 6 is a diagram showing an example of a conventional buffer control method.

In FIG. 5, an input/output control device 1 is connected to a processor bus 2 of a higher-level device (not shown), and a magnetic disk device (DK) 3 as a lower-level device. ) 3, a direct memory access mechanism (DMAC) 12, a program memory (PM) 13 that stores a program for controlling the operation of the microprocessor 11, and a microprocessor 2 11. A processor bus 2 is connected to a work memory (WM) 14 used during operation, a buffer memory (BM) 13 that temporarily stores data transferred between the host device and the magnetic disk device 3, and an internal bus 16 that connects each of the devices. It consists of a processor interface (P) 17 to which it is connected, and a device interface (DI) 1B to which it connects the magnetic disk device 3.

5 and 6, when transfer data arrives at the device interface 184 from the magnetic disk device 3, the device interface 18 transmits an access request to the buffer memory 15 to the direct memory access mechanism 12 (step Sl in FIG. 6). . After the direct memory access mechanism 12 executes a processor halt which causes the microprocessor 11 to temporarily suspend processing (step S2)
, writes data to the buffer memory 15 (
Step S3). When the data writing is completed, the direct memory access mechanism 12 executes a processor halt release that causes the microprocessor 11 to resume the suspended processing (step 54).

When transferring data stored in the buffer memory 15 to the magnetic disk device 3, and when transferring data stored in the buffer memory 15,
A similar process is performed in the case of data transfer between the host device and the host device.

[Problem that the invention seeks to solve]

As is clear from the explanation below, in some conventional buffer control systems, when data is read from or written to the buffer memory I5 from the host device or the magnetic disk device 3, the processing of the microprocessor 11 is temporarily interrupted. However, the disadvantage is that the transfer control processing time increases. Furthermore, in cases where high-speed processing is required, such as in the magnetic disk device 3, a dedicated control circuit must be provided, which may impair economic efficiency.

[Failure to solve the problem]

FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, a test circuit (100) that tests the operating state of the microprocessor (100) when receiving an access request to the buffer memory (200) from either the upper device (300) or the lower device (4 (10)) is shown. 600) is provided in the input/output control device (500).

The test circuit (600) is a microprocessor (100)
data transfer between the upper device (300) or the lower device (400) and the buffer memory (200) is allowed when the buffer memory (200) is in an instruction reading state and an arithmetic processing state.

[Effect]

That is, according to the present invention, when the microprocessor is in the instruction reading state and the arithmetic processing state, the buffer memory can be accessed from the higher-level device or the lower-level device without interrupting the processing of the microprocessor, and data transfer can be performed easily. This makes it possible to increase speed and efficiency.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing an input/output control device according to an embodiment of the invention, FIG. 3 is a diagram showing a buffer control system according to an embodiment of the invention, and FIG. 4 is a diagram showing an embodiment of the invention. FIG. 7 is a diagram illustrating a buffer accessible period according to an example. Note that the same reference numerals refer to the same objects throughout the plan.

In FIG. 2, a test circuit (
TST) 19 and game) 110 are newly established.

In FIGS. 2 to 4, when transfer data arrives at the device interface 18 from the magnetic disk device 3,
The device interface 18 transmits an access request to the buffer memory to the test circuit I9 (step 5l).
l). The test circuit I9 tests the operating state of the microprocessor 11 (step 512), and if it is in the instruction reading state and the arithmetic processing state, the test circuit I9 sets the internal bus 16 to the microprocessor 11,
A portion (16-1>) connecting the direct memory access mechanism 12, program memory 13, and work memory 14;
Buffer memory 15, process direct memory access mechanism 1
The access permission signal S for the buffer memory 15 is transmitted to the buffer memory 15. As a result, the direct memory access mechanism 12 stores the transfer data that has arrived at the device interface 1B in the buffer memory 15 (step 513).

When transferring data stored in the buffer memory 15 to the magnetic disk device 3, and when transferring data stored in the buffer memory 15,
A similar process is performed in the case of data transfer between the host device and the host device.

As is clear from the above description, according to this embodiment, when the microprocessor 11 is in a cycle other than the operand fetch cycle P as shown in FIG. The direct memory access mechanism 12 becomes capable of data transfer during the buffer accessible period BA.

Note that FIGS. 2 to 4 are only one embodiment of the present invention, and for example, the lower-order device is not limited to the magnetic disk device 3, and many other modifications may be considered, but any The effect of the present invention does not change even in this case. Also, input/output control
The configuration of the device 1' is not limited to that shown in the drawings, and many other modifications may be considered, but the effects of the present invention will not change in any case.

〔Effect of the invention〕

As described above, according to the present invention, in the input/output control device,
When the microprocessor is in the instruction reading state or arithmetic processing state, the buffer memory can be accessed from the upper or lower device without interrupting the microprocessor's processing, making data transfer faster and more efficient. becomes.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing an input/output control device according to an embodiment of the present invention, FIG. 3 is a diagram showing a buffer control system according to an embodiment of the present invention, and FIG. FIG. 4 is a diagram showing a buffer accessible period according to an embodiment of the present invention, FIG. 5 is a diagram showing an example of a conventional input/output control device,
FIG. 6 is a diagram showing an example of a conventional buffer control method. In the figure, 1.1' and 500 are input/output control devices;
2 is a processor bus, 3 is a magnetic disk device (DK),
11 and 100 are microprocessor t (MP), 12
is the direct memory access mechanism (DMAC), 13 is the program memory (PM), and 14 is the work memory (WM).
), 15 and 200 are buffer memories (BM)
, l 6.16-1 and 16-2 are internal buses, 17 is a processor interface (PI), 1B is a device interface (DI), 19 is a test circuit (TST),
110 is a gate, 300 is an upper device, 400 is a lower device, 600 is a test means, A is an operation cycle, BA is a buffer accessible period, ■ is an instruction read cycle, P is an operand fetch cycle, S is an access permission signal, and X indicates an indexing cycle.

Claims (1)

[Claims] A microprocessor (100) and a buffer memory (
200), an upper device (300) and a lower device (4
An input/output control device (
500), when receiving an access request to the buffer memory (200) from either the higher-level device (300) or the lower-level device (400), the microprocessor (100)
) is provided, and when the microprocessor (100) is in an instruction reading state and an arithmetic processing state, the test circuit (600) tests the operating state of the host device (300).
) or the lower device (400) and the buffer memory (2
A buffer control method characterized by allowing data transfer between 00 and 00).