JPH0353361A - Io control system - Google Patents

Io control system

Info

Publication number
JPH0353361A
JPH0353361A JP18940589A JP18940589A JPH0353361A JP H0353361 A JPH0353361 A JP H0353361A JP 18940589 A JP18940589 A JP 18940589A JP 18940589 A JP18940589 A JP 18940589A JP H0353361 A JPH0353361 A JP H0353361A
Authority
JP
Japan
Prior art keywords
processor
designated
interruption
dma transfer
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18940589A
Other languages
Japanese (ja)
Inventor
Yoshiyuki Miki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP18940589A priority Critical patent/JPH0353361A/en
Publication of JPH0353361A publication Critical patent/JPH0353361A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enable an IO device to use plural DMA transfer devices by applying an interruption to a processor designated by a processor ID if no DMA transfer device ID is designated.
CONSTITUTION: When the command information shows the read transfer, an IO controller 6 reads the data out of an IO device 21 connected to the controller 6 and then refers to the DMAID stored in a register 10 when the data is ready. If the DMAID is not designated, an interruption signal INT 18 is activated and an interruption (INT 12 or 13) is applied to a processor 1 or 2 which is designated by a register 7. Receiving this interruption, the processor (CPU 1 to 2) reads the data with an IO instruction of the processor itself. Thus each processor can use the IO device and also the optional one of plural DMA transfer devices.
COPYRIGHT: (C)1991,JPO&Japio
JP18940589A 1989-07-21 1989-07-21 Io control system Pending JPH0353361A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18940589A JPH0353361A (en) 1989-07-21 1989-07-21 Io control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18940589A JPH0353361A (en) 1989-07-21 1989-07-21 Io control system

Publications (1)

Publication Number Publication Date
JPH0353361A true JPH0353361A (en) 1991-03-07

Family

ID=16240733

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18940589A Pending JPH0353361A (en) 1989-07-21 1989-07-21 Io control system

Country Status (1)

Country Link
JP (1) JPH0353361A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006133968A (en) * 2004-11-04 2006-05-25 Fujitsu Ltd Information processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006133968A (en) * 2004-11-04 2006-05-25 Fujitsu Ltd Information processor

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