JPH0353361A - Io control system - Google Patents

Abstract

PURPOSE:To enable an IO device to use plural DMA transfer devices by applying an interruption to a processor designated by a processor ID if no DMA transfer device ID is designated. CONSTITUTION:When the command information shows the read transfer, an IO controller 6 reads the data out of an IO device 21 connected to the controller 6 and then refers to the DMAID stored in a register 10 when the data is ready. If the DMAID is not designated, an interruption signal INT 18 is activated and an interruption (INT 12 or 13) is applied to a processor 1 or 2 which is designated by a register 7. Receiving this interruption, the processor (CPU 1 to 2) reads the data with an IO instruction of the processor itself. Thus each processor can use the IO device and also the optional one of plural DMA transfer devices.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to the IO of an input/output control device in an information processing device.
Regarding control method.

[Conventional technology]

A DMA transfer device uses a common data transfer path (
When connected to the system bus (hereinafter referred to as system bus), the central processing unit (hereinafter referred to as CPU) transfers data between the input/output device (hereinafter referred to as IO) and the main storage device (hereinafter referred to as memory) in order to increase the response time. ) is used to speed up the process. In a multiprocessor system, each processor is not equipped with a DMA transfer device. Examples of this system configuration include an example in which the entire system has one DMA transfer device, an example in which the system has a DMA transfer device subordinate to a certain processor, and an example in which each processor has a DMA transfer device.

On the other hand, the IO control device is prepared for each IO device,
Since there is only one normal interrupt signal and one DMA transfer request signal, each of them is connected to only one processor and DMA transfer device.

FIG. 3 is a block diagram showing a conventional DMA transfer device system. Two CPUs 1a, 2a, one DMA transfer device 3a, main storage device 5, 10 control device f6a,
It includes a system bus 11 and an IO device 21. This IO control device 6a sends a DMA transfer request signal DRQ19 to the DMA transfer device 3a and receives a DMA transfer permission signal DAC.
Receive K20 and send interrupt signal 18 to CPUI. [Problem to be Solved by the Invention] As described above, in the conventional system, the IO control device 6a is connected only to one processor CPU1 and the DMA transfer device 3a, so that the other processor CPU2 is connected to the I/O control device 6a.
This has the disadvantage that it becomes difficult to issue control commands for the O device 21. An object of the present invention is to eliminate such drawbacks and provide an IO control system that enables each processor in a multiprocessor system to issue control commands to an IO device, and also allows a DMA transfer device with a plurality of IO devices to be used. The goal is to provide equipment.

[Means to solve the problem]

The configuration of the present invention is applicable to an I/O system in a multiprocessor system having a plurality of processors and a plurality of DMA transfer devices.
In the O control method, a processor ID that identifies a processor that issues a command among the plurality of processors.
to identify the processor and generate an interrupt to the processor that issued the command, identify the DMA transfer device to be used by the DMA transfer device ID, and if the DMA transfer device ID is specified at the time of data transfer, , issues a DMA transfer request to the corresponding DMA transfer device, and receives a DMA transfer permission signal from the DMA transfer device.
The present invention is characterized in that when the transfer is performed and the DMA transfer device ID is not specified, an interrupt is caused to the processor specified by the processor ID. [
Example] Next, the present invention will be explained using the drawings. FIG. 1 is a block diagram illustrating a system of a DMA transfer device according to an embodiment of the present invention, and will be explained using a multiprocessor system with two CPUs and two DMA transfer devices as an example.
In FIG. 1, CPUI is the first processor, C
PU2 is a second processor, DMA3 is a first DMA transfer device, DMA4 is a second DMA transfer device, and MEM5 is a main storage device. The system bus 11 is a bus for connecting the processors 1 and 2, the DMA transfer devices 3 and 4, the main storage device 5, and the IO control device 6. This bus 11 includes processor ID information, address information, read/write information, memory/IO information, and data.

When the processor (CPUI or CPU2) performs input/output, the processor selects the DMA transfer device (DM
A3 or DMA4) number is written in the ID register 10, and a command is issued to the target IO device. CPU 1 connects its processor I to system bus 11.
D, Output the transfer destination address/transfer source address, read/write information, memory/IO information, command information, ■○
The control device 6 takes in the above information via the system bus 11. The IO control device 6 stores the processor ID in the register 7.
The command information is stored in the command information, the operation indicated by the command information is performed, and when the command execution is completed, the interrupt signal INT18 is activated. When this INT18 becomes active, the logic circuit 8
activates the interrupt signal INT or IN713 of the CPU indicated by the processor ID stored in register 7.

If the command information is read transfer, the IO control device 6 is connected to this IO control device (reads data from the existing IO device, and when the data is ready, register 1
Look at the DMAID stored in 0 and select this DMAID.
is not specified, activates INT18 and interrupts the processor specified by register 7 (INT
12 or INT13). The processor (CPU1 or CPU2) that received this interrupt has its own
○Read data by command.

If DMAID is specified, DRQ19 is activated, and logic circuit 9 activates a DMA transfer request signal DRQ14 or DRQ16 for the DMA transfer device (DMA3 or DMA4) specified by DMAID. In addition, the logic circuit 9 selects the DMA transfer permission signal DACK15 or DACK17 from the DMA transfer device specified by DMAID, and outputs the DACK
20 to notify the IO control device 6 of permission for DMA transfer. The IO control device 6 outputs the prepared data to the system bus 11 when the DACK 20 becomes active. The data output onto the system bus 11 is written into the memory 5 by a DMA transfer device (DMA3 or DMA4).

If the command information is a write transfer, the IO control device 6 instructs the IO device 2l to write, and when the writing is ready, it checks the DMAID stored in the register 10 and activates the INT18 if the DMAID is not specified. Interrupts the processor specified by register 7 (INT12 or INT13). The processor (CPUI or CPU2) that receives this interrupt writes data to the processor 21 using its own IO command.

If the DMAID is specified, DRQ19 is activated, and the logic circuit 9 activates the DMA transfer request signal DRQ14 or DRQ16 for the DMA transfer device (DMA3 or DMA4) specified by the DMAID. DMA3 or D
MA4) reads data from memory 5 and outputs it to system bus 11. In addition, the logic circuit 9 selects the DMA transfer permission signal DACK1 5 or DACK1 7 from the DMA transfer device specified by DMAID
This is transmitted to the K20 and the IO control device 6 is notified of the DMA transfer permission. When the DACK20 becomes active, the IO control device 6 reads the data on the system bus 11.
Write to 1.

In this way, each processor can use any DMA transfer device, issue commands to the IO device, and perform data transfer.

FIG. 2 is a block diagram of a second embodiment of the invention. In the first embodiment, the system bus is in a single bus format, but with this bus format, only one processor or DMA transfer device can use the bus at a time, making it difficult to achieve sufficient multiprocessor performance. Therefore, in this embodiment, the bus type is a crossbar switch type bus 30.

In this type of bus 30, each processor or DMA transfer device has an independent connection path to the memory MEM 5 and the IO control device 6a.
Since the transfer devices can access in parallel,
It can deliver the performance of a multiprocessor.

〔Effect of the invention〕

As explained above, the multiprocessor system according to the present invention has the effect that each processor can use 10 devices and can also use any one of a plurality of DMA transfer devices. ．．

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a system of a DMA transfer device according to a first embodiment of the present invention, FIG. 2 is a block diagram showing a system configuration of a DMA transfer device according to a second embodiment of the present invention, and FIG. The figure is a block diagram showing the system configuration of a conventional DMA transfer device. 1, Ia, 2, 2a-CPU, 3.3a, 4-・DMA
Transfer device, 5... Main memory device (MEM) 6, 6a...
・IO control device, 7... Processor ID register, 8
．． 9 logic circuit, 10...DMAID register, 11...
...System bus, 12, 13.18... Interrupt request signal, 14, 16.19... DMA transfer request signal DRQ, 1 5, 1 7, 2 0... DMA transfer permission signal DACK, 2 1... IO device, 3 0... Crossbar switch type bus.

Claims (1)

[Claims] In an IO control method in a multiprocessor system having a plurality of processors and a plurality of DMA transfer devices, a processor that issues a command by identifying the processor using a processor ID that identifies the processor that issues the command among the plurality of processors. generates an interrupt for the DMA transfer device ID and selects the D
The MA transfer device is identified, and if the DMA transfer device ID is specified at the time of data transfer, a DMA transfer request is issued to the corresponding DMA transfer device, and the DMA transfer is performed by a DMA transfer permission signal from the DMA transfer device. and, if the DMA transfer device ID is not specified, an interrupt is caused to the processor specified by the processor ID.