JPS6234479Y2 - - Google Patents
Info
- Publication number
- JPS6234479Y2 JPS6234479Y2 JP1981004026U JP402681U JPS6234479Y2 JP S6234479 Y2 JPS6234479 Y2 JP S6234479Y2 JP 1981004026 U JP1981004026 U JP 1981004026U JP 402681 U JP402681 U JP 402681U JP S6234479 Y2 JPS6234479 Y2 JP S6234479Y2
- Authority
- JP
- Japan
- Prior art keywords
- thick film
- conductor layer
- insulating substrate
- hybrid integrated
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004020 conductor Substances 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 15
- 239000011347 resin Substances 0.000 claims description 9
- 229920005989 resin Polymers 0.000 claims description 9
- 229910000679 solder Inorganic materials 0.000 claims description 7
- 238000005476 soldering Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 description 7
- 229910052709 silver Inorganic materials 0.000 description 7
- 239000004332 silver Substances 0.000 description 7
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910000510 noble metal Inorganic materials 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000000696 magnetic material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
Landscapes
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Structure Of Printed Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【考案の詳細な説明】
本考案はシールド効果を有し、かつ低コストの
厚膜混成集積回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a thick film hybrid integrated circuit that has a shielding effect and is low cost.
一般に電気力線または磁力線の影響をある限ら
れた場所だけに制限する場合、またはある限られ
た場所を外部からの電磁妨害の影響を妨ぐ必要が
生じる場合、銅あるいはアルミニウムのような電
気抵抗の低い材料で作つた容器で目的とする空間
を完全に包むかあるいは鉄のような磁性材料で包
み、静電的または電磁的な相互誘導作用を防止す
るいわゆるシールドが行なわれている。 In general, when the influence of electric or magnetic lines of force is restricted to a limited area, or when it is necessary to protect a limited area from the effects of external electromagnetic interference, electrical resistors such as copper or aluminum are used. So-called shielding is performed by completely enclosing the target space with a container made of a material with a low carbon content, or by wrapping it in a magnetic material such as iron to prevent electrostatic or electromagnetic mutual induction.
従来、混成集積回路においては上述のようなシ
ールドを行なうために外装容器を銅、アルミニウ
ムなどの金属製にして、該容器にアース端子を設
けたり、第１図および第２図に示すようにアルミ
ナなどよりなる絶縁基板１の裏面に銀、パラジウ
ム銀などのシールド用導体層２をスクリーン印刷
法によつて全面に印刷、焼成して形成し、該絶縁
基板１の表面に同様にして銀、パラジウム−銀な
どの配線用導体層３および抵抗体層４を順次印
刷、焼成して形成し、さらにコンデンサ５、半導
体６、引出リード端子７ａ，７ｂ，７ｃ……など
を装着してそれぞれはんだで接続した後、樹脂８
で外装して構成されていた。しかしシールド用導
体層は銀などの高価な貴金属を用い絶縁基板１の
裏面のほとんど全面に印刷されているので、コス
ト高の要因となつていた。 Conventionally, in order to perform the above-mentioned shielding in hybrid integrated circuits, the outer container was made of metal such as copper or aluminum, and the container was provided with a ground terminal, or alumina was used as shown in Figures 1 and 2. A shielding conductor layer 2 made of silver, palladium, etc. is printed on the entire surface of the insulating substrate 1 by screen printing and baked on the back surface of the insulating substrate 1 made of silver, palladium, etc. - A conductor layer 3 for wiring such as silver and a resistor layer 4 are sequentially printed and fired, and then capacitors 5, semiconductors 6, lead terminals 7a, 7b, 7c, etc. are attached and connected with solder. After that, resin 8
It was made up of an exterior. However, the shielding conductor layer is made of an expensive noble metal such as silver and is printed on almost the entire back surface of the insulating substrate 1, resulting in high costs.
本考案は上述の欠点を除去するために上述の貴
金属の導体層２の使用量をシールド効果を有する
程度まで削減したものである。 In order to eliminate the above-mentioned drawbacks, the present invention reduces the amount of the noble metal conductor layer 2 used to the extent that it has a shielding effect.
すなわち、絶縁基板上に厚膜回路を構成した厚
膜混成集積回路において、上記絶縁基板の裏面に
メツシユ状もしくはくし状の導体層を形成し、該
導体層とアース端子とを接続したことを特徴とす
る厚膜混成集積回路である。 That is, a thick film hybrid integrated circuit in which a thick film circuit is formed on an insulating substrate is characterized in that a mesh-shaped or comb-shaped conductor layer is formed on the back surface of the insulating substrate, and the conductor layer is connected to a ground terminal. This is a thick film hybrid integrated circuit.
以下、本考案を第３図および第４図に示す実施
例についてて説明する。 The present invention will be described below with reference to the embodiments shown in FIGS. 3 and 4.
第３図は厚膜混成集積回路の裏面要部を示し、
アルミナなどよりなる絶縁基板１の裏面に銀、パ
ラジウム−銀などよりなるメツシユ状のシールド
用導体層９をスクリーン印刷法によつて印刷、焼
成して形成し、該絶縁基板１の表面には第１図に
示すように銀、パラジウム−銀などの配線用導体
層３および抵抗体層４などの順次印刷、焼成して
形成し、コンデンサ５、半導体６、引出リード端
子７ａ，７ｂ，７ｃ……などを装着し、それぞれ
はんだで接続され厚膜回路が構成される。この時
メツシユ状のシールド用導体層９は配線用導体層
３のアース側とともにアース端子７ｂにはんだ１
０によつて接続される。その後樹脂デイツプ、流
動浸漬などにより樹脂８を外装し完成される。 Figure 3 shows the main parts of the back side of the thick film hybrid integrated circuit.
A mesh-shaped shielding conductor layer 9 made of silver, palladium-silver, etc. is printed on the back surface of an insulating substrate 1 made of alumina or the like by screen printing and fired. As shown in FIG. 1, a conductor layer 3 for wiring such as silver, palladium-silver, etc. and a resistor layer 4 are sequentially printed and fired to form a capacitor 5, a semiconductor 6, lead terminals 7a, 7b, 7c, etc. etc., and are connected with solder to form a thick film circuit. At this time, the mesh-shaped shield conductor layer 9 is connected to the ground terminal 7b with the solder 1 together with the earth side of the wiring conductor layer 3.
Connected by 0. After that, resin 8 is applied to the exterior by resin dip, fluidized dipping, etc., and the product is completed.
本考案の厚膜混成集積回路は以上のようにして
構成されたものである。 The thick film hybrid integrated circuit of the present invention is constructed as described above.
したがつて絶縁基板１の表面に厚膜回路が形成
され、その裏面に形成されたメツシユ状の厚膜か
らなる導体層９によつてシールド効果を維持し、
銀などの導体層９を構成する材料の使用量が約２
分の１に削減する。全面にはんだ浸漬などして用
いるので半田付着量を少なくして電気抵抗を低減
し、かつ導体層間におけるアルミナなどの絶縁基
板１の地肌は焼結体であるので、表面に微細な凹
凸を有しこれに第４図のように直接外装樹脂８が
付着するため外装樹脂８と絶縁基板１とは接触面
積が増大して強固に接着するなどの効果が生ず
る。 Therefore, a thick film circuit is formed on the front surface of the insulating substrate 1, and a shielding effect is maintained by the conductor layer 9 made of a mesh-like thick film formed on the back surface of the thick film circuit.
The amount of material constituting the conductor layer 9, such as silver, used is approximately 2
Reduce to 1/2. Since the entire surface is immersed in solder, the amount of solder adhesion is reduced to reduce electrical resistance, and the surface of the insulating substrate 1, such as alumina, between the conductor layers is a sintered body, so the surface has minute irregularities. Since the exterior resin 8 is directly attached to this as shown in FIG. 4, the contact area between the exterior resin 8 and the insulating substrate 1 is increased, resulting in effects such as strong adhesion.
なお、上述の実施例では絶縁基板１の裏面に形
成したシールド用導体層９がメツシユ状のものに
ついて述べたが、導体層９を形成する縦方向、横
方向のいずれか一方のみで形成され、それぞれ電
気的に接続されたくし状のものについても同様な
効果を有し、また全面に形成しない空間部の形状
も正方形、長方形に限らず適宜選択できるもので
ある。また２枚の絶縁基板を用いて上述の導体層
９が互いに外側になるよう平行に配置するなどシ
ールド効果をより高めることもできる。 In the above-described embodiment, the shielding conductor layer 9 formed on the back surface of the insulating substrate 1 is mesh-shaped. Similar effects can be obtained by using comb-shaped parts that are electrically connected to each other, and the shape of the space that is not formed on the entire surface is not limited to square or rectangular, but can be appropriately selected. Further, the shielding effect can be further enhanced by using two insulating substrates and arranging them in parallel so that the above-mentioned conductor layers 9 are on the outside of each other.
叙上のように本考案の混成集積回路は安価で、
品質面においても極めて有利となり、工業的なら
びに実用的価値の大なるものである。 As mentioned above, the hybrid integrated circuit of the present invention is inexpensive;
It is extremely advantageous in terms of quality and has great industrial and practical value.
第１図は厚膜混成集積回路の外装樹脂を一部切
除した要部正面図、第２図は従来の厚膜混成集積
回路の外装樹脂を一部切除した要部背面図、第３
図は本考案の厚膜混成集積回路の一実施例の外装
樹脂を一部切除した要部背面図、第４図は同第３
図の厚膜混成集積回路のＡ−A′で切断せる側断
面図である。
１：絶縁基板、３，９：導体層、７ｂ：アース
端子。
Figure 1 is a front view of the main part of a thick film hybrid integrated circuit with part of the exterior resin removed, Figure 2 is a rear view of the main part of a conventional thick film hybrid integrated circuit with part of the exterior resin removed.
The figure is a rear view of the main part of one embodiment of the thick film hybrid integrated circuit of the present invention, with the exterior resin partially cut away, and Figure 4 is the same.
FIG. 2 is a side sectional view taken along line A-A' of the thick film hybrid integrated circuit shown in the figure. 1: Insulating substrate, 3, 9: Conductor layer, 7b: Earth terminal.
Claims (1)
回路において、上記絶縁基板の裏面にメツシユ状
もしくはくし状の導体層を形成し、該導体層とア
ース端子とをはんだで接続するとともに該導体層
全面にはんだを付着させ、上記導体層間における
絶縁基板の他肌に直接外装樹脂を付着したことを
特徴とする厚膜混成集積回路。 In a thick film hybrid integrated circuit in which a thick film circuit is formed on an insulating substrate, a mesh-shaped or comb-shaped conductor layer is formed on the back surface of the insulating substrate, and the conductor layer and a ground terminal are connected by solder, and the conductor layer is connected to a ground terminal by soldering. A thick film hybrid integrated circuit characterized in that solder is applied to the entire surface of the layer, and an exterior resin is directly applied to the other skin of the insulating substrate between the conductor layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1981004026U JPS6234479Y2 (en) | 1981-01-14 | 1981-01-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1981004026U JPS6234479Y2 (en) | 1981-01-14 | 1981-01-14 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57117696U JPS57117696U (en) | 1982-07-21 |
| JPS6234479Y2 true JPS6234479Y2 (en) | 1987-09-02 |
Family
ID=29802465
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1981004026U Expired JPS6234479Y2 (en) | 1981-01-14 | 1981-01-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6234479Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5696605B2 (en) * | 2011-07-01 | 2015-04-08 | 東京エレクトロン株式会社 | Data acquisition method for substrate processing apparatus and substrate processing apparatus |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49113162A (en) * | 1973-03-06 | 1974-10-29 | ||
| JPS5529274U (en) * | 1978-08-17 | 1980-02-26 |
-
1981
- 1981-01-14 JP JP1981004026U patent/JPS6234479Y2/ja not_active Expired
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49113162A (en) * | 1973-03-06 | 1974-10-29 | ||
| JPS5529274U (en) * | 1978-08-17 | 1980-02-26 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57117696U (en) | 1982-07-21 |
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