JPS6234235A - Multiplying device - Google Patents

Abstract

PURPOSE:To attain the multiplication of a display style of the complement of 2 by converting the data of the display style of the complement of 2 into positive numbers, performing the multiplication of positive numbers and applying correction to the multiplication of positive numbers. CONSTITUTION:Data X and Y of a display style of the complement of 2 are supplied to a positive number producing means 1 for conversion of these data into positive numbers X1 and Y1. These positive numbers are multiplied and supplied to an addition means 4. While data X and Y are supplied to a multiplication correcting means 3 for correction of multiplication involved with conversion into positive numbers. These corrected data are supplied to the means 4. The means 4 adds the output of a positive number multiplying means 2 with the output of the means 3 to obtain a product P. Thus the multiplication of the display style of the complement of 2 is made possible with use of the software and a ROM in a computer or at least the software.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiplication device, and more particularly to a multiplication device that realizes multiplication when data is in two's complement representation format on a computer.

[Conventional technology]

-m, the basic components of a computer are CPU and RA
It consists of M and ROM hardware, and software consisting of a program that organically combines these to achieve a purpose. When realizing the multiplication function on a computer,
Previously, this was handled using software.

The following equation (11(21(3)) is the multiplication algorithm that is the basis of this program.

X-27・X, +2' -X, +2' l Xs+
24 ・x 4+ 22 ・X.

+22・x2+2・x, +X0 ...(1) Y-27・yt+2′・yb+2′・y.

+24・ya +2n・y.

+22・y2+2・’/++)’.

...(2) P-X　-Y -X (2' y, +2h-yb+2S-y.

+24 ・y4+23 ・ys +22 ・yt +2・yt +)'o)=X (
2(2' ・Yt +2' -yb +2'
・y5+23 ・y4+ 21 ・y3+2・
Yt +Y+ )+)'o )-2(2(2(2(
2(2(2(yt I X) +y, l X)
+ys ・X)+y4 ・X)+)'!・X)+
Y!・X)+y+ ・X)+'lo ・X...
(3) In these formulas, the multiplicand X and the multiplier Y (hereinafter referred to as X).

Y) are assumed to be 8 bits each, and their general formula is Xx2' x, +2bx, +2' XS +2' x4
+'13x, +'l'' Xt +2x, +x(.

Y=2'Y-I+2' Yb +2'3's +2
)'4+2' ys +2n Yz +21+ +
y.

It can be expressed as If the product of X and Y is P, this P is expressed by the formula (
3), and finally -X-Y = 2(2(2(2(2(2(2(yq・X)+y6.X
)+Ys・X)+y4・X)+ys・X)+7z・x)
+y+-x)+)'o・X.

The procedure for finding this product P is to first find yt ・X, double it, then add y, ・X to this value and add 2(y,
・X)+ya ・Find X. Below, we calculate the values sequentially by doubling this value and adding y, ・X, and finally 2
Get the formula. This is an example of a multiplication algorithm that performs multiplication in software.

FIG. 6 shows an example of the program. In step M, assign X(!:Y to registers R+, Rt,
In step N, register P is set to O as an initial value, register i indicating which bit of Y is being calculated is set to 7, and calculation is started from the 7th bit. yt at step O
・0th order step Q that calculates X and adds it to register P
and increment it by one digit. Now, 2(y,・X)
The calculation has been completed. In step R, 1 is subtracted from register i to make it 6, and then the 6th bit is calculated. Return to step O, calculate y6 ・X, and store it in register P
and carry it up in step Q.

This completes the calculation up to 2 (2(yt·X)+y6). Similarly, bits 5, 4.3, and 2.1.0 are calculated, and by branching from step P, the contents of register P are output at step N.

[Problem that the invention seeks to solve]

Since the conventional multiplication device in a computer is configured as described above, multiplication is not possible when the data is in two's complement representation format.

The present invention has been made to solve the above-mentioned problems, and provides a multiplication device capable of performing multiplication in two's complement representation format using at least one of a ROM and software in a computer. The purpose is to

[Means for solving problems]

A multiplication device according to the present invention includes a positive number converting means for converting data in a two's complement display format into a positive number, a positive number multiplying means for multiplying by a positive number, and a multiplication correction means for performing multiplication correction of the positive number multiplying means. and addition means for adding the output of the positive number multiplication means and the output of the multiplication correction means, and , is a polarity sign, xl and 7i are transformed into numerical signs, and the product P(-X-Y) is expressed as the following formula % Formula % However, X, ! *X, m number of t of , Y , IJ: Y I(D
10) It is calculated according to mWl.

[Effect]

In this invention, data in a two's complement representation format is converted to a positive number, multiplication is performed by a positive number, and the multiplication correction means corrects the multiplication for the positive number, thereby performing multiplication in a two's complement representation format. be able to.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

First, the multiplication algorithm that forms the basis of the present invention will be described below.

(C) X-XI -2'-' Y-Yl -2
n-' (D) P catfish x-y = (XI -2'-') (Yt -2'-'
)=XI −Yl −(XI +'y',
) 2n + 2n - f = X + -'y',
+ (XI +1 +Y1 +1) 2'-'
+2n-"-XI -Yl + CXI +
v,')-2n-'+2n-"+2'(E) P
-X, ・Yl + (x+ +Y+) ・
2R-1+ (2n-” +1) ・2n(A)
shows a one-touch equation when an n-bit multiplicand X and an n-bit multiplier Y are expressed as two's complement numbers, where X and y3 are polarity codes. Generally, if X≧0 then X, -“0”,
, fable "1", and y.

The same is true. As it is, the product cannot be calculated because there is a minus sign in the formulas for X and Y, so each (2
The equation rewritten by adding n-2'%-1) is shown in (B). A simplified formula for this is shown in (C). (C) Xl
and Y are 1-X, -0or1 1 )'5-Oorl, and therefore can be regarded as positive numbers. (D) is the product P
-XY derivation process is shown. At this time, the identities of -X+ -yl +l, -y, -Y, and +1 are used. (E) shows a formula for obtaining the product P of two's complement representation data.

Next, a functional block diagram of a multiplication device according to an embodiment of the present invention is shown in FIG. 1 and will be described.

In FIG. 1, 1 converts X and Y, which are data in a two's complement representation format, to positive numbers, that is, X''XI 2n-Ten.

2 is a positive number multiplier that multiplies the obtained positive number Perform multiplicative correction, i.e. (Ml, Yl > ・2n-1+(2n
-Wealth+1) - Multiplication correction means for calculating 2n; and 4 is an addition means for adding the output of the positive number multiplication means 2 and the output of the multiplication correction means 3 to obtain the product P.

Further, a hardware configuration diagram of the multiplication device of the above embodiment is shown in FIG. In the figure, 11 is a computer consisting of a CPU 1a, a RAM 1lb, and a ROMI for storing programs (11c), 12 is a ROM 2 that stores the multiplication results of partial products of Xl and Yl, and 13 is a ROM that is configured by the CPU 11a. . Further, the multiplication by the positive number multiplication means 2 may be performed only by a computer as in the past, but in this case, XI and Yl are decomposed into the sum of two or more numerical values, and the partial products of the decomposed values are stored in the ROM conversion table ROM2 ( 12), and the method will be explained below.

That is, first assume that Xl and Y are 8 bits each, and
=Xt・2'+Xb・2b+Xs・25+x4・2'+
)C+・23+xz・22+X,・2+x0 Yl−yy・2'+yh・2'+)'s・25+Ya・
2'+ys・2'+)'z・22+y1・2+)'.

Expressed as. These X,, Y, are decomposed into two terms as follows.

Xl = (X7・2'+X6・2n+X5' 2 +
X4) 2'+ (x3-23+x, ・2n +xI・2
+xo)-XU・2'+XL Yl = (y-+・2' + y 6・22+ys
・2+y4)2'+(y,・2'+)'z・22+yI
・2+)'o)"YLl・2' + Y L Therefore, the product P is P-X, ・Yl "Xu' Yu・2n+(Xu-Yt + Xt, -YU)2'+XL-YL. In the two equations, Xu -Yu, Xu -Yt
, XL'YU, XL-YL represent partial products, and 21' and 24 represent carry amounts. By the way, Xu.

XL, ¥CI, YL are binary data of each bit, 0
≦X, XL, Y, YL≦15. Therefore, 0≦
Xu -Yu, Xu ・YL, Xl, -Yu
.

XL-YL≦225 and can be expressed in 8 bits. Therefore, the 8-bit value after multiplication of 4 bits x 4 bits is
If you store it in the composite address of the multiplicand and multiplier in the ROM, just read it and you will get Xu・Yu, Xu -Y
The values of L, XL-Yu, and Xt-Yt are obtained. This ROM2 (12) may be installed outside the computer 11 as shown in FIG. 2, or the RO flow diagram inside the computer 11 as shown in FIG. 5 is shown and explained in FIG. First, store XI and Yl in register R on the computer's RAM.

is taken into R1 (step H), and then 3 is stored in the loop control register i in order to perform multiplication four times (step I). Next, the combined address of XL+ and Yt+ is output to obtain the multiplication result Xt+Yυ from the ROM and stored in register B3. Below, XuYt, XL YLl
, Xt YL, register Bt
, B+, and Be store the multiplication results (step J).

next.

The CPU executes the addition of P-B0+B, .z'-+-Bz.2'+B, and 2a to obtain the multiplication result of the product P (step K). Finally, the product P is output from a predetermined port of the computer to complete the multiplication (step L). In this way, multiplication of positive numbers can be executed by combining the ROM and the program.

FIG. 4 shows a program flow diagram for multiplication of X and Y in two's complement representation format by the multiplication device of this embodiment using the algorithm (E) above. However, it is set to nwa 3.

First, the multiplicand X and the multiplier Y are stored in registers R+ and Rt (step A). Next, invert x3 to obtain XI, y
, reverse it and press Y.

is created and stored in registers Rs and R4 (Step B
). Next, Xl and Y are inverted to become Xl and Yl, and stored in registers R5 and R6 (step C). X, and Y,
are added and stored in register R1 (step D).

Multiply Xl and Yl according to the flowchart in FIG. 3, and store the result in register Re (step E) Re and R
1 multiplied by 27 and a constant 4100 (hexadecimal) are added to obtain the product P (step F). The product P is output to a predetermined computer input/output port (step G).

As described above, according to the present invention, multiplication of data in two's complement display format can be realized by using the multiplication algorithms (A) to (E) above.

Although the above embodiment has been described using an 8×8 bit multiplier with n=8 as an example, a general nXm bit multiplier can also be implemented in the same manner by applying the gist of the present invention.

〔Effect of the invention〕

As described above, according to the present invention, there is provided a positive number conversion means for converting a multiplicand and a multiplier in a two's complement representation format into positive numbers, a positive number multiplication unit for multiplying a positive number, and a multiplication correction accompanying the conversion to a positive number. and an addition means that adds the outputs of the positive number multiplication means and the multiplication correction means, and calculates the product of the multiplicand and the multiplier according to a predetermined formula. Multiplication in software or software and RO
There are effects that can be achieved by combining with M.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram of a multiplication device according to an embodiment of the present invention, FIG. 2 is a hardware configuration diagram of the above embodiment, and FIG. 3 is a multiplication program using ROM by the positive number multiplication means of the above embodiment. FIG. 4 is a program flow diagram of multiplication according to the above embodiment, FIG. 5 is a hardware configuration diagram of a multiplication device according to another embodiment of the present invention, and FIG. 6 is a program flow diagram of a conventional example. 1... Positive number conversion means, 2... Positive number multiplication means, 3...
Multiplication correction means, 4... Addition means, 11... Computer, 11 a-... CPU, 12... ROM conversion table (ROM2).

Claims (2)

[Claims] (1) The multiplicand X(n
A multiplication device that multiplies a multiplier Y (m bits) by a multiplier Y (m bits), comprising: a positive number converting means for converting data in two's complement display format into a positive number; a positive number multiplying means for multiplying by a positive number; and the positive number multiplication device. A multiplication correction means for performing multiplication correction of the means, and an addition means for adding the output of the positive number multiplication means and the output of the multiplication correction means, and -^1+Σ^n^-^2_
i_=_0x_i・2^i-2^n^-^1=X_1-
2^n^-^1 Y=(1-y_s)2^n^-^1+Σ^m^-^2_
＾＿＝＿0y＿j・2＾＾j−2＾m＾−＾1=Y_1−
2^m^-^1 However, x_s and y_s are polar signs, x_i and y_i are numerical signs, and the product P (=X・Y) is expressed as the following formula: P=X_1・Y_1+@X@_1・2＾ m＾−＾1+＠
Y@_1・2^n^-^1+2^m^-^1+2^n^
-^1+2^m^+^n^-^2 However, @X@_1 is calculated according to the one's complement of X_1, and @Y@_1 is calculated according to the one's complement of Y_1. (2) The above positive number multiplication means each sets the multiplicand and the multiplier to 2
It is characterized in that it decomposes into the sum of two or more numerical values, adds the partial products of each decomposed value, and performs multiplication, and the calculation of the partial product by each decomposed value is performed using a ROM conversion table. A multiplication device according to claim 1.