JPS62232028A - Rom type multiplier - Google Patents

Abstract

PURPOSE:To enable multiplication of number including a negative number and a positive number by converting data expressed in complement of two to positive numbers, finding partial product of positive numbers, and making necessary multiplication correction process and addition of a specified constant when multiplying a multiplicand expressed in positive number and a multiplier expressed in complement of two. CONSTITUTION:Polarity sign Ys of Y is inverted by an inverter 2. For instance, when y2=0, 1-ys=1 is established and when ys=1, 1-ys=1, 1-ys=0 is established and such inversional relation of ys and 1-ys is utilized. A positive number Y1 can be derived from Y by this processing. X and Y1 are divided respectively to higher rank and lower rank 4 bits respectively, and made to XU, XL, Y1U, Y1L, and partial products of XU.Y1U, XU.Y1L, XL.Y1U and XL.Y1L are determined successively by combination of them from an ROM6. Further, the inverse of X is made by inverting X by an inverter 3. These signals and fixed numbers 2<15>+2<7> from a constant circuit 1 are carried by a data selector 7, added successively by an adder 8, and a product P can be obtained as parallel data of 16 bits.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a ROM type multiplier that performs multiplication of a multiplicand X expressed as a positive number and a multiplier Y expressed as a two's complement number.

[Conventional technology]

FIG. 4 is a diagram showing a ROM type multiplier developed by the present inventors. This is a circuit that multiplies the 8-bit multiplicand , 106 is an adder, 10
7 is a multiplication control circuit.

First, a method for deriving the product P will be explained with reference to equations [1] to [3] below.

X"X7 ・27+x,,'2' +X5 1'+
Xa '2'+X, ・23+x2 ・2" +)
(,・”2 + x.

-(X, ・23 +x, ・2” +xs ・2+X4
)2'+(X, ・2' +xt ・2" +X,
・2+xo)-Xu ・2' +XL
[1 piece X”yt・
2'+)'b・2'+3's・2' +y
, ・24+y3 ・2'+yt ・2"+y+
・2+y0=(y, ・23+yb ・2” +Ys
・2+y4)2'+(y, ・23+V2 ・2"
+y+ ・2+yo)=yu ・2' +YL
[2]P-X-Y"(XLI'2'+Xt)(Yu'
2' +Yt, )=X, ・Yo ・211+Xu −Y
L ・24+XL-YU ・2'+)CL' Y
L [3] Here, we assume that X and Y are 8-bit data, so the general formulas for X and Y can be expressed as the first formulas in formulas [1] and [2], respectively. . These are broken down into upper and lower 4 bits [1].

[2] This is the second 2 in formula. The top 4 bits of X
The third equation is where U, the lower 4 bits are XL, the upper 4 bits of Y are YU, and the lower 4 bits are YL. Therefore, the product P can be obtained as a sum of partial products as shown in equation [3]. In the formula, 28 and 24 indicate 8-bit and 4-bit carries, respectively. Therefore, the partial product X
u'Yu.

-x,,-=Xu ・YL, Xt -Yu, XL -Yt
can be found by any means. The ROM type multiplier is
A ROM is used as a means for deriving these partial products,
This derivation method will be explained next. The product of 4 bits x 4 bits has a numerical value range of 0 to 225. This number can be expressed in 8 bits. On the other hand, there are 256 addresses indicated by a total of 8 bits, 4 bits and 4 pins. If the combination of the 4-bit decomposition numbers Xu, xt, Y, . At this time, each ROM capacity may be 256 heights.

Next, the operation will be explained. 1ROM101~4thR
The OM 104 uses Xu and Yu, Xu and YL, XL and /u, and Xt and YL as addresses to find the respective partial products, the selector 105 executes carry according to the above formula [3], and the adder 106 sequentially calculates the partial products. The partial products are added to obtain the product P.

Multiplication control circuit 107 generates a select signal for selector 105 and a control signal for sequential addition.

A ROM type multiplier can be realized in the above manner.

[Problem that the invention seeks to solve]

Since the ROM type multiplier shown in Fig. 4 is configured as described above, it is possible to multiply positive numbers, but the problem is that it cannot multiply data in the corrected display format of 2, which includes positive numbers and negative numbers. There was a point.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a ROM type multiplier that is capable of multiplying data in a positive number display format and a two's complement display format.

[Means for solving problems]

The ROM type multiplier according to the present invention includes a positive number converting means for converting two's complement display data into a positive number, a partial product calculating means using a ROM that calculates a partial product of a positive number and a positive number, and a positive number converting means for converting a positive number into a positive number. The multiplication correction means includes a complementing circuit that performs complementing and a fixed numerical value generation circuit, and a synthesis addition means that synthesizes and adds the partial product and the output of the multiplication correction means.

[Effect]

In this invention, in order to multiply a multiplicand in a positive number representation by a multiplier in a two's complement representation format, after converting the data in a two's complement representation format to a positive number, a ROM is used to calculate the partial product of the positive numbers. Since the result is subjected to necessary multiplication correction processing and addition of a predetermined constant, it becomes possible to multiply a number including a negative number by a positive number.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

First, an algorithm for multiplying an n-bit positive multiplicand X and an n-bit two's complement multiplier Y will be described.

<y, is the most significant bit of Y, polarity sign) = Y, -2"
[5] P=X ・Y = x-y, -2'-' ・X [7] (
xs is the polarity sign) -XI =x+ +i=x+2' +i [9]
P=X-Y, -2'-' ・X =X -Y, -2'''-1・X1 = X ・y+ + (2'''+X+1
) ・ 2 ′″-' [10 pieces P=
X-Y, +X ・2n-1+ 2 Zr+-
+ + tl n-1 [11 The formula [4] is a general formula for a positive number X, and the formula [5] is a general formula in two's complement representation format.

y is a polarity sign, and generally when Y≧00, yS is “0
", when Y<0, ys is 1". At this rate, Y
Since there is a negative sign in and cannot be multiplied, (2” −2'
The equation rewritten by adding -') is shown in [6].

At this time, Y becomes 1)'5-Oorl, so
It can be considered a positive number. [7] Part 2 shows the process of deriving P=X・Y. Here, the value -X appears, but since X is a positive number, there is no concept of negative. Therefore, let X be a number X1 in a two's complement representation format of (n+1) bits, such as [8]2. The polarity code X is the value of the (n+1)th bit, and since X is always a positive number, it is χ,−“′0”. [8] Formula is a general formula for X, and as a numerical value,
It can be seen that =X. Therefore, -X-X+.

In formula [9], -X is expressed as X and a constant using the identity expressed in two's complement form -X+ = X+ + 1. '[10] indicates the part after equation [7] in the process of deriving P-X-Y. Equation [11] shows a general equation for obtaining the product P of the transformed two's complement display data Y1 and the positive number X.

This is the multiplication algorithm employed in the present invention. [1
1], where X'Y+ can be multiplied by the same means as in FIG. 4 above, or can be realized by simple bit inversion of X. Note that 2 n-1 indicates carry focus.

FIG. 1 is a block diagram showing an embodiment of the present invention.
The product P is determined according to the method described above. In the figure, it is assumed that both X and Y are 8 bits (n=8). 1 is a fixed number 21 S +a,? A constant circuit that generates
2 is an inverter, 3 is 8 inverters, 4 and 5 are Xu
, Xt, or Y, , Y, L2
/1 selector, 6 is a ROM for calculating partial products, 7 is a data selector that performs a predetermined carry, 8 is an adder, 9 is a flip-flop for temporarily storing the added data, 10 is an overall This is a multiplication control circuit that performs control.

Next, the operation will be explained. Y polarity sign y.

Invert with impark 2. For example, when Ys-0, 1)'s=1, and when y, -1, 1-ys=
This takes advantage of the fact that y and 1-y are in an inverse relationship. Through this process, a positive number Y can be derived from Y. Divide X and Yl into upper and lower 4 bits each as in the case of FIG.
u, Yet and None, the combination of these, Xu
・You, Xu' Yet, Xt ・Y
IU+ and XL ・Y, L (7) partial products are sequentially ROMed
Decide from 6. Furthermore, Y is created by inverting (1's complement processing) X using an inverter 3. These signals and constant circuits
The fixed number 215.4-27 from 215.4-27 is carried by the data selector 7 according to formulas [3] and [11], and the adder 8 performs the sequential addition to obtain the product P as 16-bit parallel data. can.

In the above embodiment, the inverter 2 is a positive number conversion circuit that converts data in two's complement display format into a positive number, the inverter 3 and constant circuit 1 are a multiplication correction circuit, and the 2/1 selector 4 is a positive number conversion circuit.
, 5 and ROM 6 constitute a circuit for calculating partial products of positive numbers, and data selector 7, adder 8 and flip-flop 9 constitute addition means for adding the above partial data groups according to the algorithm of the present invention. Here, the multiplication control circuit 10 receives, for example, a clock and a start signal as input, and controls each of the above-mentioned circuits according to a predetermined procedure.

Furthermore, in the above embodiments, the multiplication algorithm is implemented using hardware, but the multiplication algorithm may also be implemented using a program such as a one-chip microcomputer.

Next, FIG. 2 shows another embodiment of the present invention in which the multiplicand X expressed as a positive number and the multiplier Y expressed as a two's complement number are both 8 bits, and an 8-bit microcomputer is used. In Figure 2, 11 is an inverter that inverts the most significant bit of Yu, 12.13 is 1 byte I10 port Po, P
+, and I4 is a one-chip microcomputer. In the one-chip microcomputer 14, 15 is the CPU, 16 is the internal R
OM, 17 is a 2-byte I10 port p,,p.

It is.

This one-chip microcomputer 14 performs multiplication using equation [11] according to the program chart in FIG. That is, first, X is decomposed into Xll and XL, and Xu is inputted into the upper 4 bits of Po, and XL is inputted into the upper 4 bits of P. Y
Yl is created by inverting the most significant bit of
Input u to the lower 4 bits of Po and YIL to the lower 4 bits of Pl.

As a result, the input of Po is Xu ・2' +Y,...
The input of p+ is XL.2'+YIL. This Po.

In step A, P is assigned to the registers R, , R, respectively, and in step B, 3 is stored in the loop control register i in order to obtain the partial products four times below.

Xu' YILI, XL in step C respectively
”/+t.

Set Xu -Yet and XL' You in the internal ROM address in order, and in step D
The output of is stored in registers B, ~B0. Step E
Repeat the loop from steps C to D four times. X in step F
is inverted and assigned to register R5. Finally, in step G, addition is performed based on formulas [3] and [11] to calculate the product P, and in step H, P2 and P:l
Outputs to 16 boats in total.

Note that in the above two embodiments, the case of 8 bits x 8 bits was considered, but generally speaking, in the case of multiplication of α x β focus,
Of course, it can also be executed in the same way.

〔Effect of the invention〕

As described above, according to the present invention, there is a means for converting either the multiplicand or the multiplier in two's complement representation format into a positive number, a means for calculating the multiplication product of positive numbers using a ROM,
The RO
Since an M-type multiplier is configured, a general-purpose and inexpensive R
The advantage is that multiplication of arbitrary numbers including positive numbers and negative numbers can be realized using OM and general-purpose TTL devices.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a ROM type multiplier according to one embodiment of the present invention, and FIG. 2 is a block diagram of another embodiment of the present invention in which the above-mentioned ROM type multiplier is realized using a one-chip microcomputer. , FIG. 3 is a flowchart of the calculation according to the other embodiment described above, and FIG. 4 is the RO developed by the inventor.
FIG. 2 is a block configuration diagram showing an M-type multiplier. In the figure, 1 is a fixed number generation circuit, 2 is an inverter forming a positive number conversion means, 3 is an inverter forming a 1's complement conversion circuit, 4.5 is a 2/1 selector, 6 is a ROM, and 7
is a data selector, 8 is an adder, 9 is a flip-flop, 10 is a multiplication control circuit, 11 is an inverter, 12.13
is input board, 14 is one-chip microcontroller, 15 is CP
U, 16 is internal ROM, 17 is output port, 101-1
03 is a ROM for calculating partial products, 105 is a selector, 10
6 is an adder, and 107 is a multiplication control circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (3)

[Claims] (1) When the multiplicand X in positive number representation and the multiplier Y in two's complement representation are expressed as in the following formulas [A] and [B], the product P of the above X and Y is expressed as in the following formula [C]. A ROM type multiplier characterized by the following: X=Σ^n^-^1_i_=_0x_i・2^i[A]
Y=-y_s・2^m^-^1+Σ^m^-^2_j_
=_0y_j・2^j[B] (y_s is the polarity sign of Y) P=X・Y_1+@X@・2^m^-^1+2^m^+
^n^-^1+2^m^-^1 [C] (Y_1=Y+2
^m^-^1) (2) A positive number conversion means for reversing the polarity sign of data Y in two's complement representation to obtain a positive number Y_1, and for obtaining a plurality of partial products of the product X·Y_1 of the positive number Y_1 and the positive number X. a ROM, a multiplication correction means comprising a complement circuit for converting the positive number X into a one's complement, and a fixed number generation circuit for generating a fixed number; R according to claim 1, further comprising an adding means for performing carry processing and adding these.
OM type multiplier. (3) A ROM type multiplier according to claim 1 or 2, characterized in that the above multiplication is realized by using a one-chip microcomputer.