JPH08190471A - Multiplier - Google Patents

Abstract

PURPOSE: To perform multiplication by the use of one adder as for the multiplier which performs binary multiplication. CONSTITUTION: A 1st input B is outputted, bit by bit, from a serial/parallel converter 111 to a selecting means 104 with a clock signal. The selecting means 104 selects and outputs one of 2nd input data 101, the inverted data 102 of the data 101, and zero data 103 according to the output 112 of the serial/parallel converter. An adding means 107 adds the output 105 of the selecting means 104, the output 106 of a storage means 109, and the output 112 of the parallel/ serial converter 111 together and outputs their addition result 108. A storage means 109 stores the addition result 108 according to the control signal of a control means 113 and supplies it to the adder 107.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplier for multiplying any two values.

[0002]

2. Description of the Related Art A conventional multiplier is shown in FIG. Here, the case where the input A and the input B are each 4 bits will be described as an example. In FIG. 6, the input 603 from B is selection means 60 one bit at a time from the lower bit.
4 and the selecting means 604 selectively outputs one of the data 601 and the zero data 602 input from A according to the input from B, and the adder 607
The output 605 of the selection means 604 and the zero data 606 are added, and the result is output to the storage means 613 and the adder 608. Similarly, the adders 608, 609 and 610 respectively add the outputs of the adders 607, 608 and 609 and the output 605 of the selection means 604 and output the results to the adders 609 and 610 and the storage means 613, respectively. To do. The storage means 613 stores the four adders 607, 6
The outputs of 08, 609 and 610 are stored and output according to the output of the control means 614, and the control means 614 outputs a control signal to the storage means 613.

Next, the operation will be described. First, the value of the least significant bit of input B is input from B, and this signal 603 is input.
Is output to the selection unit 604. The selecting means 604 selects either the input 601 from A or the zero data 602 by the output of the signal 603, and sets the number of the 4th bit of the selected data to the 5th bit or 5 bits (hereinafter It is called sign extension). The selecting means output 604 is added to the zero data 606 by the adder 607 and output to the storage means 613, and the upper 4 bits are 5
The bits are sign-extended and output to the adder 608. The storage means 613 stores the least significant bit of the output 611 of the adder 607 according to the control signal of the control means 614.

Next, the value of the second bit of the input B is input, and this signal 603 is output to the selecting means 604. The selecting means 604 selects either the input 601 from A or the zero data 602 according to the output of the signal 603,
In addition, it sign-extends to 5 bits and outputs. In the adder 608, the selection means output 605 is added to the addition result 611 of the adder 607 and output to the storage means 613, and the upper 4 bits are sign-extended to 5 bits and output to the adder 609. The storage means 613 is the control means 6
The control signal of 14 stores the least significant bit of the output of the adder 608.

In this way, the same operation is performed for the value of the third bit of the input B, and subsequently the value of the fourth bit, resulting in B
The result of multiplication of the least significant bit of the input from A and the input from A, the result of the multiplication of the second bit of the input from B and the input from A, and the third bit of the input from B and A The least significant bit of the multiplication result with the input of
13 and the most significant bit of the input from B and A
The multiplication result with the input from is stored in the storage means 613, and the storage means 61 is controlled by the control signal of the control means 614.
It is output from 3.

[0006]

However, the above-mentioned conventional technique has a problem that the number of multipliers is required and the circuit scale becomes large. For example, if two inputs are 4 bits, then four adders are required. Therefore, the present invention solves such a problem, and an object of the present invention is to configure a multiplier with one adder.

[0007]

In a multiplier for multiplying any two inputs, the first input is set to 1 by a clock.
A parallel / serial converter that outputs bit by bit,
Selecting means for selecting either the second input data, the data obtained by inverting all the bits of the second input, or the zero data according to the output value of the parallel-serial converter; and the output of the selecting means. An adding means for adding a carry input selected by the output of the storing means and the output of the parallel-serial converter, a pulse generating means for generating a pulse to the storing means by a clock, and an output of the adding means. The lower bit is stored in synchronization with the pulse generated by the pulse generating means, and the output result of the adding means is output to the adding means.

[0008]

FIG. 1 shows a schematic diagram of the present invention. The parallel-serial converter 111 outputs the serial output 112 bit by bit in order from the lower bit in synchronization with the first data 110 input from the outside in synchronization with the clock signal, and the selection unit 1
Reference numeral 04 denotes the second data 101 inputted from the outside and the data 10 obtained by inverting all the bits of the input data 101.
2 or zero data 103 is selectively output according to the output 112 from the parallel-serial converter 111, and the adding means 107 outputs the output 105 of the selecting means 104 and the output 106 of the storing means 109. Are added and the addition result 108 is output, and the storage means 109 stores the least significant bit of the addition result 108 according to the output from the control means 113 and outputs the bits other than the least significant bit to the addition means 107. Then, the control means 113 outputs a control pulse to the storage means 109 in response to the input of the clock signal.

FIG. 2 shows an embodiment of the present invention. In this example, two input data, that is, a first input B and a second input A are multiplied by three control signals of a basic clock SCLK, a reset signal RESET, and an enable signal EN for enabling multiplication, and the result is obtained. Output M. The first input B, the second input A, and the output M are all represented in 2's complement. First, by switching RESET and then by switching EN, the first input 21 from the outside
5 is loaded into the parallel / serial converter 216, and the parallel / serial converter 216 receives the basic clock SC.
The serial output 217 is sequentially output bit by bit from the lower bit by LK. The parallel / serial converter 216 is composed of, for example, a shift register for parallel input / serial output. The second input 201 is the selector 203, and the parallel / serial converter 2
When the value of the most significant bit B3 of the first input B output from 16 is 1, the data 202 obtained by inverting all the bits of the second input A becomes the input of the selector 204, and when the value of B3 is 0, The second input 201 is the selector 2 as it is
It becomes the input of 04. The selector 204 selects the second input when the output of the parallel-serial converter 216 is 1, and zero data when the output is 0, and adds the same value as the most significant bit of the data to the next higher digit (hereinafter It is output as a selector output 205 (referred to as sign extension). Adder 2
07 is the selector output 205 and the data latch 209
And the sign-extended output 214 from
8 is output. In the selector 206, when the value of the most significant bit B3 of the first input output from the parallel / serial converter 216 is 1, the carry input is 1
When the value of B3 is 0, carry input is set to 0 and addition is performed. This operation is such that the first input and the second input are values expressed in two's complement, and all the bit inversions of the second input and the sign inversion of the second input by adding 1 to the least significant bit. Means that you are doing. The latch clock generator 218 is composed of, for example, a shift register or the like, generates a signal having one pulse in one multiplication sequence from the basic clock SCLK, and outputs it to the latch 213, the latch 212, the latch 211, and the latch 210 in the order of pulse generation. It is output as the latch clock 219. The latch 21
3, 212, 211 and 210 are latch clock generators 2
The addition result 2 by the latch clock 219 from 18
08 least significant bit is latched and the data latch 20
9 latches all bits except the least significant bit by the basic clock SCLK, and inputs 214 of the adder 207.
Supply as.

FIG. 3 is a timing chart showing the operation of each part of the embodiment shown in FIG. Enable signal EN
The first input is loaded into the parallel-to-serial converter 216 after the falling edge of, and the least significant bit B0 is transferred to the selector 204 at the first rising edge of the basic clock SCLK.
Is output to Since the data of the second input A is selected by the selector 204, this data and the output 214 of the latch 209 are added by the adder 207 and S0 is output.
The least significant bit of this adder output S0 is latched in the latch 213 by the latch clock 219 (latch clock 0) to the latch 213 output from the latch clock generator 218, and at the same time, the upper 4 bits are the next basic clock SCL.
At the rising edge of K, it is latched by the latch 209, sign-extended, and supplied to the adder 207. This latch 2
The second bit B1 of the first input is output to the selector 204 at the same time as the rising of the basic clock SCLK that serves as the latch pulse of 09, and the same operation is performed thereafter.
The least significant bit of 1 is the latch clock 2 to the latch 212
It is latched in the latch 212 by 19 (latch clock 1). As a result, the least significant bit of the addition result S2 is sent to the latch 211 by the latch clock 219 (latch clock 2) to the latch 211, and the least significant bit of the addition result S3 is sent to the latch 210 by the latch clock 219 (latch clock 3). Respectively latched to
Basic clock SC after the fall of enable signal EN
At the 5th rising edge of LK, the upper 4 bits are aligned in the latch 209, resulting in an 8-bit multiplication result.

Next, the operation will be described according to the input data shown in FIG. In the input example, both A and B have 4 bits, and when the most significant bit of the input is 1, the input is a negative number and is represented as 2's complement data. Therefore, the input A represents a positive number and the input B represents a negative number. Further, the initial value of the output 214 from the latch 209 which is the input of the adder 105 is set to zero data.

When the reset signal RESET is switched to 0 level and then the enable signal EN is switched to 0 level, the first input B and the second input A are loaded. The first input B is loaded into the parallel / serial converter 216, and the value 1 of the least significant bit B0 is output as the serial output 217 in synchronization with the rising edge of the basic clock SCLK. The second input A is loaded to the selector 204 as it is, and the selector 204 outputs the serial output 2
The data of the second input A is selected by 1 of 17 and is sign-extended and output as the selector output 205. Latch 20
Since the initial value of the output 214 of 9 is zero data, the zero data and the selector output 205 are added in the adder 207.
Value is added to output the adder output 208 to the data latch unit 22.
Output to 0. In the data latch unit 220, the latch 213 latches the least significant bit of the adder output 208 by the clock 219 from the latch clock generator 218, and the upper 4 bits are supplied from the latch 209 to the adder 207.

The value 1 of B1 and the next basic clock SC in synchronization with the rising edge of the next basic clock SCLK.
The value of B2 is 0 at the rising edge of LK, and finally B
The value 1 of 3 is output from the parallel / serial converter 216 to the selector 204, and these serial outputs 217 are set to 1
In the case of, the second input A is sign-extended and output as it is to the adder 207, and in the case of 0, the zero data 4 bits are sign-extended and output to the adder 207. Also, B3 is 1
Therefore, the selector 203 selects all the inverted data (1's complement) of the second input A and selects the selector 204.
Is input to the adder 207 and is sign-extended. Then, the selector 206 selects 1 as the carry input of the adder 207 (two's complement). The adder 20
In No. 7, the carry input is added when the output 214 of the latch 209, the selector output 205, and the most significant bit B3 were previously multiplied. The higher 4 bits of the addition result 208 of the 5th bit of the 2nd time and the 3rd time are sign-extended and added to the adder 2
It becomes the input of 07, and the least significant bit is latch 21 respectively.
2, latched by the latch 211, and the fourth addition result 20
The 8 least significant bits are latched in the latch 210, and the upper 4 bits are latched in the latch 209, and finally the 8-bit multiplication results are obtained.

The calculation process of the embodiment using the input data of FIG. 4 is shown in FIG. When the input data of FIG. 4 is represented by a decimal number, A is +5, B is a negative number, which is a two's complement representation, and is -5. 5 shows the output data 205 of the selector 204, is the data 201 with the second input selected as it is, is the value with zero data selected, and is the data obtained by inverting all the bits of the second input. This is the value for which 202 is selected. Further, is the output data of the adder 207, and is the result of adding zero data that is the initial output of the latch 209 to the value obtained by sign-extending the upper 4 bits of This is the result of adding the above output 214 of the latch 209, and similarly is the result of adding the above output 214 of the latch 209 to the sign-extended value of the upper 4 bits of. Indicates a carry input to the adder 207 in the selector 206. Is a result obtained by adding the carry input and the output 214 of the latch 209 to a value obtained by sign-extending the upper 4 bits of the.
JK indicates the multiplication result output from the data latch unit 220 as a result. The result of this multiplication is a two's complement representation, which is -25 when expressed in a decimal number, and it can be seen that the multiplication according to this embodiment is certainly correct.

As described above, when a certain value is added once, if the least significant bit is stored and the other bit-extended digit is used as the input for the next addition, one adder can be used to multiply the number of digits. It is possible to

[0016]

As described above, according to the present invention, since a multiplier can be configured with one adder, the circuit scale can be reduced. Further, as can be seen from FIG. 3, the time required for the multiplication is held until the result is fixed at 5 clocks from the next rise of the basic clock SCLK when the enable signal EN changes to 0 level and the enable signal EN becomes 1 level. You can see that One of the applications that can use such time-division processing is affine transformation that performs scaling rotation, which is often used for image processing. In such use, not only the circuit scale is reduced but also low power consumption is achieved. It becomes possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing an outline of the present invention.

FIG. 2 is a block diagram showing an embodiment of the present invention.

FIG. 4 is an input data diagram used for explaining the present invention.

FIG. 5 is an output data diagram used for explaining the present invention.

FIG. 6 is a block diagram showing a conventional example.

[Explanation of symbols]

101 Second Input Data 4 Bits 102 Second Input Data 4 Bits Inversion 103 Zero Data 104 Selection Means 105 Selection Means Output 5 Bits 106 Storage Means 109 Output 5 Bits 107 Adder 108 Adder Output 5 Bits 109 Storage means 110 First input data 4 bits 111 Parallel / serial converter 112 Serial output of parallel / serial converter 111 113 Control means 201 Second input data 4 bits A0, A1, A2,
A3 202 Inverted data of 201 201 4 selectors of 201 and 202 204 Selector 205 Output of selector 204 5 bits 206 Adder 207 carry input selector 207 Adder 208 Adder 207 output 209 209 Upper 4 bit latch 210 Latch of the least significant bit of 208 (the result of the fourth addition) 211 Latch of the least significant bit of 208 (the result of the third addition) 212 208 Latch of the least significant bit of 208 (the result of the second addition) 213 208 (the first time) Latch of least significant bit of addition result) 214 Output of latch 209 sign-extended 215 First input data 4 bits B0, B1, B2,
B3 216 Parallel / serial converter 217 Serial output of parallel / serial converter 216 218 Latch clock generator 219 Output of latch clock generator 218 4 bits 220 Data latch unit 601 4 bits of input data from A 602 Zero data 603 1 bit Input data from B 604 selection means 605 selection means output 604 606 zero data 607 adder 608 adder 609 adder 610 adder 611 adder 607 output data 5 bits 612 adder 610 output data 5 bits 613 storage means 614 control means

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[Procedure amendment]

[Submission date] November 25, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 is a block diagram showing an outline of the present invention.

FIG. 2 is a block diagram showing an embodiment of the present invention.

FIG. 3 is a timing chart of the operation of each part of the embodiment of FIG.

FIG. 4 is an input data diagram used for explaining the present invention.

FIG. 5 is an output data diagram used for explaining the present invention.

FIG. 6 is a block diagram showing a conventional example.

[Description of Reference Signs] 101 second input data 4 bits 102 second input data 4 bits inversion 103 zero data 104 selection means 105 output 5 bits of selection means 106 output 5 bits of storage means 107 adder 108 adder Output 5 bits 109 storage means 110 first input data 4 bits 111 parallel-serial converter 112 serial output of parallel-serial converter 111 113 control means 201 second input data 4 bits A0, A1, A2,
A3 202 Inverted data of 201 201 4 selectors of 201 and 202 204 Selector 205 Output of selector 204 5 bits 206 Adder 207 carry input selector 207 Adder 208 Adder 207 output 209 209 Upper 4 bit latch 210 Latch of the least significant bit of 208 (the result of the fourth addition) 211 Latch of the least significant bit of 208 (the result of the third addition) 212 208 Latch of the least significant bit of 208 (the result of the second addition) 213 208 (the first time) Latch of least significant bit of addition result) 214 Output of latch 209 sign-extended 215 First input data 4 bits B0, B1, B2,
B3 216 Parallel / serial converter 217 Serial output of parallel / serial converter 216 218 Latch clock generator 219 Output of latch clock generator 218 4 bits 220 Data latch unit 601 4 bits of input data from A 602 Zero data 603 1 bit Input data from B 604 selection means 605 selection means output 604 606 zero data 607 adder 608 adder 609 adder 610 adder 611 adder 607 output data 5 bits 612 adder 610 output data 5 bits 613 storage means 614 control means

Claims (1)

[Claims] 1. A multiplier that multiplies any two inputs, a parallel-serial converter that sequentially outputs the first input bit by bit by a clock, and the parallel-serial converter.
Selection means for selecting either the second input data, the data obtained by inverting all the bits of the second input, or the zero data according to the output value of the serial converter, and the output and storage means of the selection means. Of the carry input selected by the output of the parallel-to-serial converter, pulse generating means for creating a pulse to the storage means by a clock, and the least significant bit of the output of the adding means. A multiplier comprising storage means for storing in synchronism with a pulse generated by the pulse generating means and for outputting an output result of the adding means to the adding means.