JPS58144260A - Multiplier for two's complement - Google Patents

Abstract

PURPOSE:To reduce the number of basic blocks, by inverting numeral bits into positive numbers when a multiplicand and a multiplier are negative. CONSTITUTION:In the multiplication of a multiplicand and a multiplier displayed in the input signal format of two's complement, -1 is added to the multiplied result by using total adders 601-615 before the inversion of the multiplied result, and then the added result is inverted to obtain the multiplied result displayed as two's complement. Therefore when a multiplier is constituted by n X n bits, the multiplier requires only n<2> - 1 stage basic addition blocks, reducing the number of basic block elements.

Description

[Detailed description of the invention] The present invention relates to a two's complement multiplier.

Binary multipliers have various circuit systems depending on the input signal format. , the multiplicand X and the multiplier Y are (1).

In the case of a positive integer representation as shown in equation (2), the product ζ is as shown in equation (3).

p=x, yJ ri<x, -y,)@2川−2(3)゛l211=1 Here, n is the bit word length of the multiplicand X, m is the bit word length of the multiplier Y, X4 ．． ．． 7i represents each bit.

The multiplication process in equation (3) is as follows when the bit word length of the multiplicand 9 multiplier is 4 bits, and "4"3
"2"1 "4'1"3"1 "2"1 "1"1"472"
372 “2”2 “1y2”4”3 “3ya”2
73 "1" 3P8P7P6P6P4P3P2P1 The answer is the sum of the partial products x1 + 71 of each pi y).

A circuit configuration for performing such multiplication is shown in FIG. In the same figure,! , ~x4 is each bit of the multiplicand X, 71~
y4 is the input terminal for each pin of the multiplier Y, P1 to P8
is each bit output terminal of the product P.

Reference numerals 1 to 7 are AND gates, which are constructed as shown in FIG. 3 using the turnout half adder shown in FIG. In the figure, 301 is an AND gate, 302 is a half adder, and the door is half 1. The sum output of the device, C.

is a carry output. 11 to 16 are AND gates and full adders constructed as shown in FIG. In the figure, 4o1 is an AND gate, 402 is a full adder, Ci is a carry input of the full adder, S is a sum, an output, and C
o is the carry output/output, 017 is the half adder, K
, Ci are input terminals, S is a sum output, and Ci is a carry output terminal. Reference numerals 18 and 19 are full adders, a and a are input terminals, Ci is a carry input, white is a sum output, and Co is a carry output terminal.

With such a circuit configuration, by generating partial products using an AND gate and adding them using an adder, it is possible to perform the multiplication of the multiplicand and the multiplier shown in the multiplication process described above. Although FIG. 1 shows multiplication in the case where both the multiplicand and the multiplier are expressed as positive integers, in digital signal processing, calculations are often performed in two's complement representation because of the ease of processing.

In multiplication in two's complement representation, the multiplicand X and the multiplier X are (4
), (6), and the product P is as shown in equation (6).

・・・・A6) Here, 5. xli and y8 are sign bits, (6
), the second term is "1" as seen from equation (3).
Although calculations can be performed using the array method shown in the figure, the first term and the third term. Correction of the fourth term is required, and the circuit configuration becomes complicated. Therefore, a proposal has been made to simplify the circuit configuration by modifying equation (6) as shown below.

・・・・・・・・・(A) In equation (7), the first term (x8・V8−”B−V′
S) Ha! Since it can be found by OR operation between 8 and y8, (7
) The multiplication process of the equation is as follows.

X 813!2 X 1 xsy1x3y1x2y1!1y1 ”sy2 x3y2°2”2 ”1y2”sV3 ”3
ya "273" 1y3 here, X8+7. indicates the OR operation of x6 and y8, and P8 indicates the sign focus of the product output.

In order to perform the multiplication of equation (7), the configuration of the heading path is as shown in FIG. In the figure, x1 to XB are input terminals for each bit of the multiplicand X, y1 to y8 are input terminals for each bit of the multiplier Y, and output terminals for each bit of the p-p g product.However,! s * y, 8 + P' B is
They are the code pids of X, Y, and P, respectively, and are 11 to x3. y
1 to "31 P1 to P6 are numerical bits of X, Y, and P, respectively. 501 to 506 are AMq shown in FIG.

Gate 507 is an OR gate. , 6φ8~510
is the AND game shown in FIG. 3) 3'01 and the half adder 302.
Blocks 611 to 616 are blocks consisting of an AND gate 401 and a full adder 402 shown in FIG. 4, and blocks 617 to 620 are full adders. 621-52
6 is body/verter, and when generating a partial product of the sign bit x of the multiplicand
To generate a partial product between and the numeric bits (!, ~X S ) of the multiplicand
By adding the s OR output to the digit corresponding to Ps, the multiplicand and the multiplier can be multiplied in two's complement representation as shown in the multiplication process described above.

nXn using the circuit system shown in Fig. 1 and Fig. 6.
For bit multiplication, the block shown in FIG. 4 consisting of ANL) 401 and full adder 402 is
Therefore, the multiplication speed is the sum of delays of (2n) stages of this basic block. In addition, the circuit configuration is a basic block (n+n
-1) It becomes a stage.

The present invention aims to provide a complement multiplier that improves the multiplication speed and reduces the number of elements in multiplication using two's complement representation. That is, when the multiplicand and the multiplier are positive, only the numerical bits are multiplied, and when they are negative, the numerical bits are inverted and converted to a positive number before multiplication is performed.

An embodiment according to the present invention is shown in FIG. 66 below. Same figure ζ
In this case, 801 to 609 are $, and processors 628 to 63 consisting of an AND gate 401 and a full adder 40 distortion shown in FIG.
4 is AND gate, 636 is Exclusive OR
It is a gate. In the figure, a select signal 701 causes an input signal 702 or an inverted input signal to be sent to an output terminal 703.
Output to. 704 and 705 are AND gates, 706 is an OR gate, and 707 and 708 are inverters.

(a) When the multiplicand X and the multiplier Y are both positive values, the multiplication only requires calculation of numerical focus, as shown below.

o(x8)x3x2x1 x )O(:8) y3 y2 yl”3”1
"2"1 "1"1 "3V2 "2"2 !1"2 (b) In multiplication when the multiplicand X is negative 9 and the multiplier Y is a positive value, first, the numerical bits x, ~ -, and construct a partial product with the numerical value of the multiplier Y') y1 to y3.

Here, if X is negative, the value of X is BINOTO! If the value obtained by inverting 1 to x3 is X', then 1 X ) - = X' + 1
......The relationship is as shown in (7).

For example, -3 becomes 1101 in complement representation, but if you invert numerical bit 101, it becomes 010, which is + from the absolute value of -3.
It decreases by 1. Therefore, by adding 1 to the inverted numerical value bit, the absolute value is obtained (0).Also, since it is a multiplication of a negative value and a positive value, the product output is negative. Therefore, each bit of the addition output of partial products is inverted and a sign bit is added, but if the addition output of partial products is P', and the value obtained by inverting and adding the sign bit is P (P1=P '-1・
......The relationship is as shown in (8). Therefore, P'
1 must be added to the inverted value. This is equivalent to subtracting 1 from the value P' before inversion and then inverting.

The above multiplication process is shown below. First, when the multiplicand X is negative and the multiplier Y is positive, the value X' obtained by inverting the numerical bits of X is lXl-1, so Y must be added to the partial product of each focus. Therefore, it becomes as follows.

1(!,) x3x2x1 P6P5P4P3P2P1 x8■”BP6P6'4 '3 '2 '1(P
8) Here, you may invert the multiplication result (the sum up to the pA part) and then add 1 to display it as a complement, but if you do this, six new full adders will be added after the select circuits 622 to 627. It becomes necessary. Therefore, in this embodiment, full adders 601 to 616 are used to eliminate this drawback.

In other words, before inverting the multiplication result, the full adders 601~61
6 is used to add -1 to the multiplication result, and then it is inverted to obtain the multiplication result expressed as a complement.

In addition of partial products, adding 111111 means adding -1. Also x8■y
8 is! Represents the exact OR of 8 and y8. Multiplication when the multiplicand X is positive and the multiplier Y is negative can be considered in the same way, and the calculation process will be shown below.

0(zs) x3x2x1 x) 1(y,) y3 y2 yl”3”1
”2”1 ”171 ”372 ”2y2 ”1”2 ”3y3 ”2”3 ”1”3 3C33C2! 1 P6P6P4P3P2P1 xs+■y8P6P''5p4P3'2 'j (P8
) Explaining this using Figure 6, if the multiplicand X is negative and the multiplier Y is positive, then X is "1" + 7. is "On," so the signals of
1'1172. While sending y3 to the adder, the AND gates 631 to 633 input the numerical value bits 74 .
Add V2e 73 to the adder. At this time, Antogame)
The outputs of 62B to 630 are O''.The Exctusive OR635 output of Xs and y8 is 1'', so 1Add this signal to each digit and perform the operation of -1,
The signal is applied to select circuits 622 to 627, the addition output signal is inverted and output, and PsK "1" is output as a sign bit.

If the multiplicand X is positive 9 and the multiplier Y is negative, x8 is O″y,
Since U"1.", the select circuits 616-621 select the numeric bits X1. X2. Xa and an inverted signal Y1t 72+ 7a of numerical bits of Y are output. or,
The outputs of AND gates 631 to 633 become O", and 62
yl for outputs 8-630.

V2+73 is output and added to the adder.

Since the output of the Ezczusiva OR635 is 1'', 1 is added to each digit and a -1 operation is performed, and the addition output signal of the select circuits 622 to 627 is inverted, and the sign bit P8 is set to 1. As described above, in multiplication when one value is negative and the other value is positive, the calculations shown in the calculation process described above are performed.

Next, in multiplication when the multiplicand X and the multiplier Y are both negative (as shown in the scheme, the numerical bits of X
The inverted value X' and the numeric bit y1 of Y. y2.
The value Y' that is the inversion of y3 is X' = 1λ1-1 Y' = 1 Y 1-1, so the product of both is X'・Y' = l X l・IYI-IXI-IYl
0 which becomes +1 Therefore, if we add X' and Y' to this value, we get X'・Y'+ A'+ Y'= l X l・11'l
-1.

Therefore, when both X and Y are negative, multiplication is performed by the following calculation process.

(Left below) 1 (x, ) xa
Numerical hiratono reversal signal,! IX2. ! 3゜y4. Te2. te is output. Mata and gate 628
By 634, '11'2+'3171? Te2.
Te. is added to the adder, and the at output "1" of xs, y, and I is added to the least significant digit of the adder by the output of 634. Since the product output is a positive value, Ji:xc
Due to the output of the tough OR 635, the addition results are output as they are to the outputs of the select circuits 622-62-.

From the above explanation, it can be seen that multiplication in two's complement representation can be performed in the configuration example shown in FIG.

As described above, according to the present invention, when configuring an nXn bit multiplier, the basic addition block only needs to have n2-1 stages, and the other select circuits and AND gates have simple gate configurations, as shown in FIG. Compared to the conventional method of n2+n stages, the number of elements is reduced by approximately n+1 stages. According to the present invention, the maximum signal propagation path that determines the multiplication speed is the sum of the select circuit, one AND gate, and 2n-1 stages of the configuration block shown in FIG. is a simple gate configuration, so
It can be considered as a block configuration of n-1 stages. In the conventional method, the delay is due to the block configuration of 2n stages, so the multiplication speed can be increased by one stage of the block configuration.

Conventionally, when integrating these multipliers into integrated circuits, there were problems in that as the number of bits increased, the chip size increased and power consumption increased, but according to the present invention,
Since the number of basic blocks is reduced, the chip size is reduced, and power consumption is also reduced, which is very effective.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a conventional example of a positive integer multiplier, Figs. 2, 3, and 4 are explanatory diagrams of the blocks in Fig. 1, and Fig. 6 is a conventional example of a two's complement multiplier. FIG. 6 is a block diagram showing an example of the block configuration of a two's complement multiplier according to the present invention, and FIG. 7 is a detailed diagram of the select circuit in FIG. 6. 601-609...Block including AND gate and full adder, 610-616...Full adder,
616-627...Select circuit, 704°7
05...AND gate, 706...O
R Gate, 7o7. -708...Inverter.

Claims (1)

[Scope of Claims] (1) A multiplier whose input signal format is a two-number multiplication of a multiplicand and a multiplier in two's complement representation, and which converts a negative input signal to a positive value and performs the multiplication. A two's complement multiplier comprising: (2) means for the multiplication means to multiply only numerical bits when both of the input signals of two numbers are positive; and when the input signals of the two numbers are negative, one is negative and the other is positive; means for multiplying a value obtained by inverting the numerical bits of the signal by the numerical bits of the positive input signal; and means for adding the numerical bits of the pressure input signal to the multiplication result;
When both of the numerical input signals are negative, means for inverting the numerical bits of both input signals and performing multiplication; 2. A two's complement multiplier according to claim 1, further comprising means for adding 1 to a lower digit. (3) The input signal format is binary multiplication between a multiplicand and a multiplier in two's complement representation, and when the input signal is negative, it is converted to a positive value and multiplied, and the multiplication means and the output of this multiplication means 2's complement multiplier, characterized in that it has an output means for converting the multiplication result into a negative value and outputting the result when is negative. (4) means for causing the multiplication means to multiply only numerical bits when both input signals of two numbers are positive;
means for multiplying a value obtained by inverting the numerical bits of the negative input signal by the numerical bits of the positive input signal when one of the numerical input signals is negative and the other is positive, and the two numerical input signals 4. A two's complement multiplier according to claim 3, further comprising means for inverting the numerical value vias of both input signals and performing multiplication when both are negative. (6) The output means includes a first addition means that adds 1 to all digits of the output signal of the multiplication means when one of the two input signals is negative and the other is positive; 2. The method according to claim 4, further comprising: first inverting means for inverting the numerical bits of the output of the means; and means for adding a sign bit to the output of the first inverting means. Complement Multiplier〇(6) Output means is 1.2 When both input signals of numbers are negative, a second inverting means for inverting all digits of the output signal of the multiplication means, and this second inverting means 6. The two's complement multiplier according to claim 4 or claim 5, further comprising a second addition means for adding 1 to the least significant digit of the output.