JPH05266060A - Matrix arithmetic circuit - Google Patents

Abstract

PURPOSE:To execute matrix arithmetic in arbitrary arithmetic and output scan directions without enlarging hardware scale. CONSTITUTION:Reading ate for either input matrix data stored in a data memory 1 and similar input matrix data stored in a coefficient memory 2 is made n-times as high as a serial output, read speed for the other data is made equal, therefore, the matrix arithmetic is executed by one multiplier, and the output matrix data of this arithmetic result are serially outputted. Then, this circuit is provided with an address generating circuit 3 to generate a data memory address and a coefficient memory address by selecting whichever the input matrix data or coefficient matrix data makes the reading rate n-times or make it equal and selecting whether the order of addresses is made horizontal or vertical to the matrix corresponding to an arithmetic direction instruction showing whether the coefficient matrix data are multiplied from the right or left of the input matrix data and an output scan direction instruction showing whether data are outputted by horizontal scan or vertical scan.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix operation circuit, and more particularly to a matrix operation circuit for performing an operation for multiplying two matrix data.

Matrix operations are one of the most widely used operations in digital signal processing devices and the like. Although various circuits can be considered for realizing such a matrix operation, it is desirable that the number of multipliers, which increases the scale of hardware, is small.

[0003]

2. Description of the Related Art An example of such matrix calculation is shown in FIG.
Shown, here a 2x2 matrix is taken as an example for simplicity
To explain. Input digital represented by matrix X
A digit represented by a transform coefficient matrix C for data
Output data matrix transformed by multiplying
Y is obtained. Note that each element of the matrix x_11,x_12,x_{twenty one,}x
_{twenty two,}c_11,c_12,c_{twenty one,}c_{twenty two,}y_11,y_12,y_{twenty one,}y_{twenty two}
One for each (represented by, for example, 8 bits)
Represents the digital data of.

Although there are several possible circuits for implementing this matrix operation, an example of a circuit that requires a small number of large-scale multipliers as hardware is shown in FIG. Matrix operation circuit 10
A data memory 2 is provided outside of the matrix memory 10 for storing input matrix data (hereinafter, may be simply referred to as data), and a coefficient memory 2 is provided inside the matrix operation circuit 10 (hereinafter, may be simply referred to as coefficient). There is an address generator for generating and giving respective addresses to the data memory 1 and the coefficient memory 2, and 11 is a data memory 1 and a coefficient memory 2.
, 13 are multipliers for multiplying the respective data, and adders 16 and 1 are for adding the multiplication result of the multiplier 11 and the output values of the registers 14 and 15 holding the values at the previous operation.
Reference numeral 7 is a register for holding the output values of the registers 14 and 15, respectively, and reference numeral 18 is a selector for serially outputting one of the output values held in the registers 16 and 17.

FIG. 11 shows an operation time chart of the matrix operation circuit 10 as described above. By inputting a predetermined address from the address generator 21 to the memory 1, the input data X is x ₁₁ → x as shown in the figure. ₁₂ → x ₂₁ → x
Reads serially in the order of ₂₂ and simultaneously generates address
By giving a predetermined address from 2 to the internal memory 2, the coefficient data C is c ₁₁ → c ₁₂ → c ₂₁ → as shown in the figure.
Reading is performed at twice the speed in the order of c ₂₂ .

The output data of the memories 1 and 2 are multiplied by the multiplier 11 in accordance with the timing when the input data X changes, and the adder 12 and the register 14 are connected.
The data shown in the figure is output from the register 16 at a timing corresponding to two pieces of input data by way of
Further, at the same time, the data as shown in the drawing is output from the register 17 at the timing of two pieces of input data and at the timing delayed from the register 16 by one timing of the coefficient data by passing through the adder 13 and the register 15. To be done.

The output data of the registers 16 and 17 are alternately selected by the selector 18 at the timing of the input data, so that the data y ₁₁ (x ₁₁ c ₁₁ + x ₁₂ c ₂₁ ) _, y shown in FIG. ₁₂ (x ₁₁ c ₁₂ + x ₁₂ c
₂₂ ) _, y ₂₁ (x ₂₁ c ₁₁ + x ₂₂ c ₂₁ ) _, y ₂₂ (x ₂₁ c ₁₂ +
x ₂₂ c ₂₂ ) is obtained.

In this way, by operating the processing speed of the coefficient data C at twice the processing speed of the input data X, the matrix operation is realized by one multiplier.

[0009]

The above-mentioned conventional example has the following problems. Since the address generation is fixed, there is no degree of freedom in the calculation direction of whether to multiply the input data from the right or left of the coefficient data, and when performing the multiplication from the opposite direction with the same address generation, the input data memory The data arrangement and the data arrangement of the internal coefficient memory must be changed in advance in the form of a transposed matrix. Due to the internal hardware configuration, the order of scans for outputting input data is limited.
Specifically, when the input data X is multiplied from the coefficient data C from the left as shown in FIG. 12 (a), the input data X must be output in a horizontal scan. When the coefficient data C is multiplied by X from the right, the matrix calculation output is limited to the vertical scan as shown in the figure. If the scan order of the subsequent data processing is different from this, a buffer for scan conversion must be provided externally, which increases the hardware scale.

Therefore, the present invention executes a matrix operation of the input matrix data stored in the data memory and the coefficient matrix data stored in the coefficient memory and processed at a speed twice as fast as the speed of the input matrix data. In the matrix operation circuit that serially outputs the output matrix data of the operation result,
It is an object of the present invention to be able to execute a matrix operation in an arbitrary operation direction and an output scan direction without increasing the hardware scale.

[0011]

FIG. 1 shows the principle of a matrix operation circuit according to the present invention for solving the above problems. Whether the coefficient matrix data C is multiplied from the right of the input matrix data X or not. The processing speed of the coefficient matrix data C with respect to the input matrix data X is doubled according to the calculation direction instruction indicating whether to multiply from the left and the output scan direction instruction indicating whether to output in the horizontal scan or the vertical scan. Address for generating read addresses for the data memory 1 and the coefficient memory 2 by selecting whether to make the address horizontal or vertical in the matrix. The generation circuit 3 is provided.

[0012]

In the present invention shown in FIG. 1, the input matrix data X
When the address generating circuit 3 is instructed of the calculation direction indicating whether the coefficient matrix data C is multiplied from the right side or the left side and the output scan direction indicating whether to output in the horizontal scan or the vertical scan, Whether to double the processing speed of the coefficient matrix data C with respect to the input matrix data X
Select (decide) whether to set to / 2.

As described with reference to FIG. 10, this is 1 in the case of horizontal output scan with data X × coefficient C.
Since the processing speed of the coefficient matrix data C must be set to twice the processing speed of the input matrix data X in order to execute the matrix operation by one multiplier, the address generator circuit 3 operates in the direction of operation as described above. In order to change the output scan direction and create the four patterns shown in FIGS. 2 (a) and 2 (b), it is necessary to double or half the processing speed of the coefficient matrix data C and the input matrix data X. Because there is.

Further, in the address generation circuit 3, in order to generate the respective read addresses for the data memory 1 and the coefficient memory 2 together with the processing speed as described above, the order of the addresses is shown in FIG. As shown in b), select whether to output the matrix horizontally or vertically and output it.

In this way, it becomes possible to execute the matrix operation on a small hardware scale without preparing various data and coefficients according to the operation direction and the output scan direction.

[0016]

FIG. 3 shows an embodiment in which the address generating circuit 3 shown in FIG. 1 is incorporated in a matrix operation circuit 10 having one multiplier as shown in FIG. Three specific examples are shown in FIG.

In FIG. 4, reference numeral 31 denotes an address generator, which is the input matrix data X of 2 × 2 size as shown in FIG.
And a counter that generates a 2-bit output (0, 1, 2, 3) for specifying each element of the coefficient matrix data C, and 32 is a counter that also generates a 1-bit output (0, 1) as an address generator. Yes, one bit on the LSB side of the 2-bit output of the counter 31 is added to the MSB side of the 1-bit output from the counter 32 to form a 2-bit output. The reason why the counters 31 and 32 are 2 bits and 1 bit in this way is to reduce the number of bits of the counter 32, and the counter 32 also has a 2 × 2 size of input matrix data X and coefficient matrix data C. It is also possible to use a 2-bit one for identifying the element.

Further, 33 is a switch for receiving 2-bit output of each of the counters 31 and 32 and selecting whether to pass the signal as it is (hereinafter referred to as “through”) or to intersect (hereinafter referred to as “cross”), and 34 and 35 are switches 33. Each output of (2
Bit) to select whether to pass the 2-bit signal through or cross it and apply it to the data memory 1 and the coefficient memory 2 shown in FIG. 3, respectively, and 36 are switches 33 to 33. 35 is a control signal generation unit that generates a control signal for controlling the control unit 35 according to the instructions regarding the calculation direction and the output scan direction.

5 to 8 are operation time charts of the matrix operation circuit 10 when the address generation circuit 3 is used, which will be described below in order.

(1) Vertical output scan with data × coefficient
(Refer to FIG. 5): In this case, the coefficient is located on the left side of the data, which corresponds to the example of FIG. 2 (a). First, the processing speed of the coefficient data C and the processing speed of the input data X are Since the relationship of 10 is also double or 1/2 as described above, the count speed of the counter 32 is set to twice the count speed of the counter 31 as illustrated. Note that this relationship is the same in the examples of FIGS.

As described above, the 2-bit output of the counter 31 is directly given to the upper input terminal of the switch 33 in the order of binary count values "0", "1", "2", "3". From the counter 32 side, 1 bit from the counter 32 becomes the LSB, and 1 on the LSB side of the counter 31.
Switch 33 with 2 bits as MSB.
The count value "0", "1",
"2" and "3" are given in this order at double speed.

Since the vertical output scan is instructed in the data × coefficient calculation direction as described above, the control signal given from the control signal generating unit 36 to the switch 33 is as shown in Table 1 below.

[0023]

[Table 1]

That is, the switch 33 is controlled by the control signal generator 36 so as to be crossed, so that the 2-bit output from the counter 31 side is output to the switch 35 and the 2-bit output from the counter 32 side as shown in FIG. Are switched to the switch 34 respectively and the count value is "0",
“1”, “2”, and “3” are sent in this order.

These switches 34 and 35 are also shown in Table 1 above.
According to the control signal generator 36, the two switches 34 and 35 pass the 2-bit signal in a form in which the MSB side and the LSB side are interchanged (crossed), as shown in FIG. As shown, the data addresses are in the order of binary values "0", "2", "1", "3",
Coefficient address is 1/2 speed and binary value "0",
The order is "2", "1", "3".

By inputting such a data address from the address generating circuit 3 to the memory 1 (see FIG. 3), the input data X is in the order of x ₁₁ → x ₂₁ → x ₁₂ → x ₂₂ (vertical scan) as shown in the figure. Serially, and at the same time, by giving the coefficient address to the memory 2 (see FIG. 3), the coefficient data C is input in the order of c ₁₁ → c ₂₁ → c ₁₂ → c ₂₂ (vertical scan) as shown in the figure. Read at 1/2 speed.

The subsequent processing operation will be described with reference to FIG.
It is the same as that shown in FIG.
As shown in y₁₁(X₁₁c₁₁+ X₁₂c_{twenty one})_,y_{twenty one}(X
_{twenty one}c ₁₁+ X_{twenty two}c_{twenty one})_,y₁₂(X₁₁c₁₂+ X₁₂c_{twenty two})_,y
_{twenty two}(X_{twenty one}c₁₂+ X_{twenty two}c_{twenty two}) Are serially output
It will be.

(2) Horizontal output scan with coefficient × data
(See FIG. 6): In this case, the coefficient comes to the left side of the data, which corresponds to the example of FIG. 2 (b). According to Table 1 above, the switch 33 is crossed and the switches 34 and 35 are controlled to be through. As shown in the figure, the data address and the coefficient address are in the order of “0”, “1”, “2”, “3”, and the speed of the data address is double the speed of the coefficient address and output. Will be done.

By inputting such a data address from the address generation circuit 3 to the memory 1, the input data X is serially read out in the order of x ₁₁ → x ₁₂ → x ₂₁ → x ₂₂ (horizontal scan) as shown in the drawing, At the same time, by giving a coefficient address to the memory 2, the coefficient data C is changed to c as shown in the figure.
₁₁ → c ₁₂ → c ₂₁ → c ₂₂ are read in this order (horizontal scan) at a speed half that of the input data X.

The subsequent processing operation will be described with reference to FIG.
It is the same as that shown in FIG.
As shown in z₁₁(X₁₁c₁₁+ X_{twenty one}c₁₂)_,z₁₂(X
₁₂c ₁₁+ X_{twenty two}c₁₂)_,z_{twenty one}(X₁₁c_{twenty one}+ X_{twenty one}c_{twenty two})_,z
_{twenty two}(X₁₂c_{twenty one}+ X_{twenty two}c_{twenty two}) Are serially output
It will be.

(3) Vertical output scan with coefficient × data
(Refer to FIG. 7): In this case, the coefficient comes to the left side of the data, which also corresponds to the example of FIG. 2 (b). According to Table 1 above, the switch 33 becomes through and the switches 34 and 35 are controlled to cross. As shown in the figure, both the data address and the coefficient address are “0”, “2”, “1”,
The order is "3", and the speed of the data address is 1/2 of the speed of the coefficient address, and the data is output.

By inputting such a data address from the address generating circuit 3 to the memory 1, the input data X is serially read out in the order of x ₁₁ → x ₂₁ → x ₁₂ → x ₂₂ (vertical scan) as shown in the drawing. At the same time, by giving a coefficient address to the memory 2, the coefficient data C is changed to c as shown in the figure.
Reading is performed at a speed twice as fast as the input data X in the order of ₁₁ → c ₂₁ → c ₁₂ → c ₂₂ (vertical scan).

The subsequent processing operation will be described with reference to FIG.
It is the same as that shown in FIG.
As shown in z₁₁(X₁₁c₁₁+ X_{twenty one}c₁₂)_,z_{twenty one}(X
₁₁c _{twenty one}+ X_{twenty one}c_{twenty two})_,z₁₂(X₁₂c₁₁+ X_{twenty two}c₁₂)_,z
_{twenty two}(X₁₂c_{twenty one}+ X_{twenty two}c_{twenty two}) Are serially output
It will be.

(4) Horizontal output scan with data × coefficient
(Refer to FIG. 8): In this case, the same as the conventional example of FIG. 10, the coefficient comes to the right side of the data, so it corresponds to the example of FIG. 2 (a). 34 and 35 are also controlled to be through, and as shown in the figure, both the data address and the coefficient address are in the order of “0”, “1”, “2”, “3”, and the speed of the data address is the coefficient address. It will be output at half the speed.

By inputting such a data address from the address generating circuit 3 to the memory 1, the input data X is serially read out in the order of x ₁₁ → x ₁₂ → x ₂₁ → x ₂₂ (horizontal scan) as shown in the drawing. At the same time, by giving a coefficient address to the memory 2, the coefficient data C is changed to c as shown in the figure.
₁₁ → c ₁₂ → c ₂₁ → c ₂₂ (horizontal scan) is read at twice the speed of the input data X.

Finally, as shown in FIG.
As shown in y₁₁(X₁₁c₁₁+ X ₁₂c_{twenty one})_,y₁₂(X
₁₁c₁₂+ X₁₂c_{twenty two})_,y_{twenty one}(X_{twenty one}c₁₁+ X_{twenty two}c_{twenty one})_,y
_{twenty two}(X_{twenty one}c₁₂+ X_{twenty two}c_{twenty two}) Are serially output
It will be.

Although a matrix operation circuit in a matrix of size 2 × 2 is taken as an example for explanation here, the present invention can be applied to a matrix operation of an arbitrary size in the same way.

[0038]

As described above, according to the matrix operation circuit of the present invention, the operation direction indication indicating whether the coefficient matrix data is multiplied from the right or the left of the input matrix data and whether the coefficient matrix data is output by the horizontal scan or the vertical scan is output. Depending on an output scan direction instruction indicating whether to output by scanning, it is selected whether the processing speed of the coefficient matrix data with respect to the input matrix data is doubled or halved, and the address order is set to the horizontal matrix. Since the address generating circuit for generating the data memory address and the coefficient memory address by selecting the vertical direction or the vertical direction is provided, the matrix arithmetic circuit having a flexible input / output interface by adding a simple circuit. Can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing in principle a matrix operation circuit according to the present invention.

FIG. 2 is a diagram showing an output sequence of a matrix operation circuit according to the present invention.

FIG. 3 is a block diagram showing an embodiment of a matrix operation circuit according to the present invention.

FIG. 4 is a block diagram showing an embodiment of an address generation circuit used in the matrix operation circuit according to the present invention.

FIG. 5 is a time chart showing an operation (No. 1) of the embodiment of the matrix operation circuit according to the present invention.

FIG. 6 is a time chart showing the operation (No. 2) of the embodiment of the matrix operation circuit according to the present invention.

FIG. 7 is a time chart diagram showing an operation (No. 3) of the embodiment of the matrix operation circuit according to the present invention.

FIG. 8 is a time chart diagram showing an operation (No. 4) of the embodiment of the matrix operation circuit according to the present invention.

FIG. 9 is a diagram for generally explaining a matrix calculation.

FIG. 10 is a block diagram showing a conventional example.

FIG. 11 is a time chart showing the operation of the conventional example.

FIG. 12 is a diagram showing an output order of a conventional example.

[Explanation of symbols]

 1 data memory 2 coefficient memory 3 address generation circuit In the figure, the same reference numerals indicate the same or corresponding portions.

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[Procedure amendment]

[Submission date] September 4, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction content]

In this way, by making the reading speed of the coefficient data C from the memory twice as fast as the reading speed of the input data X, the matrix operation is realized by one multiplier.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction content]

Therefore, according to the present invention, the reading speed of either the input matrix data stored in the data memory or the coefficient matrix data stored in the coefficient memory is read at a speed n times the speed of the serial output data. Matrix operation circuit using only the multipliers of the above, and the matrix operation circuit that serially outputs the output matrix data of this operation result, executes the matrix operation in any operation direction and output scan direction without increasing the hardware scale. The purpose is to be able to.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction content]

[0011]

FIG. 1 shows the principle of a matrix operation circuit according to the present invention for solving the above problems. Whether the coefficient matrix data C is multiplied from the right of the input matrix data X or not. The read speed of the coefficient matrix data C relative to the serial output speed of the output matrix data is determined according to the calculation direction instruction indicating whether to multiply from the left and the output scan direction instruction indicating whether to output in the horizontal scan or the vertical scan. Select whether to make n times or the same, and also to make the reading speed of the input matrix data (X) n times or the same, and whether to set the address output order in the horizontal direction of the matrix. It is characterized in that an address generating circuit 3 is provided for selecting whether to make the vertical direction and generating respective read addresses for the data memory 1 and the coefficient memory 2. .

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction content]

[0012]

In the present invention shown in FIG. 1, the input matrix data X
When the address generating circuit 3 is instructed to calculate the calculation direction indicating whether the coefficient matrix data C is multiplied from the right or from the left and the output scan direction indicating whether to output in the horizontal scan or the vertical scan, The reading speed of either the input matrix data X or the coefficient matrix data C is selected (determined) to be n times or the same.

[Procedure Amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction content]

As described with reference to FIG. 10, this is 1 in the case of horizontal output scan with data X × coefficient C.
Since the read speed of the coefficient matrix data C must be set to n times the read speed of the input matrix data X in order to execute the matrix operation by one multiplier, the address generator circuit 3 operates in the direction of operation as described above. In order to change the output scan direction to create the four patterns shown in FIGS. 2 (a) and 2 (b), either the coefficient matrix data C or the input matrix data X must be read n times faster. Is.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction content]

(1) Vertical output scan with data × coefficient
(See FIG. 5): In this case, since the coefficient is located on the left side of the data, it corresponds to the example of FIG. 2 (a). First, the processing speed of the coefficient data C and the processing speed of the input data X are shown in FIG. As described above, since the serial output has a double speed or the same speed, the count speed of the counter 32 is set to double the count speed of the counter 31 as illustrated. Note that this relationship is the same in the examples of FIGS.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Name of item to be corrected] 0025

[Correction method] Change

[Correction content]

These switches 34 and 35 are also shown in Table 1 above.
According to the control signal generator 36, the two switches 34 and 35 pass the 2-bit signal in a form in which the MSB side and the LSB side are interchanged (crossed), as shown in FIG. As shown, the data addresses are in the order of binary values "0", "2", "1", "3",
The coefficient address has the same speed as the serial output, and is in the order of binary values "0", "2", "1", "3".

[Procedure Amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0038

[Correction method] Change

[Correction content]

[0038]

As described above, according to the matrix operation circuit of the present invention, coefficient matrix data of size n × n is multiplied from the right of input matrix data of size n × n or from the left. The read speed of either the input matrix data or the coefficient matrix data is set to the serial output speed according to the calculation direction instruction indicating whether to multiply and the output scan direction instruction indicating whether to output in the horizontal scan or the vertical scan. An address generating circuit for generating a data memory address and a coefficient memory address by selecting n times or the same and selecting whether the address order is the horizontal direction or the vertical direction of the matrix is provided. I configured it, so
A matrix arithmetic circuit having a flexible input / output interface can be realized by adding a simple circuit.

Claims (1)

[Claims] 1. A matrix operation of input matrix data (X) stored in a data memory (1) and coefficient matrix data (C) stored in a coefficient memory (2) is executed, and an output matrix of the operation result is obtained. In a matrix operation circuit for serially outputting data, an operation direction indicating whether to multiply the coefficient matrix data (C) from the right or the left of the input matrix data (X) and output in horizontal scan or vertical scan The processing speed of the coefficient matrix data (C) with respect to the input matrix data (X) is set to 2 according to the output scan direction instruction indicating
By doubling or halving, and by selecting whether the order of the addresses is the horizontal direction or the vertical direction of the matrix, the respective addresses for the data memory (1) and the coefficient memory (2) are selected. Address generation circuit for generating read address
A matrix operation circuit characterized in that (3) is provided.