JPS6231139A - Method for filling insulating isolation groove - Google Patents
Method for filling insulating isolation grooveInfo
- Publication number
- JPS6231139A JPS6231139A JP17143185A JP17143185A JPS6231139A JP S6231139 A JPS6231139 A JP S6231139A JP 17143185 A JP17143185 A JP 17143185A JP 17143185 A JP17143185 A JP 17143185A JP S6231139 A JPS6231139 A JP S6231139A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- groove
- shaped groove
- surface layer
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
半導体集積回路の各素子間を電気的に分離する方法の一
つとしてU溝絶縁分離法が用いられているが、U字型溝
をポリシリコンで埋込むに当たりシリコンの選択成長方
法を用い、工程の簡易化を図った。[Detailed Description of the Invention] [Summary] The U-groove insulation isolation method is used as one of the methods for electrically isolating each element of a semiconductor integrated circuit. We used a selective silicon growth method to simplify the process.
本発明は、U字型絶縁分離溝の埋込み方法の改良方法に
関する。The present invention relates to an improved method for burying U-shaped isolation trenches.
半導体集積回路の製造に当たり、基板上に形成される各
素子を分難する方法として、PN接合分離法、絶縁層分
離法等が用いられている。2. Description of the Related Art In manufacturing semiconductor integrated circuits, methods such as a PN junction separation method and an insulating layer separation method are used to separate each element formed on a substrate.
これらの中で分離特性が良好で、集積度の高い集積回路
の製造にU字型絶縁分離法が多く用いられているが、U
字型溝をポリシリコンで埋込むに当たり基板全面を機械
的にウェット法で研磨することが必要であり、作業性が
悪く改善が要望されている。Among these, the U-shaped insulation isolation method has good isolation characteristics and is often used to manufacture integrated circuits with a high degree of integration.
In order to fill the grooves with polysilicon, it is necessary to mechanically polish the entire surface of the substrate using a wet method, which has poor workability and requires improvement.
従来の技術によるU字型絶縁分離法の工程を図面により
概要を説明する。The steps of a conventional U-shaped insulation separation method will be outlined with reference to drawings.
シリコン基板1 (エピタキシアル成長層等を含む)に
絶縁膜2が積層されRIE法により0字型溝3を形成す
る。絶縁膜はSiO□膜が1層の場合もあるがSiO□
膜とS i 3 N m膜の2層として積層される場合
もある。An insulating film 2 is laminated on a silicon substrate 1 (including an epitaxial growth layer, etc.), and a 0-shaped groove 3 is formed by the RIE method. The insulating film may be a single layer of SiO□ film, but SiO□
In some cases, two layers, a film and a Si 3 N m film, are laminated.
熱酸化によりU字型溝の内面にも酸化膜4を成長させる
。これを第2図(a)に示す。An oxide film 4 is also grown on the inner surface of the U-shaped groove by thermal oxidation. This is shown in FIG. 2(a).
この状態の基板に気相成長法でシリコンを成長させる。Silicon is grown on the substrate in this state by vapor phase growth.
この場合絶縁膜の上ではポリシリコンが成長するので、
全面にポリシリコン層5が成長しU字型溝を埋込む。こ
れを第2図(b)に示す。In this case, polysilicon grows on the insulating film, so
A polysilicon layer 5 is grown over the entire surface and fills the U-shaped groove. This is shown in FIG. 2(b).
次いで、U字型溝内のポリシリコン以外の不要なるポリ
シリコン層を研磨除去し、更に熱酸化工程を経てU字型
絶縁分離溝が完成する。これを第2図(C)に示す。Next, unnecessary polysilicon layers other than the polysilicon in the U-shaped trench are polished away, and a thermal oxidation process is further performed to complete the U-shaped isolation trench. This is shown in FIG. 2(C).
上記に述べた、従来の技術による方法では絶縁膜上に堆
積せるポリシリコン層を機械的な研磨法により平坦化さ
れることである。In the conventional method described above, the polysilicon layer deposited on the insulating film is planarized by mechanical polishing.
研磨に際してはシリコンのエツチング液を使用するので
ウェット・プロセスとなり、工数がかさむのみならず汚
染等の恐れもあり、ウェハー歩留りの低下を来す。Since a silicon etching solution is used during polishing, it is a wet process, which not only increases the number of steps but also poses a risk of contamination, resulting in a decrease in wafer yield.
またシリコンの気相成長の条件によっては、U字型溝領
域に凹部を生じて研磨後の面が平坦化しない場合も見ら
れる。Further, depending on the conditions of silicon vapor phase growth, there are cases in which a recess is formed in the U-shaped groove region and the surface after polishing is not flattened.
上記問題点は、U字型溝を形成せる基板を酸化膜で被覆
し、U字型溝を開口せるレジスト膜を積層した後、U字
型溝の底部の酸化膜の表面にシリコン・リッチなる表面
層を形成し、次いで、該表面層上にシリコンの選択成長
を行ってU字型溝を埋込むことよりなる本発明の方法に
よって解決される。The problem mentioned above is that after the substrate on which the U-shaped groove is formed is coated with an oxide film and the resist film that opens the U-shaped groove is laminated, silicon-rich material is formed on the surface of the oxide film at the bottom of the U-shaped groove. The problem is solved by the method of the invention, which consists of forming a surface layer and then performing selective growth of silicon on the surface layer to fill the U-shaped trench.
上記シリコン・リッチなる表面層の形成法として、U字
型溝の底の酸化膜にシリコンのイオン打込みを行うこと
によって可能であり、また別の方法としてアルゴンのス
パッタ・エッチングを行うことによっても形成すること
が出来る。The above-mentioned silicon-rich surface layer can be formed by implanting silicon ions into the oxide film at the bottom of the U-shaped groove, or alternatively, by sputter etching with argon. You can.
シリコンの気相成長はソースガスと被成長面の表面状態
により著しく影響を受ける。The vapor phase growth of silicon is significantly influenced by the source gas and the surface condition of the growing surface.
上記のU字型溝の底部の絶縁膜をシリコン・リッチとす
ることにより、この領域でのシリコンの成長は他の絶縁
膜上に比して著しく促進されてU字型溝を埋め込むもの
で、それ以外の絶縁膜上にはポリシリコンは成長するこ
とはない。従って研磨の工程を省略することが出来る。By making the insulating film at the bottom of the U-shaped groove silicon-rich, the growth of silicon in this region is significantly promoted compared to other insulating films, filling the U-shaped groove. Polysilicon does not grow on other insulating films. Therefore, the polishing step can be omitted.
本発明は絶縁膜上でのシリコンを選択気相成長法の技術
をU字型溝絶縁分離法に適用するものであり、シリコン
の選択気相成長方法については本発明者の一員である三
重野により別途出願されている。The present invention applies the technique of selective vapor phase growth of silicon on an insulating film to the U-shaped groove insulation isolation method. A separate application has been filed.
本発明の一実施例を第1図f8)〜(C1により詳細説
明する。U字型溝を形成し酸化膜を形成するまでの工程
は特に変わらないので、従来の技術の項において用いた
符号と同一のものは説明を省略する。An embodiment of the present invention will be explained in detail with reference to FIG. Descriptions of items that are the same as those will be omitted.
上記基板を用いてU字型溝の開口部のみを除いてレジス
ト膜6積層する。これを第1図(a)に示す。Using the above substrate, a resist film 6 is laminated except for the opening of the U-shaped groove. This is shown in FIG. 1(a).
次いで、イオン打込み法によりシリコン・イオンを0字
型溝3の底部に照射する。イオン打込みは約30KeV
、 ドーズ量は5×10167CII+2とする。Next, the bottom of the 0-shaped groove 3 is irradiated with silicon ions by an ion implantation method. Ion implantation is approximately 30KeV
, the dose amount is 5×10167 CII+2.
これによりシリコン・リッチなる表面層7が酸化股上に
形成される。これを第1図(b)に示す。This forms a silicon-rich surface layer 7 on the oxidized top. This is shown in FIG. 1(b).
次いで、レジスト膜6を除去した姦、トリクロール・シ
ランを用い、水素還元法でシリコンの気相成長を行う。Next, vapor phase growth of silicon is performed by a hydrogen reduction method using trichlorosilane from which the resist film 6 has been removed.
成長は減圧条件で、温度800℃で行われる。Growth is performed under reduced pressure conditions and at a temperature of 800°C.
S i HC13+ Hz→Si↓+HCI ↑これ
により第1図(C)に示すごとく、0字型溝3はポリシ
リコン8で埋込まれ、その他の基板面にはシリコンは成
長することはない。S i HC13+ Hz→Si↓+HCI ↑Thus, as shown in FIG. 1(C), the 0-shaped trench 3 is filled with polysilicon 8, and silicon does not grow on the other substrate surfaces.
シリコン・リッチなる表面層の形成には、上記に述べた
シリコンのイオン打込み性基外にもアルゴンによるスパ
ッタ・エッチング法も適用可能である。In addition to the above-mentioned silicon ion implantation method, sputter etching using argon can also be applied to form a silicon-rich surface layer.
これはアルゴンのイオンをU字型溝の底部に衝突させて
、酸化膜の表面の酸素原子をはじき出して(スパッタリ
ング)シリコン・リッチなる表面層を形成するものであ
る。This method involves bombarding the bottom of the U-shaped groove with argon ions to expel (sputter) oxygen atoms on the surface of the oxide film to form a silicon-rich surface layer.
第1図(C)以降の工程は、従来の方法と変わることは
ない。The steps after FIG. 1(C) are unchanged from the conventional method.
以上に説明せるごとく本発明の方法を適用することによ
り従来の機械的な研磨工程を省略することが可能となり
、コストの削減とウェハーの歩留り向上に寄与すること
が大きい。As explained above, by applying the method of the present invention, it is possible to omit the conventional mechanical polishing process, which greatly contributes to cost reduction and improvement of wafer yield.
第1図(al〜(e)は本発明にかかわるU字型絶縁分
離溝の埋込方法を説明する工程順断面図、第2図(a)
〜[0)は従来の技術によるU字型絶縁分離溝の埋込方
法を説明する工程順断面図、を示す。
図面において、
1はシリコン基板、
2は絶縁膜、
3はU字型溝、
4は酸化膜、
5.8はポリシリコン層、
6はレジスト膜、
7はシリコン・リッチ表面層、
をそれぞれ示す。
@ 1 図
第2mFIGS. 1(a) to 1(e) are step-by-step cross-sectional views illustrating the method of burying a U-shaped insulation isolation trench according to the present invention, and FIG. 2(a)
-[0] are process-sequential sectional views illustrating a conventional method for burying a U-shaped insulation isolation trench. In the drawings, 1 is a silicon substrate, 2 is an insulating film, 3 is a U-shaped groove, 4 is an oxide film, 5.8 is a polysilicon layer, 6 is a resist film, and 7 is a silicon-rich surface layer. @ 1 Figure 2m
Claims (3)
、該溝を開口せるレジスト膜(6)を積層した後、溝の
底部の酸化膜の表面にシリコン・リッチなる表面層(7
)を形成し、 次いで、該表面層上にシリコンの選択成長を行う工程を
含むことを特徴とする絶縁分離溝の埋込方法。(1) After covering the substrate on which the groove (3) is to be formed with an oxide film (4) and laminating the resist film (6) that opens the groove, a silicon-rich surface is formed on the surface of the oxide film at the bottom of the groove. layer (7
) and then selectively growing silicon on the surface layer.
、シリコンのイオン打込みを行うことを特徴とする特許
請求範囲第(1)項記載の絶縁分離溝の埋込方法。(2) The method for burying an insulation isolation trench according to claim (1), wherein the silicon-rich surface layer is formed by silicon ion implantation.
、アルゴンのスパッタ・エッチングを行うことを特徴と
する特許請求範囲第(1)項記載の絶縁分離溝の埋込方
法。(3) The method for burying an isolation trench according to claim (1), wherein the silicon-rich surface layer is formed by argon sputter etching.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17143185A JPS6231139A (en) | 1985-08-02 | 1985-08-02 | Method for filling insulating isolation groove |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17143185A JPS6231139A (en) | 1985-08-02 | 1985-08-02 | Method for filling insulating isolation groove |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6231139A true JPS6231139A (en) | 1987-02-10 |
Family
ID=15922996
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17143185A Pending JPS6231139A (en) | 1985-08-02 | 1985-08-02 | Method for filling insulating isolation groove |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6231139A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6331472B1 (en) * | 2000-10-11 | 2001-12-18 | Macronix International Co., Ltd. | Method for forming shallow trench isolation |
SG117420A1 (en) * | 2001-11-13 | 2005-12-29 | Chartered Semiconductor Mfg | Preventing plasma induced damage resulting from high density deposition |
-
1985
- 1985-08-02 JP JP17143185A patent/JPS6231139A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6331472B1 (en) * | 2000-10-11 | 2001-12-18 | Macronix International Co., Ltd. | Method for forming shallow trench isolation |
SG117420A1 (en) * | 2001-11-13 | 2005-12-29 | Chartered Semiconductor Mfg | Preventing plasma induced damage resulting from high density deposition |
US7208426B2 (en) | 2001-11-13 | 2007-04-24 | Chartered Semiconductors Manufacturing Limited | Preventing plasma induced damage resulting from high density plasma deposition |
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