JPS6230659B2 - - Google Patents

Info

Publication number
JPS6230659B2
JPS6230659B2 JP57148914A JP14891482A JPS6230659B2 JP S6230659 B2 JPS6230659 B2 JP S6230659B2 JP 57148914 A JP57148914 A JP 57148914A JP 14891482 A JP14891482 A JP 14891482A JP S6230659 B2 JPS6230659 B2 JP S6230659B2
Authority
JP
Japan
Prior art keywords
main memory
bus
memory device
active
address bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57148914A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5957352A (ja
Inventor
Akihiro Sera
Satoshi Osada
Kazuhiko Gokon
Minoru Watanabe
Juji Shibata
Tetsuo Kawamata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57148914A priority Critical patent/JPS5957352A/ja
Publication of JPS5957352A publication Critical patent/JPS5957352A/ja
Publication of JPS6230659B2 publication Critical patent/JPS6230659B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/74—Masking faults in memories by using spares or by reconfiguring using duplex memories, i.e. using dual copies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
JP57148914A 1982-08-27 1982-08-27 診断方式 Granted JPS5957352A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57148914A JPS5957352A (ja) 1982-08-27 1982-08-27 診断方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57148914A JPS5957352A (ja) 1982-08-27 1982-08-27 診断方式

Publications (2)

Publication Number Publication Date
JPS5957352A JPS5957352A (ja) 1984-04-02
JPS6230659B2 true JPS6230659B2 (enExample) 1987-07-03

Family

ID=15463478

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57148914A Granted JPS5957352A (ja) 1982-08-27 1982-08-27 診断方式

Country Status (1)

Country Link
JP (1) JPS5957352A (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0769848B2 (ja) * 1987-02-28 1995-07-31 日本電気株式会社 診断インタフエ−ス切替方式

Also Published As

Publication number Publication date
JPS5957352A (ja) 1984-04-02

Similar Documents

Publication Publication Date Title
EP0330475B1 (en) Configuration control system
US4380798A (en) Semaphore register including ownership bits
JP2886856B2 (ja) 二重化バス接続方式
JPS5914778B2 (ja) デ−タ処理装置
JPS6230659B2 (enExample)
JPH0122653B2 (enExample)
JPH0340417B2 (enExample)
JPS6259825B2 (enExample)
JPS5845116B2 (ja) 二重化記憶装置
JP3012402B2 (ja) 情報処理システム
JPH05307491A (ja) 多重化処理装置の切替方法および装置
JPH04263333A (ja) メモリ二重化方式
JPS638500B2 (enExample)
JPH0827761B2 (ja) 二重化メモリの両系同時書込方法
JPS6041787B2 (ja) 多重プロセツサによるデ−タ処理装置
JPS61117651A (ja) インタ−フエイス装置
JPS6242233A (ja) モジユ−ル構成方式
JPH0139122B2 (enExample)
JPS5855536B2 (ja) コモンメモリ制御回路
KR20000005448U (ko) 프로세서 이중화 시스템
JPH0363098B2 (enExample)
JPS61173365A (ja) デ−タ処理方式
JPH04170834A (ja) データ伝送制御システム
JPH047771A (ja) 複合系システム
JPS6051746B2 (ja) 制御回路の診断方式