JPS6230655B2 - - Google Patents

Info

Publication number
JPS6230655B2
JPS6230655B2 JP57192046A JP19204682A JPS6230655B2 JP S6230655 B2 JPS6230655 B2 JP S6230655B2 JP 57192046 A JP57192046 A JP 57192046A JP 19204682 A JP19204682 A JP 19204682A JP S6230655 B2 JPS6230655 B2 JP S6230655B2
Authority
JP
Japan
Prior art keywords
register
address
bits
bit
extended
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57192046A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5981742A (ja
Inventor
Kazuo Tajiri
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP57192046A priority Critical patent/JPS5981742A/ja
Publication of JPS5981742A publication Critical patent/JPS5981742A/ja
Publication of JPS6230655B2 publication Critical patent/JPS6230655B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/342Extension of operand address space

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP57192046A 1982-11-01 1982-11-01 アドレス拡張方式 Granted JPS5981742A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57192046A JPS5981742A (ja) 1982-11-01 1982-11-01 アドレス拡張方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57192046A JPS5981742A (ja) 1982-11-01 1982-11-01 アドレス拡張方式

Publications (2)

Publication Number Publication Date
JPS5981742A JPS5981742A (ja) 1984-05-11
JPS6230655B2 true JPS6230655B2 (enrdf_load_stackoverflow) 1987-07-03

Family

ID=16284708

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57192046A Granted JPS5981742A (ja) 1982-11-01 1982-11-01 アドレス拡張方式

Country Status (1)

Country Link
JP (1) JPS5981742A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5423013A (en) * 1991-09-04 1995-06-06 International Business Machines Corporation System for addressing a very large memory with real or virtual addresses using address mode registers

Also Published As

Publication number Publication date
JPS5981742A (ja) 1984-05-11

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