JPS62298860A - Data transfer method - Google Patents

Abstract

PURPOSE:To improve the operation of a CPU and the operation efficiency of a main memory part by using the serial port memory of the dual port D-RAM of the main memory part as an input buffer part for data communication. CONSTITUTION:When a command i/F control part 18 transmits a transfer request to the opposite system and receives ACK from the opposite system, a CPU 11 instructs a memory control part 14 to transmit a specific signal. The memory control part 14 transmits the specific signal to the main memory 13 and a data i/F control part 20. When the main memory 13 receiving the signal, a DRAM is placed in READ transfer mode for one cycle. Transfer begins to be performed to the opposite system through a data i/F part 19 one cycle later. When the transmission of data is finished, a signal ACK is received from the opposite system according to a transfer end command and the transmitting operation is finished.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention Industrial Field of Application The present invention relates to a memory and an O P that accesses this memory.
The present invention relates to a data transfer method that makes it possible to efficiently utilize an OPU... that connects a U.

2. Description of the Related Art Conventionally, when sending data stored in a memory from a communication circuit or importing data into a memory, a data transfer system as shown in FIG. 3, for example, has been used. This data transfer system includes an O P IJl that controls each circuit of this system, a main memory 3 and a data iJl that are respectively connected to the CPIJl via a CPU bus 2.
/F control unit 4 and command i/F control unit 5, data i/F unit 6 controlled by data i/P control unit 4, and command i/F unit controlled by command i/F control unit 5. 7. When transmitting using this data transfer system, OPU
1 accesses the main memory 3, from which the stored data is retrieved, and this stored data is sent to the data I/F control unit 4 via the CPU bus 2 (see processing procedure ST1 in FIG. 3), and from there Data was to be transmitted to data i/f 6 (ST2). On the other hand, data reception was performed through the opposite route to that used for transmission.

Note that a local memory 8 may be added to the data i/p control unit 4 in some cases. In this case, after the processing at ST13'' in FIG. 3, the data is temporarily stored in the local memory 8 and S
T3.5T4) After that, the process proceeds to ST2 using DMA (direct memory access), and transmission is performed in such a way as to increase the usage efficiency of the CPU bus 2. Furthermore, reception was performed through a route opposite to that of the above-mentioned transmission.

Problems to be Solved by the Invention Incidentally, in this data transfer method, when data in the main memory 3 is transmitted and received by the data I/F unit 6, the C
The problem is that the CPU bus 2 must be routed through the PU bus 2, and while the transmission and reception is being performed, the CPU bus 2 is occupied or used preferentially, causing the CPU 1 to be put on standby. There was a point.

As a solution to this problem, for example, a data transfer system as shown in FIG. 4 can be considered. This data transfer system connects the main memory 3 and the data I/F control section 4 with the CPU bus 2 and another high-speed data path, and also connects the CPU bus 2 during data transfer between the main memory 3 and the data I/F section 6. 2 is now in use. Therefore, in this case, 1, for example (1!PTJ1) can access peripheral devices other than the main memory 3.

However, even in this data transfer system, it is impossible to access main memory during data transfer, and C
There was a problem in that the PU could not access the main memory and communicate data in real time.

The present invention has been made in view of the above circumstances.

An object of the present invention is to provide a data transfer method that allows a CPU to access the main memory in real time by minimizing the occupation of the CPIJ bus when transmitting and receiving data in the main memory.

Means for Solving the Problems In order to achieve the above object, the present invention connects a main memory section having a randomly accessible RAM port and a serial port accessible via a serial memory to a CPU via a CPU bus. A memory control unit is also provided to control the access mode of the main memory unit.

When a serial port in the main memory section is selected under the control of the working memory control section, this port is used as an input/output buffer for communication. Communication is then performed via the serial port with the RAM port open.

Embodiment FIG. 1 is a block diagram showing a schematic configuration of a data transfer system to which an embodiment of the present invention is applied.

This data transfer system includes an OPU 11 that controls each circuit of this system, a main memory section 13 connected to the CPU 11 via a CPU bus 12, and a main memory section 13 and a CPU bus 12.
A memory control unit 14 that is interposed between the PU bus 12, controls the main memory unit 13 such as setting the access mode of the main memory unit 13, and generates the transmission signals TXCT and TXENA; A signal RA is sent to the control unit 14.
It is equipped with a timing generator 16 that outputs NG, 0ASG, TXOT, KG to control the timing of the memory control unit 14, and a communication control unit 16 interposed between the other party's system. There is.

The main memory section 13 has a RAM port that can be randomly accessed and a RAM port that can be accessed via a serial memory, and constitutes a so-called Puar (2) port dynamic memory (Puar port DRAM).

The communication control unit 16 includes a command i/F unit 17 that sends and receives commands to and from the other party's system, and a command
A command i/F control unit 18 that controls and manages the /F unit 17 and synchronizes with the other system, a data i/F unit 19 that sends and receives data to and from the other system, and a data i/F unit. 19 and outputs sE (serial enable) and 5AS (serial clock) to the main memory 13 during transmission and reception, respectively.
/F control section 2o.

A case in which an embodiment of the present invention is applied to a data transfer system configured as described above will be described with reference to FIG. 2, taking as an example the transmission of data to a partner system.

7 Per-Command I/F When the control unit 18 transmits a transfer request to the other party's system and receives the signal AOK from the other party's system, the CPU 11 instructs the memory controller 14 to transmit a predetermined signal.

At this time, the number of bytes to be transferred and the transfer start address are simultaneously specified in units of n bits (blt). In response to instructions from the CPU 11, the memory control section 14 transmits signals CAB, RAS, and TR10E1ME/WE to the main memory section 13, and also transmits signals TXOLK and TXENA to the data i/F control section 2o. When the main memory unit 13 inputs the word signal, the dual port DRAM of the main memory unit 13 operates in READ transfer mode (a mode in which one row of the specified RAM is latched into the serial memory, see FIG. 2). ). After one cycle of this READ transfer mode has passed, the data I/F
8E and 8AS are output from the control section 2o to the main memory section 13. When the main memory section 13 receives the SR and SAS, it starts transferring data to the other party's system via the data I/F section 19. Note that in response to this data transfer, the data I/F control unit 20 outputs signals OT, K, and BNA.
is generated and sent to the other party's system. When the data transmission is completed, a transfer end command is sent from the command I/F control unit 18, and a signal ACK is received from the other party's system in response to this transfer end command, thereby ending the transmission operation. In this case, as shown in the R, BAD transfer mode in FIG.
The data I/F section 19 occupies one cycle of the main memory section 13 to transfer data of t, and the CPU bus 12 and The processing in the main memory section 13 is not obstructed.

It should be noted that transfer at the time of reception is performed in the same manner as above on a path in the opposite direction to the transmission transfer operation described above.

In this case as well, the CPU bus 12 and the main memory section 1
There are very few restrictions on the use of 3.

As described in detail, the present invention uses the serial port memory of the main memory unit's Puer port 1)-RA, M as an input/output cover sofa for data communication, which improves the operating efficiency of the CPU and the main memory unit. As the speed increases, high-speed communication becomes possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a data transfer system to which an embodiment of the present invention is applied, and FIG. 2 is a time chart showing an embodiment of the present invention applied to the same system.
FIG. 3 is a block diagram showing a schematic configuration of a data transfer system to which an example of a conventional method is applied, and FIG. 4 is a block diagram showing a schematic configuration of a data transfer system to which another conventional method is applied. 11...CPU, 12...CPU bus, 13...
Main memory unit, 14...Memory control unit, 16...Communication control unit, 18...Command I/P control unit, 20...
Data I/F control unit.

Claims (1)

[Claims] A memory controller controls an access mode in a main memory section that is connected to the CPU via a CPU bus and has a randomly accessible RAM port and a serial port that is accessible via a serial memory. Select the serial port of
A data transfer method characterized in that the buffer is used as a communication input/output buffer to transmit and receive data to and from the main memory section.