JPS62298111A - 半導体装置 - Google Patents
半導体装置Info
- Publication number
- JPS62298111A JPS62298111A JP61142344A JP14234486A JPS62298111A JP S62298111 A JPS62298111 A JP S62298111A JP 61142344 A JP61142344 A JP 61142344A JP 14234486 A JP14234486 A JP 14234486A JP S62298111 A JPS62298111 A JP S62298111A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- amount
- layer
- width
- alignment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 239000000758 substrate Substances 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 230000013011 mating Effects 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 10
- 230000008602 contraction Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 235000014121 butter Nutrition 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- 241001300198 Caperonia palustris Species 0.000 description 1
- 235000000384 Veronica chamaedrys Nutrition 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 210000000744 eyelid Anatomy 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61142344A JPS62298111A (ja) | 1986-06-17 | 1986-06-17 | 半導体装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61142344A JPS62298111A (ja) | 1986-06-17 | 1986-06-17 | 半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62298111A true JPS62298111A (ja) | 1987-12-25 |
| JPH0515299B2 JPH0515299B2 (enrdf_load_stackoverflow) | 1993-03-01 |
Family
ID=15313176
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61142344A Granted JPS62298111A (ja) | 1986-06-17 | 1986-06-17 | 半導体装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62298111A (enrdf_load_stackoverflow) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007201499A (ja) * | 2007-04-06 | 2007-08-09 | Denso Corp | 半導体基板およびその製造方法 |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7138936B2 (ja) * | 2018-10-23 | 2022-09-20 | 国立大学法人信州大学 | 油圧装置の制御流量推定用のモデルベーストルックアップテーブルの作成方法、制御流量推定用のモデルベーストルックアップテーブルおよび圧力推定方法 |
-
1986
- 1986-06-17 JP JP61142344A patent/JPS62298111A/ja active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007201499A (ja) * | 2007-04-06 | 2007-08-09 | Denso Corp | 半導体基板およびその製造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0515299B2 (enrdf_load_stackoverflow) | 1993-03-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4516316A (en) | Method of making improved twin wells for CMOS devices by controlling spatial separation | |
| US5171703A (en) | Device and substrate orientation for defect reduction and transistor length and width increase | |
| US4381956A (en) | Self-aligned buried channel fabrication process | |
| US20170345906A1 (en) | Self-Aligned Dual Trench Device | |
| US5300797A (en) | Coplanar twin-well integrated circuit structure | |
| JPH02222161A (ja) | 半導体装置の製造方法 | |
| JPS6081839A (ja) | 半導体装置の製造方法 | |
| EP0211174B1 (en) | Monolithic temperature compensated voltage-reference diode and method for its manufacture | |
| US3997378A (en) | Method of manufacturing a semiconductor device utilizing monocrystalline-polycrystalline growth | |
| JPS62298111A (ja) | 半導体装置 | |
| CN108735795B (zh) | (0001)面外延的六方相SiC晶圆、UMOSFET器件及其制作方法 | |
| KR20190086590A (ko) | 자가-정렬 듀얼 트렌치 소자 | |
| US6537895B1 (en) | Method of forming shallow trench isolation in a silicon wafer | |
| CN112908850A (zh) | 稳压二极管的制备方法 | |
| JPH04171979A (ja) | 半導体装置およびその製造方法 | |
| JPS63173340A (ja) | 半導体装置の製造方法 | |
| JPH0340415A (ja) | アライメントマーク及びアライメントマーク形成方法 | |
| JP3913300B2 (ja) | 半導体集積回路 | |
| US4295267A (en) | Two-mask VJ-FET transistor structure | |
| JPS6253952B2 (enrdf_load_stackoverflow) | ||
| EP0961320A2 (en) | Semiconductor wafer comprising an epitaxial layer and an alignment mark | |
| US4886762A (en) | Monolithic temperature compensated voltage-reference diode and method for its manufacture | |
| US5179030A (en) | Method of fabricating a buried zener diode simultaneously with other semiconductor devices | |
| JPH0414863A (ja) | 半導体装置の抵抗素子形成方法 | |
| US12414345B2 (en) | Manufacturing method of semiconductor device and semiconductor wafer |