JPS62295136A - Floating point arithmetic circuit - Google Patents

Abstract

PURPOSE:To save the quantity of hardware or the consuming power of a floating decimal point arithmetic circuit by carrying out the positioning and the normalization of a mantissa part by one positioning means and performing the difference of an exponent part and the carry/carry down after the normalization by one arithmetic means. CONSTITUTION:The exponent parts of inputs A, B obtain the difference between the exponent parts through an exponent part selection means 5 by the exponent part arithmetic means 1 and selects a larger exponent part. According to the difference, a control means 3 controls the positioning means 2 to set the digit of the mantissa parts. Then, the operation of the mantissa parts is carried out by the arithmetic means 4 and when the result is a normalizing number, an operated exponent part is outputted as it is. When it is not the normalizing number, the control means 3 obtains the quantity of shift for the normalization, controls the exponent part selection means 5 according thereto to apply the larger exponent part and the obtained quantity of normalizing shift to the exponent part arithmetic means 1 to adjust the exponent part of the carry/carry down.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Summary] The present invention provides an arithmetic circuit that performs addition and subtraction of normalized floating point numbers, in which digit alignment and normalization of the mantissa part are performed using one shifter. The circuit is miniaturized by performing the difference in the exponent part and the carry after normalization using a single add/subtract circuit (ALU).

[Industrial application field]

The present invention relates to a floating-point number arithmetic circuit, and particularly to an improvement in an arithmetic circuit that performs addition and subtraction of normalized floating-point numbers.

Floating point operations can automatically determine the position of the decimal point,
The number word can cover a sufficiently wide range of numbers.

Therefore, high fJX accuracy can be maintained and programming is easy (DSP (digital signal processing)
Various attempts have been made to apply this to arithmetic circuits.

[Conventional technology]

The configuration of a conventional floating point 'pl arithmetic circuit is shown in FIG.
EL)-114 and 115 are shifters (SFT), 11
6 is a mantissa addition/subtraction circuit (ALU), 11'7 is a mantissa output register (M A N R), 118 is a normalization shift detection circuit (NSD), 119 and 120 are exponent addition/subtraction circuits (ALU), and 121 is the sign judgment circuit (SN
J).

Here, a floating point number in binary is N-3
-m・2m, where S is a positive or negative sign, m
represents the mantissa representing the magnitude of the number, and e represents the exponent representing the scale. The numeric word in this floating point system is the fourth
As shown in the figure.

In such a conventional floating point arithmetic circuit, addition or subtraction is first commanded in the arithmetic mode, and two floating point numbers are converted into A=S-ml·2'''' and B=S-m2·2'''.
To explain the operation of adding and subtracting floating point numbers A and B as
After finding the difference between l and the exponent e2 of the floating point number B, the shifter 114 adjusts the digits of the mantissa parts m1 and m2 of the floating point numbers A and B to match the larger one in accordance with this difference. In this case, both floating point numbers A and B are input to the selectors 111 and 112, and depending on the signal indicating the magnitude of the exponent part from the exponent part addition/subtraction circuit 119, the larger one is sent to the output of the selector 111, and the smaller one is sent to the output of the selector 111. It is controlled so that the signal is generated at the output of the selector 112.

Then, according to the calculation mode, the sign determination circuit 121 sets the mantissa addition/subtraction circuit 116 to addition or subtraction, and the mantissa addition/subtraction circuit 116 adds and subtracts the mantissa parts m1 and m2.The result of this addition/subtraction is sent to the normalized shift amount detection circuit. A shift amount for normalization is calculated in step 118 , and a shifter 115 normalizes the mantissa operation value from the mantissa addition/subtraction circuit 116 and sends it to the register 117 . Normalization here refers to an operation in which the decimal point is shifted so that the minimum digit above the decimal point in the mantissa does not become 0, and the exponent part is added or subtracted according to the shift amount.

On the other hand, in the exponent addition/subtraction circuit 119, floating point numbers A and B
A signal indicating the larger of exponent parts e1 and el is output to the selector 113 to select el or el. This selected exponent part is output from the normalization shift amount detection circuit 118 in the exponent part addition/subtraction circuit 120.
are added and output the value of the exponent part. Finally, the sign judgment circuit! The code signal from 21 is added and the addition/subtraction results are output.

[Problem that the invention seeks to solve]

In this way, conventional floating-point arithmetic circuits use separate digit shifters for mantissa digit alignment and normalization operations, and use separate digit shifters for exponent part calculations for difference calculations and post-normalization operations. The problem was that separate addition and subtraction circuits were used, making the hardware extremely large.

Therefore, an object of the present invention is to provide a floating-point arithmetic circuit with as small a hardware as possible.

[Means for solving problems]

FIG. 1 shows a principle block diagram of an arithmetic circuit that performs addition and subtraction of normalized floating point numbers according to the present invention. 1 calculates the difference between the exponent parts of floating point numbers A and B, and selects the larger exponent part. exponent calculation means; 2 is digit alignment means for aligning the mantissa parts of floating point numbers A and B;
3 is a control means for controlling the digit adjustment means 2 according to the difference between the exponent parts obtained by the exponent part calculation means 1; 4 is a mantissa calculation means for calculating the mantissa parts whose digits have been adjusted; 5 is a mantissa An exponent that selects the exponent part to be given to the exponent part calculation means 1 according to the normalized shift amount obtained by the control means 3 only when the calculated values of the mantissa parts obtained by the part calculation means 4 are not normalized. part selection means, and digit alignment means 2
is for normalizing the calculated value of the mantissa calculation means 4 according to the normalized shift amount from the control means 3, and the control means 3
Further, when the calculated value of the mantissa calculation means 4 is normalized, the larger exponent part selected by the exponent part calculation means 1 is outputted.

[Operation] In FIG. 1, after the exponent parts of inputs A and B pass through the exponent part selection means 5, the exponent part calculation means 1 calculates the difference between the exponent parts and selects the larger exponent part. The control means 3 controls the digit adjustment means 2 according to the difference between the obtained exponent parts.
is controlled to match the digits of the mantissa parts. The mantissa parts are then calculated by the mantissa calculation means 4. If the result of this mantissa calculation is a normalized number, the calculated mantissa is output as is, and the larger exponent obtained by exponent calculation means 1 is output as is. However, if the result is not a normalized number, The control means 3 determines the shift amount for normalization, controls the exponent part selection means 5 accordingly, and supplies the larger exponent part and the determined normalized shift amount to the exponent part calculation means 1. The exponent part calculation means 1 performs calculations in the same manner as the calculations between exponent parts to adjust the exponent part by carrying up and down by 7 digits, and outputs the calculated value as an exponent part under the control of the control means 3.

〔Example〕

FIG. 2 is a circuit diagram showing an embodiment of the floating point arithmetic circuit of the present invention conceptually shown in FIG. An exponent part addition/subtraction circuit (ALU) 11, a selector (SEL>12) which outputs the larger exponent part under the control of the selector control circuit (SLCN) 32 of the control means 3, and a selector 12.
A register (EXPR) 13 that holds the output of 1. A selector (SEL) inputs each floating point number and outputs the one with the larger absolute value under control by the selector control circuit 32 of the control means 3.
) 21 and a selector (SE
L) 22 and a shifter (SFT) 23 that shifts the output mantissa of this selector 22.
U) When the mantissa calculation value outputted from 41 is not normalized, a zero value is input under the control of the selector control circuit 32 of the control means 3 and sent to the mantissa addition/subtraction circuit 41. is for sending the mantissa computed value to the shifter 23 under the control of the selector control circuit 32 of the control means 3 when the mantissa computed value is not normalized. Control means 3
The selector control circuit 32 controls all the selectors, and in addition to this, the control means 3 includes a normalized shift amount detection circuit ( NSC) 33 and selector control circuit 32 to select the exponent part output of the exponent part addition/subtraction circuit 11 or the normalized shift amount to the shifter 23.
It is composed of a selector (SEL) 31 which is given to The exponent selection means 5 includes a selector (SEL) 5 that inputs the floating point number and the output of the normalized shift amount detection circuit 33.
1.52, one of the selectors outputs a large exponent part under the control of the selector control circuit 32, and the other selector outputs the normalized shift amount. still,
The sign determination circuit 121 is similar to that described in FIG.

Next, addition and subtraction operations in the embodiment of FIG. 2 will be explained using floating point numbers A and B similar to those used in the case of FIG.

Floating point numbers A and B first pass through selectors 51 and 52 and are input to exponent addition/subtraction circuit 11 . The exponent addition/subtraction circuit 11 calculates the difference between the exponent parts e1 and 82 and sends it to the selector 31, and also sends a signal indicating the magnitude relationship between the two to the selector control circuit 32. In response to this, the selector control circuit 32 controls the floating point numbers A and B to pass the one with the larger absolute value (the one with the larger exponent part) through the selector 21 and the smaller one through the selector 22. Also, does the selector control circuit 32 control the selector 31? ■The difference between the exponent parts obtained by the exponent addition/subtraction circuit 11 is sent to the shifter 23, and the mantissa part of the floating point number with the smaller exponent part is converted into the mantissa part of the floating point number with the larger exponent part by the shifter 23. Align the digits. Thereafter, the mantissa addition/subtraction circuit 41 performs addition/subtraction of the mantissa (addition or subtraction is specified by the calculation mode).

If the result of addition/subtraction of the mantissa parts is a normalized number, the selector control circuit 32 that receives this controls the selector 12 and stores the larger of the exponent parts e1 and e2 of the floating point numbers A and B in the register 13. At the same time, the output of the mantissa addition/subtraction circuit 41 is sent to the register 42.

On the other hand, if the result of addition/subtraction of the mantissa part is a non-normalized number, the normalized shift amount detection addition/subtraction 33 detects the shift amount to be normalized and sends it to the selector 31 and selectors 51 and 52. The selector control circuit 32 receives a signal from the normalized shift amount detection circuit 33, controls the selector 31, sends the normalized shift) 1 to the shifter 23, and also sends the normalized shift) 1 to the shifter 23.
1.52 and passes the normalized shift amount through the larger exponent part to the other based on the magnitude relationship of the already obtained exponent parts.

Therefore, the mantissa outputted from the mantissa addition/subtraction circuit 41 passes through the selector 22 under the control of the selector control circuit 32, is normalized by the shifter 23, and is input to the mantissa addition/subtraction circuit 41 again. At this time, under the control of the selector control circuit 32, the selector 21 inputs "000...0" and sends it to the mantissa addition/subtraction circuit, t1. Therefore, the output of the mantissa addition/subtraction circuit 41 is output in a normalized form.

Further, the exponent part addition/subtraction circuit 11 performs exponent part adjustment for carry (or carry down) by inputting the larger exponent part and the shift amount to be normalized. In this case, the selector control circuit 32 controls the selector 12 and sends the output of the exponent addition/subtraction circuit 11 to the register 13.

In this way, one mantissa addition/subtraction circuit performs mantissa calculation and mantissa normalization operation, and one exponent addition/subtraction circuit performs exponent calculation adjustment.

〔Effect of the invention〕

As described above, according to the floating point arithmetic circuit of the present invention, digit alignment and normalization of the mantissa part are performed by one digit alignment means, and the difference in the exponent part and the carry up and down 7 digits after normalization are carried out in one unit. Since the calculation is performed using two calculation means, the amount of hardware can be reduced.
This has the effect of reducing power consumption.

[Brief explanation of the drawing]

Fig. 1 is a principle diagram of a floating point arithmetic circuit according to the present invention, Fig. 2 is a hardware block diagram showing an embodiment of a floating point arithmetic circuit according to the present invention, and Fig. 3 is a conventional floating point arithmetic circuit. FIG. 4 is a block diagram showing the circuit. FIG. 4 is a diagram showing numerical words of floating point numbers. 1 and 2, 1 is an exponent calculation means, 2 is a digit adjustment means, 3 is a control means, 4 is a mantissa calculation means, 5 is an exponent selection means, 11 is an exponent addition/subtraction circuit, 12. 21.22.31.51, 52 are selectors, 13
．． 42 is a register, 23 is a shifter, 32 is a selector control circuit, 33 is a normalized shift amount detection circuit, and 41 is a mantissa addition/subtraction circuit. In the drawings, the same reference numerals indicate the same or corresponding parts. Patent applicant: Fujitsu Ltd. Representative Patent Attorney Mori 1) Hiroshi (one other person) Floating point number input' Figure 1 Figure 3

Claims (5)

[Claims] (1) In an arithmetic circuit that performs addition and subtraction of normalized floating point numbers, exponent part calculation means (1) calculates the difference between exponent parts of the floating point numbers and selects the larger exponent part, and the floating point number digit matching means (2) for digit matching between the mantissa parts; control means (3) for controlling the digit matching means according to the difference between the exponent parts; and calculation for the mantissa parts whose digits have been aligned. a mantissa calculation means (4) for performing the above-mentioned mantissa calculation means (4); and only when the calculation value of the mantissa calculation means (4) is not normalized, the exponent is adjusted according to the normalized shift amount determined by the control means (3). exponent part selection means (5) for selecting an exponent part to be given to part calculation means (1);
) according to the normalized shift amount from the mantissa calculation means (
4) is used to normalize the calculated value, and the control means (
3) A floating point arithmetic circuit which outputs the selected larger exponent part when the calculated value of the mantissa part arithmetic means (4) is normalized. (2) the exponent part calculation means (1) comprises an exponent part addition/subtraction circuit (11) for calculating a difference between the exponent parts of the floating point numbers;
a first selector (12) that is controlled by the control means (3) and outputs the larger exponent;
2) A floating point arithmetic circuit according to claim 1, comprising: a register (13) for holding the output of (2); (3) a second selector (21) into which the digit alignment means (2) inputs each of the floating point numbers and outputs the one with a larger absolute value under the control of the control means (3);
It is composed of a third selector (22) that outputs the smaller absolute value, and a shifter (23) that shifts the output mantissa part of the third selector (22).
21) is when the mantissa calculation value is not normalized,
Under the control of the control means (3), a zero value is input and sent to the mantissa calculation means (4), and the third selector (22) is configured such that the mantissa calculation value is not normalized. 3. The floating point arithmetic circuit according to claim 1, wherein the mantissa operation value is sent to the shifter (23) under the control of the control means (3). (4) The control means (3) includes a selector control circuit (32) that controls the first selector (12) when the mantissa calculation value is a normalized number; a normalized shift amount detection circuit (33) that detects the shift amount to be normalized when the shift amount is not normalized, and the selector control circuit (32).
), the fourth selector (31) selects the exponent output of the exponent addition/subtraction circuit (11) or the normalized shift amount and supplies it to the shifter (23); 4. The floating point arithmetic circuit according to claim 3, wherein the circuit (32) controls the second and third selectors (21) and (22). (5) The exponent part selection means (5) is fifth and sixth selectors (51, 52) that input the floating point number and the output of the normalized shift amount detection circuit (33),
One of the selectors is connected to the selector control circuit (3).
5. The floating point arithmetic circuit according to claim 4, wherein the selector outputs a large exponent part under the control of item 2), and the other selector outputs the normalized shift amount.