JPH0323937B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a digit alignment processing circuit, particularly a digit alignment processing circuit that performs digit alignment for the mantissas of two floating point data, in which the floating point data is expressed in a first representation mode. In both cases, when it is expressed in the second expression mode, just by giving the expression instruction signal,
The present invention relates to a digit alignment processing circuit capable of performing desired digit alignment.

Floating point data, for example, as shown in FIG. 1, is expressed by an exponent part EXP and a mantissa part M, and is further provided with a sign bit SM of the mantissa part M and a sign bit SE of the exponent part EXP. For example, when adding or subtracting two such floating point data, the contents of the exponent part of each data EXP1 and EXP2
Based on this, it is necessary to align the digits of the contents M1 and M2 of the provisional number.

Although such digit alignment is required, there are two types of representation modes for floating point data itself. Conventionally, a digit alignment processing circuit that handles floating point data in the first expression mode, and a digit alignment processing circuit that handles floating point data in the first expression mode, and A separate digit alignment processing circuit was required to handle the floating point data.

Contents of the exponent part In the case of EXP1 (#1 representation method), the exponent value is expressed as a logical value that adds "64" to the actual value, EXP = 16 (2 6 SE + ₇ 〓 ^{i= 2} 2 7-i ・b i-64) The content of the exponent part is EXP2 (#2 representation method)
In this case, the exponent value is expressed as a catch of 2, and is expressed as EXP=16(-2 6·SE+ ₇ 〓 ⁱ⁼² 2 7−i·b i). SE of the exponent in both representation methods
There are differences in the handling of bits. Note that i takes the value of any one of bit positions "1" to "7".

That is, FIGS. 2A and 2B are explanatory diagrams for explaining the representation mode of floating point data, with FIG. 2A explaining the mantissa part and FIG. 2B explaining the exponent part, respectively. As can be seen from FIG. 2A, in the case of the first expression mode (#1 expression method), if the content of the mantissa is () "0, 0...0", the value of the mantissa indicates zero. , () "0, 10...0" indicates the minimum positive absolute value, () "0, 1...1" indicates the maximum positive absolute value, () "1, 0...
0", it does not exist as a mantissa value, and ()
"1, 10...0" indicates the minimum negative absolute value, and () "1, 1...1" indicates the maximum negative absolute value. On the other hand, as can be seen from FIG. 2A, the second expression mode (#2 expression method) is different from each of the first expression modes.

Furthermore, as can be seen from FIG. 2B, in the case of the first expression mode (#1 expression method), the contents of the exponent part are
() "0000000" means 16 ^-64 , ()
"0111111" means 16 ^-1 , () "1000000"
If 16 means ⁰ , if () "1111111"
It means 16 ⁺⁶³ . On the other hand, as can be seen from FIG. 2B, the second expression mode (#2 expression method) is different from that of the first expression mode. For this reason, conventionally, separate digit alignment processing circuits had to be prepared depending on the representation mode of floating point data.

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, it is an object of the present invention to enable a single digit alignment processing circuit to perform digit alignment processing. And for that reason,
The digit alignment processing circuit of the present invention uses the sign of the mantissa as SM, the sum of the numbers in the mantissa as ΣM, the most significant bit of the exponent as SE, and the sum of the numbers in the exponent excluding the most significant bit as ΣE. When defined respectively, the exponent value is EXP=16 (2 6・SE+ ₇ 〓 ⁱ⁼² 2 7−i ・b i−64) and the mantissa value is ^SM・( ₆₃ 〓 ^{i =8} 2 ^7-i・b _i ) and the exponent value is EXP=16 (-2 6・SE+ ₇ 〓 ⁱ⁼² 2 7-i・b i) and the mantissa value Two floating point data (OP1) and (OP2) in one of the expression modes with the second expression mode expressed as mantissa value = (-SM+ ₆₃ 〓 ⁱ⁼⁸ 2 ^7-i・b _i ) is input, calculate the exponent difference based on the contents of the exponent parts of the two data, shift the contents of the mantissa part of one data based on the exponent difference, and align the digits of the two floating point data. In the digit alignment processing circuit, a first addition is performed to calculate the difference between the content of the exponent part (EXP1) of the first floating point data (OP1) and the content of the exponent part (EXP2) of the second floating point data (OP2). a circuit section; and a second addition circuit section that calculates the difference between the contents of the exponent point (EXP2) of the second floating point data (OP2) and the contents of the exponent part (EXP1) of the first floating point data (OP1). and an expression method that is supplied to each of the first addition circuit section and the second addition circuit section to indicate the above expression mode, and causes both of the addition circuit sections to execute processing corresponding to the expression mode. a second signal conversion circuit section that generates an instruction signal and a shift signal corresponding to the content (M1) of the mantissa part of the first floating point data (OP1) in response to the output from the second addition circuit section; , a first signal conversion circuit section that generates a shift signal for the content (M2) of the mantissa part of the second floating point data (OP2) in response to the output from the first addition circuit section; a second align circuit that shifts the content (M2) of the mantissa part of the second floating point data (OP2) in response to a shift signal from the signal conversion circuit section; a first align circuit that shifts the content (M1) of the mantissa part of the first floating point data (OP1) in response to a shift signal; and a first align circuit and a second align circuit, respectively. a data control signal that instructs the operation mode in each of the align circuits; and the expression method instruction signal is supplied as an external instruction signal corresponding to the currently input data; The present invention is characterized in that the processing mode for determining the difference is selected by the representation method instruction signal, and that floating point data having different representation modes can be processed. This will be explained below with reference to the drawings.

Figure 3 shows the configuration of one embodiment of the present invention, and Figure 4 shows the configuration of the third embodiment.
An explanatory diagram explaining the processing of the align circuit corresponding to the DATACONTROL signal shown in the figure.
An explanatory diagram explaining the shift mode by the illustrated OP1 shift signal or OP2 shift signal, FIG.
An embodiment of the configuration of the first adder circuit shown in FIG.
The diagram shows an example configuration of the signal conversion circuit section 7 shown in FIG. 3, FIGS. 8A and 8B show an example configuration of the second align circuit 2 (ALiGN2) shown in FIG. An explanatory diagram illustrating processing by the gate circuit shown in FIGS. 6 to 8 is shown.

In FIG. 3 showing an embodiment of the present invention, reference numeral OP1 in the figure represents first floating point data, OP2 represents second floating point data, and 1 represents a first align circuit which represents first floating point data. 2 is a second align circuit that shifts the mantissa content M2 of the second floating point data OP2; 3 and 4 are output registers; 5 is the first adder circuit section and the first
The contents of the exponent part of the floating point data OP1 from EXP1 to the contents of the exponent part of the second floating point data OP2
6 is a second addition circuit that calculates the difference between EXP2 and calculates the difference between the content EXP2 of the exponent part of the second floating point data OP2 and the content EXP1 of the exponent part of the first floating point data OP1. things to do, 7, 8
are respectively signal conversion circuit parts, "expression instruction" is a representation method instruction signal, "OP1 shift" is a shift instruction signal for the content M1 of the coefficient part, "OP2 shift" is a shift instruction signal for the content M2 of the mantissa part,
DATACONTROL represents a control signal for the align circuits 1 and 2, which is given as a 4-bit signal as will be described later with reference to FIG.

When two floating point data OP1 and OP2 are given, the contents EXP1 and EXP2 of the respective exponent parts are supplied to adder circuits 5 and 6. The adder circuit section 5 calculates EXP1-EXP2, and the adder circuit section 6 calculates EXP2-EXP1. At this time, when the representation method instruction signal is given and the two floating point data OP1 and OP2 are given in the first representation mode (#1 representation method), the above EXP1 and EXP2 are It is calculated as taking a value corresponding to the #1 expression method shown in Figure B. Also two floating point data OP1 and OP2
are respectively given in the second expression mode (#2 expression method), the above EXP1 and EXP2 are given in the second expression mode (#2 expression method).
It is calculated as taking a value corresponding to the #2 expression method shown in Figure B. As mentioned above, there is a difference in the handling of SE bits between the #1 representation method and the #2 representation method, and in order to determine which exponent value is larger in an exponent difference calculation that includes SE bits, both are used. Control is performed as to whether to compare logically or as signed (capture of 2) numerical values.

The outputs of the first and second adder circuits 5 and 6 are
In the case shown in Figure B, it is generally a 7-bit value, but it is converted into a 4-bit signal by signal conversion circuits 7 and 8, and the illustrated OP2 shift signal and OP1 shift signal are supplied to align circuits 1 and 2, respectively. .

Each align circuit 1, 2 has a fourth
A DATACONTROL signal, which will be described later with reference to the figures, is supplied, as well as the content of the mantissa part of the corresponding floating point data and its sign bit.
Then, after the desired shifts have been performed on the contents of the corresponding mantissa parts, the output registers 3 and 4 are
is set to

FIG. 4 shows an explanatory diagram illustrating the processing of the align circuit corresponding to the DATACONTROL signal shown in FIG. 3. The DATACONTROL signal is given as a 4-bit signal, and includes () ALiGN bit () SiGNED bit () UNSiGNED bit () SHORT bit. When the ALiGN bit is applied, it is instructed to perform a shift according to the shift amount corresponding to the OP1 shift signal or OP2 shift signal. SiGNED bits and UNSiGNED
If the bits are "0, 0", it is instructed that no special processing be performed on the contents of the given mantissa. Similarly, in the case of "0, 1", "0...0" is extended to the left end by the shift amount for the contents of the shifted mantissa part. Similarly, “1,
In the case of "0", the content of the sign bit (SM) is extended to the left end by the amount of shift with respect to the content of the shifted mantissa part as "0...0" or "1...1". Additionally, if the SHORT bit is given, floating point data O1 and OP2 will typically be 64
The 32nd bit of the mantissa input to each align circuit 1 and 2 indicates that the data is given in 32 bits. It is instructed to add "00...0" to the 63rd bit. In addition, the mantissa part in the case of the #1 representation method is a sign and a decimal number expressed as a true value (absolute value), and the mantissa value = (-1) ^SM・( ₆₃ 〓 ⁱ⁼⁸ 2 ^7-i・b _i ) The mantissa part in the _case of the ^# 2 representation method is a decimal number in the catch representation of 2, and ^is expressed as _follows . Therefore, by shifting the mantissa to the right (digit alignment), in #1 representation (absolute value), zero is extended to the left end by the shifted amount, and in #2 representation (capture of 2), the zero is extended to the left by the shifted amount. The sign bit (0 or 1) is extended by the amount.

Figure 5 shows the OP1 shift signal shown in Figure 3 or
FIG. 3 is an explanatory diagram illustrating a shift mode using an OP2 shift signal. Then, A EXP1>EXP2, and the difference is the value "15"
If it exceeds , the value "0" is given as the OP1 shift signal, and the value "15" is given as the OP2 shift signal.

B If EXP1>EXP2 and the difference is greater than or equal to the value "1" and less than or equal to the value "15", the value "0" is given as the OP1 shift signal, and the value corresponding to the above difference is given as the OP2 shift signal. is given.

(C) When EXP1=EXP2, the OP1 shift signal and
The value "0" is given to the OP2 shift signal and the OP2 shift signal, respectively.

(D) If EXP1<EXP2 and the difference is greater than or equal to "1" and less than or equal to the value "15", the value corresponding to the above difference is given as the OP1 shift signal, and the value "0" is given as the OP2 shift signal. ' is given.

(E) EXP1 < EXP2, and the difference is the value “15”
If it exceeds , the value "15" is given as the OP1 shift signal, and the value "0" is given as the OP2 shift signal.

Note that if the value "15" is given as the shift signal, the shift amount will be truncated to the maximum value.

FIG. 6 shows an embodiment of the configuration of the first adder circuit section 5 shown in FIG. That is, an adder that performs EXP1-EXP2 operations is described. Originally, the operation performed here applies only the subtraction operation of both exponent parts, so the logic gate that creates the catch of 1 of EXP2 is omitted, and if -i bits are input instead of +i bits (or The subtraction can be accomplished with a conventional adder circuit (the reverse may also be used). Code 9 in the diagram
represents the half-sum generation section/generate signal generation section/propagate signal generation section, and generates the basic term of the adder from bit 1 to bit 7, propagation term P, generate term G, and half-sum term H. It shows.

Reference numeral 10 denotes a group carry generation section, which detects the occurrence of a carry from bit 4 in the adder. Reference numeral 11 represents a maximum shift amount detection section, which shows the logic for detecting an index difference of 15 or more, and indicates that (EXP1-EXP2)>15 as explained in FIG. 5 is detected.

Reference numeral 12 represents a difference value check circuit, which detects an instruction difference constituted together with expression method instruction signals (MODE1, MODE2). In other words, the exponent of OP1 (EXP1) is
If it is equal to or larger than the exponent (EXP2) of OP2, the output of the adder circuit AD1 (number 5 in Figure 3) is generating the correct exponent difference, and conversion 1 (number 7 in Figure 3)
If the exponent (EXP1) of OP1 is small, the output of the adder circuit AD2 (numeral 6 in FIG. 3) outputs the correct difference between the two exponents. Therefore, the output signal of the difference value check circuit 12 is the same as the inhibit signal connected from the adder circuit section 5 to the signal converter circuit section 8 or from the adder circuit section 6 to the signal converter circuit section 7 in FIG.

FIG. 7 shows an embodiment of the configuration of the signal conversion circuit section 7 shown in FIG. That is, AD1 shown in Figure 3,
Between AD2 and ALIGN1, ALIGN2, both addition outputs are converted and four shift signals SA0, SA1,
It outputs SA2 and SA3 and instructs the mantissa shift circuit to shift the amount. Only one of the signal conversion circuit section 7 and the signal conversion circuit section 8 operates at a time. This is the topmost signal in Figure 7 +
It is controlled by OP1OP2 and is the same as the inhibit signal in FIG.

The shift amount signals SA0, SA1, SA2, and SA3 sent to each align circuit 1 and 2 have 32, 16, 8, and 4 as the digit of the shift amount, respectively. Therefore, fixing the shift amount to 15 in Fig. 5 means setting all SA0 to SA3 to '1', and the shift amount at this time is (32 +
16+8+4=60), and all digits of the mantissa are shifted.

A circuit similar to that shown in Fig. 8 is copied for ALIIGN1, and the input signal at that time is supplied from the adder circuit section 6, and conversion is inhibited by the -OPOP2 signal of difference value check circuits 1 and 2 shown in Fig. 6. will be done.

8A and 8B each show an embodiment of the align circuit shown in FIG. 3. FIG. That is, the actual ALIGN1/
This explains the ALIGN2 circuit.

Reference numeral 13 represents a shift amount decoding circuit section, which is a decoding circuit that decodes SA0 to SA3 outputted from the signal conversion circuit section 7. SA2 is decoded together with SA3, SA0 is decoded together with SA1, and PR1 (SH0,
SH4, SH8, SH12) and shift amounts 0, 4,
8. Indicates 12 bits, and SEC(SH0,
SH16, SH32, SH48) are shift amounts 0, 16, respectively.
Indicates 32 or 48 bits.

15 is a circuit related to sign control based on the SIGNED/UNSIGND instruction, and 14 is a circuit that outputs mantissa bits 0 to 7.

16 and 17 in Figure 8B indicate the actual ALIGN circuit, and PR1 BIT00 to 63 are the first stage shift circuits (PR1 SH0, SH4, SH8, SH12)
SEC BIT00 to 63 indicate the second stage shift circuit (-SEC SH0, SH0, SH16, SH32,
SH48) is shown. These circuits are
It is provided for each of ALIGN1 and ALIGN2.

Note that FIG. 9 shows an explanatory diagram for explaining the processing by the gate circuit shown in FIGS. 6 to 8. In the figure, 18 corresponds to inputs A, B, C, and D, and outputs X=.=+ as output X. Further, 19 outputs the following as output X in response to inputs A, B, C, and D: X=(A+B).(+) +(+).(C+D). Further, 20 outputs X=.Y=.Z=(A+B).(C+D) as outputs X, Y, and Z in response to inputs A, B, C, and D, respectively.

As explained above, according to the present invention, regardless of whether the given floating point data OP1 and OP2 take either of the above-mentioned first expression mode or second expression mode, a single digit The alignment processing circuit makes it possible to perform desired digit alignment.

[Brief explanation of drawings]

Figure 1 is an explanatory diagram explaining floating point data.
2A and 2B are explanatory diagrams illustrating the representation mode of floating point data, and FIG. 3 shows the configuration of an embodiment of the present invention.
FIG. 4 is an explanatory diagram explaining the processing of the align circuit corresponding to the DATA CONTROL signal shown in FIG. 3, and FIG.
An explanatory diagram illustrating the shift mode by the OP2 shift signal, FIG. 6 is an embodiment of the configuration of the first addition circuit section shown in FIG. 3, and FIG. 7 is an implementation of the signal conversion circuit section 7 shown in FIG. 3. Example configuration, FIGS. 8A and 8B each show an example configuration of the second align circuit 2 shown in FIG. 3, and FIG. 9 is an explanation explaining the processing by the gate circuit shown in FIGS. 6 to 8. Show the diagram. In the figure, 1 and 2 are align circuits, 3 and 4 are output registers, 5 and 6 are adder circuits,
7 and 8 represent signal conversion circuit sections, respectively.

Claims (1)

[Claims] 1. As a representation of floating point data: The sign of the mantissa part is SM The sum of the numbers in the mantissa part is ΣM The most significant bit of the exponent part is SE The sum of the numbers in the exponent part excluding the most significant bit is ΣE
When defined respectively, the exponent value is EXP=16 (2 6・SE+ ₇ 〓 ⁱ⁼² 2 7−i ・b i−64) and the mantissa value is ^SM・( ₆₃ 〓 ^{i The} first ^expression form _{is expressed} ^as Two floating point data (OP1) and (OP2) in one of the expression modes with the second expression mode expressed as mantissa value = (-SM+ ₆₃ 〓 ⁱ⁼⁸ 2 ^7-i・b _i ) is input, calculate the exponent difference based on the content of the exponent part of the two data, shift the content of the mantissa part of one data based on the exponent difference, and align the digits of the two floating point data. In the digit alignment processing circuit that performs digit alignment, a first circuit that calculates the difference between the content of the exponent part (EXP1) of the first floating point data (OP1) and the content of the exponent part (EXP2) of the second floating point data (OP2) is used. an addition circuit unit; and a second addition circuit that calculates the difference between the contents (EXP1) of the exponent part of the first floating point data (OP1) and the contents (EXP2) of the exponent part of the second floating point data (OP2). and is supplied to the first addition circuit section and the second addition circuit section to instruct the expression mode, and causes the addition circuit sections of both to execute processing corresponding to the expression mode. a representation method instruction signal; and a second signal conversion circuit section that generates a shift signal for the content (M1) of the mantissa part of the first floating point data (OP1) in response to the output from the second addition circuit section; , a first signal conversion circuit section that generates a shift signal for the content (M2) of the mantissa part of the second floating point data (OP2) in response to the output from the first addition circuit section; a second align circuit that shifts the content (M2) of the mantissa part of the second floating point data (OP2) in response to a shift signal from the signal conversion circuit section; a first align circuit that shifts the content (M1) of the mantissa part of the first floating point data (OP1) in response to a shift signal; and a first align circuit and a second align circuit, respectively. a data control signal that instructs the operation mode in each of the align circuits; and the expression method instruction signal is supplied as an external instruction signal corresponding to the currently input data; A digit alignment processing circuit characterized in that the processing mode for determining the difference is selected by an expression method instruction signal, and is capable of processing floating point data having different expression modes.