JPS62291937A - Prober - Google Patents

Prober

Info

Publication number
JPS62291937A
JPS62291937A JP61136532A JP13653286A JPS62291937A JP S62291937 A JPS62291937 A JP S62291937A JP 61136532 A JP61136532 A JP 61136532A JP 13653286 A JP13653286 A JP 13653286A JP S62291937 A JPS62291937 A JP S62291937A
Authority
JP
Japan
Prior art keywords
wafer
chuck
external bias
semiconductor wafer
wafer chuck
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61136532A
Other languages
Japanese (ja)
Inventor
Toshiki Yabu
俊樹 薮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP61136532A priority Critical patent/JPS62291937A/en
Publication of JPS62291937A publication Critical patent/JPS62291937A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To stably and accurately measure a fine current region by using an insulating material for a wafer chuck, forming a conductor only at the contacting surface with a wafer, and mounting a detachable external bias application terminal. CONSTITUTION:Ceramics having 8mm thick is used for a chuck body, and an Au film 10 having 10mum thick is deposited only on the surface contacted with a wafer. A detachable external bias application terminal 8 is provided at the chuck, connected with the Au film to apply the external bias directly to the rear surface of the wafer to be measured. The terminal 8 is removed at the time of measuring in a floating state. Since the film 10 is extremely thinner than the wafer 2, the influence of an electric noise in the environment can be suppressed to an extremely low value to stably and accurately measure a fine current region.

Description

【発明の詳細な説明】 3、発明の詳細な説明 産業上の利用分野 本発明は半導体ウェーハ上に形成された半導体素子の電
気的特性あるいは集積回路の回路特性をウェーハ段階に
て厳密に測定するだめのプローパに関するものである。
[Detailed Description of the Invention] 3. Detailed Description of the Invention Industrial Application Field The present invention precisely measures the electrical characteristics of semiconductor elements or the circuit characteristics of integrated circuits formed on a semiconductor wafer at the wafer stage. It's about bad properties.

従来の技術 従来のプローバのウェーハ・チャックとしては、半導体
ウェーハの裏面に直接バイアスを印加することを可能と
するために、極めて導電性の良好な金属性材料を用いて
いる。例えば、第2図はこの従来の導電性ウェーハチャ
ックを備えたプローバを用いて測定を行なっている状態
の断面図である。
BACKGROUND OF THE INVENTION The wafer chuck of a conventional prober uses a metallic material with extremely good electrical conductivity in order to make it possible to apply a bias directly to the back surface of a semiconductor wafer. For example, FIG. 2 is a cross-sectional view of a state in which a measurement is being performed using a prober equipped with this conventional conductive wafer chuck.

1はグローブ針、2は被測定半導体ウェーハである。1
1は導電性材料を用いたウェーハチャックであり、半導
体ウェーハの裏面に直接バイアスを印加できるように外
部バイアス印加端子8を設けである。また、半導体ウェ
ーハを固定するために、ウェーハチャックに穴をあけて
真空源と接続しである。5は絶縁性台座でウェーハチャ
ック11をX、Yステージ6に対して電気的に絶縁し、
かつ固定するだめのものである。9は測定系10i’j
、貞空ポンプである。
1 is a globe needle, and 2 is a semiconductor wafer to be measured. 1
Reference numeral 1 denotes a wafer chuck made of a conductive material, and is provided with an external bias application terminal 8 so that a bias can be directly applied to the back surface of the semiconductor wafer. In addition, in order to fix the semiconductor wafer, a hole is made in the wafer chuck and connected to a vacuum source. 5 is an insulating pedestal that electrically insulates the wafer chuck 11 from the X and Y stages 6;
And it is something that cannot be fixed. 9 is the measurement system 10i'j
, which is a chaiku pump.

発明が解決しようとする問題点 しかしながら従来の導電性ウェーハチャックを而えたプ
ローバでは、半導体ウェーハの裏面に対して外部バイア
スを印加せず、半導体ウェーハ上に形成された電極パッ
ドのみにバイアスを印加する測定を行なうとき、半導体
ウェーハは電気的に不安定なフローティング状態となり
、半導体装置−ハの厚さに対して極めて厚い導電性ウェ
ーハチャックが接触していることにより、ウェーハチャ
ックがまた測定には必要としない外部バイアス印加端子
及び測定系9への接続線が取つけられたままであること
により、外部バイアス印加端子及びその接続線が一種の
アンテナの様な役割をして周囲の電気的雑音による影響
を受けてしまい、半導体ウェーハ上に形成された半導体
素子の電気的特性あるいは集積回路の回路特性に影響を
与え、安定かつ高精度な微少電流領域の測定が行なえな
いという問題点を有していた。
Problems to be Solved by the Invention However, in a conventional prober equipped with a conductive wafer chuck, an external bias is not applied to the back surface of the semiconductor wafer, but a bias is applied only to the electrode pads formed on the semiconductor wafer. When making measurements, the semiconductor wafer is in an electrically unstable floating state, and the wafer chuck is in contact with the extremely thick conductive wafer chuck relative to the thickness of the semiconductor device. By leaving the external bias application terminal and the connection wire to the measurement system 9 attached, the external bias application terminal and its connection wire function as a kind of antenna and are not affected by surrounding electrical noise. This has the problem of affecting the electrical characteristics of semiconductor elements formed on semiconductor wafers or the circuit characteristics of integrated circuits, making it impossible to perform stable and highly accurate measurements in the microcurrent region. .

本発明はかかる点に鑑み、従来通り、半導体ウェーハの
裏面に対して外部から直接バイアスを印加して測定を行
なうことが可能であり、かつ、電気的に極めて不安定な
フローティング状態でも安定かつ高精度な微少電流領域
の測定を行なうことができるプローパを提供することを
目的とする。
In view of these points, the present invention makes it possible to perform measurements by applying a bias directly from the outside to the back surface of a semiconductor wafer, as in the past, and to achieve stable and high performance even in an electrically extremely unstable floating state. The purpose of the present invention is to provide a propper that can perform accurate measurement in the microcurrent region.

問題点を解決するだめの手段 本発明は半導体ウェーハを保持するだめのウェーハチャ
ックに絶縁性材料を用い、かつ半導体ウェーハと接触す
るウェーハチャック表面にのみ金属薄膜の蒸着等にて導
電体を形成したウェーハチャックを備え、かつ、着脱可
能な外部バイアス端子をウェーハチャックの導電性部分
に接続して取付けたプローバである。
Means to Solve the Problem The present invention uses an insulating material for the wafer chuck that holds the semiconductor wafer, and forms a conductor by vapor deposition of a metal thin film only on the surface of the wafer chuck that comes into contact with the semiconductor wafer. This prober is equipped with a wafer chuck and has a removable external bias terminal connected to the conductive part of the wafer chuck.

作用 本発明は前記した構成により、半導体ウェーハ上に形成
された半導体素子の電気的特性あるいは集積回路の回路
特性をウェーハ段階にて、安定かつ高精度な微少電流領
域の測定を行なうことができる。すなわち、絶縁性ウェ
ーハ・チャックの半導体ウェーハと接触する表面に金属
薄膜の蒸着等により導電体を形成しているため、従来通
りに外部バイアス端子を通じて半導体ウェーハの裏面に
対して外部から直接バイアスを印加して」11定するこ
とができ、また金属薄膜は半導体ウェーハに対して厚さ
が十分薄くかつ、着脱可能な外部バイアス印加端子を取
りはずすことにより周囲の電気的雑音の影響をうけるこ
となくフローティング状態においても安定かつ高精度な
微少電流領域の測定を行なうことができる。
Effect of the Invention With the above-described configuration, the present invention enables stable and highly accurate measurement of the electrical characteristics of semiconductor elements or the circuit characteristics of integrated circuits formed on a semiconductor wafer in a microcurrent region at the wafer stage. In other words, since a conductor is formed by vapor deposition of a metal thin film on the surface of the insulating wafer chuck that comes into contact with the semiconductor wafer, a bias can be directly applied from the outside to the back surface of the semiconductor wafer through an external bias terminal as before. Furthermore, the metal thin film is sufficiently thin relative to the semiconductor wafer, and by removing the removable external bias application terminal, it can be placed in a floating state without being affected by surrounding electrical noise. It is also possible to perform stable and highly accurate measurements in the microcurrent region.

実施例 以下、本発明の一実施例について説明する。第1図は本
発明の実施例における絶縁性材料を用い、かつ半導体ウ
エーノ・と接触するウエーノ・・チャック表面にのみ金
属薄膜を蒸着したウエーノ・・チャーツクを有し、かつ
着脱可能な外部バイアス端子を取付けたブローパを用い
て、測定を行なっている状態の断面図である。1はプロ
ーブ針、2は被測定半導体ウェーハである。7はプロー
バ本体である。6は絶縁性台座で、XYステージ6にウ
ェーハ・チャックを固定するだめのものである。3゜4
は本発明の特徴であるところのウエーノ・・チャックで
あり、本実施例ではウエーノ・・チャック本体4に絶縁
材料として厚さ8朋のセラミックを用い、半導体ウエー
ノ・と接触するウエーノ・・チャック表面にのみ金属薄
膜3としてAuを10μm蒸着しである。このとき、着
脱可能な外部バイアス印加端子8をウェーハ・チャック
に設けておき、金属薄膜と接続することによって、半導
体ウェーハの裏面に直接外部バイアスを印加して従来通
りの測定を行なうことができる。また、フローティング
測定時には、外部バイアス端子を取りはずし半導体ウェ
ーハとして例えば6インチSiウェーハでは厚さ約60
0μmであるのに対して、金属薄膜3の厚さを10μm
と極めて薄くしていることにより、周囲からの電気的雑
音による影響を極めて低く抑えることができる。例えば
、本実施例を用いてMOSFETのトランジスタ測定を
行なったとき、サブスレッショルド領域でのリーク電流
特性は数10f人オーダーで測定された。これは測定器
のスペックを満足するものである。
EXAMPLE An example of the present invention will be described below. Figure 1 shows an embodiment of the present invention in which an insulating material is used, the wafer chuck has a thin metal film deposited only on the surface of the wafer chuck that contacts the semiconductor wafer, and a removable external bias terminal. FIG. 3 is a cross-sectional view of a state in which a measurement is being performed using a blower with a blooper attached thereto. 1 is a probe needle, and 2 is a semiconductor wafer to be measured. 7 is the prober body. Reference numeral 6 denotes an insulating pedestal for fixing the wafer chuck to the XY stage 6. 3゜4
is a Ueno chuck which is a feature of the present invention, and in this embodiment, a ceramic with a thickness of 8 mm is used as an insulating material for the Ueno chuck body 4, and the Ueno chuck surface that comes into contact with the semiconductor Ueno is Au was deposited to a thickness of 10 μm as the metal thin film 3 only on the substrate. At this time, by providing a removable external bias application terminal 8 on the wafer chuck and connecting it to the metal thin film, it is possible to directly apply an external bias to the back surface of the semiconductor wafer and perform conventional measurements. In addition, during floating measurement, the external bias terminal is removed and the semiconductor wafer, for example, a 6-inch Si wafer, has a thickness of about 60 mm.
0 μm, whereas the thickness of the metal thin film 3 is 10 μm.
By making it extremely thin, the influence of electrical noise from the surroundings can be kept to an extremely low level. For example, when a MOSFET transistor was measured using this embodiment, the leakage current characteristic in the subthreshold region was measured to be on the order of several 10 f. This satisfies the specifications of the measuring instrument.

以上のように本実施例によれば、絶縁性材料がらなり、
かつ半導体ウェーハと接触する面のみに金属薄膜を蒸着
したウェーハ・チャックを備えかつ着脱可能な外部バイ
アス印加端子を取付けたプローバを構成することにより
、半導体ウェーハ上に形成された半導体素子の電気的特
性あるいは集積回路の回路特性をウェーハ段階にて、フ
ローティング状態においても、安定かつ高精度な微少電
流領域の測定を行なうことができる。
As described above, according to this embodiment, the insulating material is made of
By constructing a prober equipped with a wafer chuck with a metal thin film deposited only on the surface that contacts the semiconductor wafer and a removable external bias application terminal, the electrical characteristics of semiconductor elements formed on the semiconductor wafer can be improved. Alternatively, the circuit characteristics of an integrated circuit can be measured in a stable and highly accurate minute current range at the wafer stage, even in a floating state.

発明の詳細 な説明したように、本発明によれば、ウェーハ・チャッ
クに絶縁性材料を用い、かつ半導体ウェーハと接触する
面にのみ導電体を形成しかつ着脱可能な外部バイアス印
加端子を取付けたプローバを構成することにより、半導
体ウェーハ上に形成された半導体素子の電気的特性ある
いは集積回路の回路特性をウェーハ段階にて厳密な測定
を行うことができ、その実用的効果は太きい。
As described in detail, according to the present invention, an insulating material is used for the wafer chuck, a conductor is formed only on the surface that contacts the semiconductor wafer, and a removable external bias application terminal is attached. By configuring a prober, it is possible to precisely measure the electrical characteristics of a semiconductor element formed on a semiconductor wafer or the circuit characteristics of an integrated circuit at the wafer stage, which has great practical effects.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明における一実施例であるところのウェー
ハ・チャックに絶縁性材料を用い、かつ半導体ウェーハ
と接触する面にのみ金属薄膜を蒸着したウェーハ・チャ
ックを有し、かつ着脱可能な外部バイアス印加端子を取
付けたプローパを用いて測定を行なっている状態を示す
断面図、第2図は従来の導電性ウェーハ・チャックを備
えたグローバを用いて測定を行なっている状態を示す断
面図である。 1・・・・・・プローブ針、2・・・・・・半導体ウェ
ーハ、3・・・・・・金属薄膜、4・・曲絶縁性ウェー
ハ・チャック、5・・・・・・台座、6・・・・・・X
・Yステージ、7・・・・・・プローバ本体、8・・・
・・・着脱可能外部バイアス印加端子、9・・・・・・
測定系、10曲・・真空ポンプ、11・・・出導電性ウ
ェーハ・チャック、12・・・・・・外部バイアス印加
端子。
FIG. 1 shows an embodiment of the present invention in which the wafer chuck is made of an insulating material and has a metal thin film deposited only on the surface that contacts the semiconductor wafer, and has a removable external part. Figure 2 is a cross-sectional view showing a state in which measurements are being made using a propper with a bias application terminal attached; Figure 2 is a cross-sectional view showing a state in which measurements are being made using a glover equipped with a conventional conductive wafer chuck. be. DESCRIPTION OF SYMBOLS 1... Probe needle, 2... Semiconductor wafer, 3... Metal thin film, 4... Curved insulating wafer chuck, 5... Pedestal, 6 ......X
・Y stage, 7...Prober body, 8...
...Removable external bias application terminal, 9...
Measurement system, 10 tracks: vacuum pump, 11: conductive wafer chuck, 12: external bias application terminal.

Claims (2)

【特許請求の範囲】[Claims] (1)半導体ウェーハを保持するためのウェーハチャッ
クとして絶縁性材料を用いかつ半導体ウェーハと接触す
るウェーハチャック表面にのみ導電体を形成してなるプ
ローバ。
(1) A prober in which an insulating material is used as a wafer chuck for holding a semiconductor wafer, and a conductor is formed only on the surface of the wafer chuck that contacts the semiconductor wafer.
(2)着脱可能な外部バイアス印加端子を、ウェーハチ
ャックの導電性部分に接続して取付けた特許請求の範囲
第1項記載のプローバ。
(2) The prober according to claim 1, wherein the detachable external bias application terminal is connected to and attached to the conductive portion of the wafer chuck.
JP61136532A 1986-06-12 1986-06-12 Prober Pending JPS62291937A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61136532A JPS62291937A (en) 1986-06-12 1986-06-12 Prober

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61136532A JPS62291937A (en) 1986-06-12 1986-06-12 Prober

Publications (1)

Publication Number Publication Date
JPS62291937A true JPS62291937A (en) 1987-12-18

Family

ID=15177387

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61136532A Pending JPS62291937A (en) 1986-06-12 1986-06-12 Prober

Country Status (1)

Country Link
JP (1) JPS62291937A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6472079A (en) * 1987-06-24 1989-03-16 Tokyo Electron Ltd Electrical characteristic measuring instrument
JPH01315153A (en) * 1989-02-17 1989-12-20 Tokyo Electron Ltd Wafer-mounting member of prober
WO2001039551A1 (en) * 1999-11-19 2001-05-31 Ibiden Co., Ltd. Ceramic heater
JP2007036165A (en) * 2005-07-22 2007-02-08 Creative Technology:Kk Mounting pedestal for wafer inspecting device
WO2011111834A1 (en) * 2010-03-12 2011-09-15 東京エレクトロン株式会社 Probe apparatus

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6472079A (en) * 1987-06-24 1989-03-16 Tokyo Electron Ltd Electrical characteristic measuring instrument
JPH01315153A (en) * 1989-02-17 1989-12-20 Tokyo Electron Ltd Wafer-mounting member of prober
WO2001039551A1 (en) * 1999-11-19 2001-05-31 Ibiden Co., Ltd. Ceramic heater
JP2007036165A (en) * 2005-07-22 2007-02-08 Creative Technology:Kk Mounting pedestal for wafer inspecting device
WO2011111834A1 (en) * 2010-03-12 2011-09-15 東京エレクトロン株式会社 Probe apparatus
JP2012058225A (en) * 2010-03-12 2012-03-22 Tokyo Electron Ltd Probe apparatus
CN102713650A (en) * 2010-03-12 2012-10-03 东京毅力科创株式会社 Probe apparatus
US9658285B2 (en) 2010-03-12 2017-05-23 Tokyo Electron Limited Probe apparatus

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