JPS62290902A - Digital servo circuit - Google Patents

Abstract

PURPOSE:To compensate the effect of the digit-out data caused by the D/A conversion into the number of bits smaller than the error data, by adding the carry data obtained by integrating the digit-out component smaller than the minimum bit of a D/A converter of the next stage to the digital error data of a prescribed number of bits. CONSTITUTION:An adder 15 adds lower 4 bits of the data DP sampled in the previous time to lower 4 bits of the present data DP. This added output value is added again to an AND gate 16 and processed by an adder 17 and a delay circuit 19. Then this processed value is added again to the adder 15. These actions are repeated. As a result, the digit-out data components are successively integrated to the data DP by the adder 15. Then '1' is added to the lowest bit of the data on upper 4 bits obtained through the gate 16. The data on said upper 4 bits is multiplied by K2=2<-4> by a gain control circuit 11 and then added to an adder 12 to be added with the data DS multiplied by K1 1 and received from a gain control circuit 10.

Description

Detailed Description of the Invention 3. R'P Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a digital servo circuit for a motor used in a VTR or the like.

[Summary of the invention]

The present invention adds carry data obtained by integrating a bit loss smaller than the minimum bit of a subsequent D/A converter to a predetermined number of bits of digital error data. This is designed to compensate for the influence of data with loss of precision that occurs when performing /A conversion.

(Prior Art) In a digital servo circuit that controls a drum motor of a VTR, a speed detection signal is obtained from a frequency generator installed in the motor, and a counter is controlled by this speed detection signal, so that speed errors can be detected from this counter. At the same time, a phase detection signal is obtained by a pulse generator installed in the motor, and another counter is controlled using this phase detection signal (δ and a reference signal such as a vertical synchronization signal). Phase error data is obtained from a counter.The speed error data and phase error data are each subjected to gain control in a gain control circuit according to the operation mode of the VTR, and then converted to D//. The added signals are used to control the speed and phase of the motor to a predetermined value.

The gain control circuit is provided to control the gain, phase, etc. of each error data according to the cue, review, etc. mode of the VTR, that is, according to the set speed of the motor. This gain control circuit is composed of many circuit elements such as resistors, switches, and capacitors corresponding to each mode, and the connections of these circuit elements are switched in conjunction with an external operation for mode switching. Therefore, the above-mentioned conventional digital servo circuit has the disadvantage that it requires many circuit elements and has a complicated configuration.

To solve this problem, a digital servo circuit as shown in FIG. 3 has been used, which has a simplified configuration by controlling the gain of the gain control circuit with a microcomputer.

In FIG. 3, the rotation 4 of the drum motor 1 is detected by a rotation detector 2 provided on the motor l. This rotary generator 2 includes a frequency generator and a pulse generator, and its speed detection head 3 outputs an FG pulse having a period according to the speed as shown in FIG. For example, three cycles are obtained. Further, the phase detection head 4 outputs a PC pulse corresponding to the rotational phase of the motor 1 as shown in FIG.
Obtained at a rate of one per rotation.

The above FG pulse is applied to the control signal generator 5, and the above P
The G pulse is applied to the control signal generator 6.

The control signal generator 5 controls the speed error counter 7, and as shown in FIG. 4, at the rising edge of the FG pulse, the counter 7 is reset and starts counting, and at the falling edge of the FG pulse, the count value NI, N2, N3
It is designed to read. Data consisting of the read count values N + , N zN3-...- is sent to the gain control circuit 10 as speed error data DS.

Further, the control signal generation circuit 6 controls the phase error counter 8 together with the vertical synchronization signal VP applied from the terminal 9.

As shown in FIG. 4, the counter 8 is reset and started counting at the rising edge of the signal P, and at the rising edge of the PC pulse, the count values M, , M,
It is designed to read. This eight-sold count (Direct Ml, M.

-1-- is sent to the gain control circuit 11 as phase error data DP. In addition, counter 7.8
For example, the clock CK of IMIIz is given to the IMIIz clock CK.

The gain control circuit 10 multiplies the speed error data DS by 1 and adds it to the adder 12, and the gain control circuit 11 multiplies the phase error data DP by 2 and adds it to the adder &H12. The added data obtained from this adder 12 is converted into an analog signal by a D/A converter 13. This control i[11 signal is converted into a fffl signal and controls the speed and phase of the motor 1 through the drive amplifier 14.

The gain control circuit 10.11 has a multiplier of 1, N2, and is controlled by the microcomputer 21 in accordance with the operation of an external operation section zO consisting of a mode button or the like of the VTR. In that case,
In general, it is controlled so that >>K, and the control signal for the velocity servo loop is larger than the control signal for the phase servo loop. For example, in the case of normal mode, #1, K, = 2-' are selected.

In general, in a motor servo circuit having a speed servo loop and a phase servo loop, the phase rotation of the speed servo loop is -90'', and the phase rotation of the phase servo loop is -18 degrees.In the servo circuit, the speed detection signal Since control is performed by negative feedback of the phase detection signal, that is, by inverting it to 180°, in the phase servo loop, in addition to the above-mentioned -180° phase rotation, the 180° inversion due to negative feedback is performed. Therefore, the overall size is 36o.

A phase rotation occurs. That is, the input and output to the motor 1 are in phase, causing the loop to oscillate.

In order to prevent such oscillation and obtain stable operation,
>Kg, and when the gain is 1, the speed servo control works more strongly than the phase servo control.

According to the servo circuit of FIG. 3 described above, the gain control circuit 1
0.11 is controlled by the microcomputer 21, the number of circuit elements in the gain control circuits 10 and 11 can be reduced and the configuration can be simplified. Omitting the D/A converter, 1
D/A converters 13 can be used.

Next, the addition processing method in the adder 12 will be explained.

In the adder 12, the above data D S ;fr:K
Multiply the data by 1 ・DS and the above data DP by K
2・DS is added to the data multiplied by g. Data D
S, DP are each 8 bits, K, ζ1, K2-2-4
Then, the calculation of 2.DP for Kl -DS+ is performed as shown in FIG.

K1 ・DS#DS K2 ・DP=2-'・DP 2-4・DP is 4 for −DS as shown in Figure 5.
This is equivalent to shifting only the bits toward the lower bits. Therefore, the added value DS+2-'·DP becomes 12-bit data. This added value is added to the D/A converter 13, and this D/A converter 13 is of the same 8-bit type as the data DS and DP. For this reason, conventionally, the upper 8 bits of the above 12-bit data were treated as valid data, the lower 4 bits were treated as digit-loss data, and this digit-loss data was either truncated or the upper 8 bits and 7 bits of valid data were Rounding up or rounding is performed.

[Problem that the invention seeks to solve]

Conventionally, the above-mentioned operation error data is rounded down, rounded up, or rounded off, so noise is mixed into the control signal finally given to the motor 1, degrading its accuracy, resulting in increased wow and flutter, etc. In particular, the negative effects appeared in the low range. In order to solve this problem, it would be possible to increase the number of D/A converters by 130 bits, but this is difficult due to reasons such as increased cost.

[Means for solving problems]

The present invention includes a signal processing means for processing a signal corresponding to the rotational speed of the motor to obtain error data of a predetermined number of bits, and a D/A that converts the error data into an analog signal and supplies it to the drive circuit of the motor. a digital servo circuit having a converting means, means for detecting a carry-off component of the error data that is less than the minimum bit of the D/A converting means; A means for adding to the error data is provided, and the output data of the adding means is added to the D/A converting means.

[For production]

Since the lower bits, which are the decimated data, are integrated and the carry is added to the error data that is finally used, the decimal data can be corrected.

〔Example〕

FIG. 1 shows a first embodiment of the present invention, in which the present invention is applied to the digital servo circuit shown in FIG.

Note that parts corresponding to those in FIG. 3 are given the same reference numerals.

In FIG. 1, 8-bit phase error data DP obtained from the phase error counter 8 is applied to one input terminal of an AND gate 16 through an adder 15 and also to an adder 17.

The other input terminal of the AND gate 16 is connected to the terminal 18.
A signal with a code of OH, ie rl 1110000J, is added. Therefore, only the upper 4 bits of the 8-bit data DP are taken out from the AND gate 16. The data of the upper 4 bits is added to the adder 17 and the data DP is added to the adder 17.
is subtracted from.

Therefore, only the lower 4 bits of the 8-bit data DP are obtained from the adder 17.

The lower 4 bits of data are (
This corresponds to the attached drop-down list.

Therefore, this digit-loss data is delayed by one sampling period by a delay circuit 19, and then added to the original data DP by an adder 15. The count values Ml, &iZ due to the PC pulse in FIG.
・−・・−・・−・・− is the period obtained. Further, as the delay circuit 19, a memory, an 8-bit shift register, or the like is used.

In the adder 15, the lower 4 of the current data DP
The lower 4 bits of the previously sampled data DP are added to the bits. Therefore, if the addition result in the lower 4 bits has a carry, 1 will be added to the 4th bit from the MSB of the data DP in the addition output value of the addition ff1W15. This addition output value is again applied to the AND gate 16, further processed in the same manner by the adder 17 and the delay circuit 19, and again applied to the adder 15, and this operation is repeated. As a result, in the adder 15, the data DP is successively integrated by the amount of data with a carry loss, and when the lower 4 bits are integrated up to the amount of carry, the 4th bit from the MSB of the data DP- is integrated. That is, the least significant biftoni 1 of the upper 4 bits of data obtained from the AND gate 16 is added. The upper 4 bits of data obtained from this AND gate 16 are multiplied by Kz = 2-' in the gain-controlled X++ circuit 11, then added to the adder I2, and then input from the gain-controlled X++ circuit 10. It is added to the data DS multiplied by 1 as shown in FIG. Therefore, from this adder 12, 8 in FIG.
Bit valid data is obtained. LS of this valid data
In B, the precision of the control signal given to the motor 1 can be improved because the digit loss data has been corrected by the above-mentioned integral operation.

FIG. 2 shows a second embodiment of the present invention, in which the present invention is applied to a digital servo circuit for a general motor. In FIG. 2, parts corresponding to those in FIG. 1 are given the same reference numerals.

In the tree embodiment, when a D/A converter 13 with b bits smaller than C bits is used for input error data D of C bits, the loss of digits of a-b=c bits is corrected. It is.

In FIG. 2, the C bit error data D is added at 23
It is added to one large cuff of the AND gate 16 through I5; A signal S having a code for extracting the upper b (<a) bits of data D is applied from a terminal 18 to the other input terminal of the AND gate 16. The upper b bit data taken out from the AND gate 16 is added to the adder 17 and subtracted from the data D. Therefore, from this adder 17, the lower order c (-a-b) of data D is output.

This data can be obtained by converting this data to x
It is delayed by one sampling interval from the Y extension circuit 19 and then added to the original data D in the adder 15.

As a result, an integral operation similar to that in Figure 1 is performed,
As a result, a correction is made in which 1 is added to the least significant bit of the upper b bit data obtained by 7B from Antgame 1.16. This b-bit data is converted into an analog control signal by a b-bit D/A converter 13 and applied to the motor 1. Since this system '+1[1 signal has been corrected by the loss of digits of the C bit, its accuracy can be improved.

[Effects of the invention] The conventional processing of rounding up, rounding down, rounding off, etc. of data with missing digits eliminates the
It is possible to eliminate the noise and substantially reduce the cumulative error to zero. Therefore, it is possible to obtain excellent control performance such as being able to reduce wow and flank.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a first embodiment of the invention, Fig. 2 is a block diagram showing a second embodiment of the present invention, and Fig. 3 is a block diagram of a conventional digital sensor. Bo times, 1. U4. Figure 4 is the timing chart of Figure 3, and Figure 5 is the block time of Figure 4.
The figure is a diagram illustrating a data addition method. In addition, in the symbols used in the drawings, 8---------1--- Phase error counter 13-- D/A converter 15--Adder 16----------And gate 17
−・−・−1−−−−−−Adder 19−・・・−・
-・-It is a delay circuit.

Claims (1)

[Scope of Claims] Signal processing means for processing a signal corresponding to the rotational speed of the motor to obtain error data of a predetermined number of bits; A digital servo circuit having A conversion means, means for detecting a lost-digit component of the error data that is less than the minimum bit of the D/A converting means; and means for adding the error data to the error data, the digital servo circuit further comprising: means for adding the output data of the adding means to the D/A converting means.