JPS6070836A - Transmitter - Google Patents

Abstract

PURPOSE:To realize simply correction of transmission data and accumulation of digit shift-down bits by accumulating a low-order data other than an high-order significant bit extracted from PCM code original data and adding a carry to transmission bit data when the carry occurs in the significant bit. CONSTITUTION:DPCM data is compressed into 8 bits by a compression extraction circuit 52 and also inputted to the 1st mask logic 54, where the low-order accumulation object bit in response to a scale value is given to an accumulator 55. The value of a logic 54 and a value of a digit shift-down storage register 57 which is accumulation of digit shift-down bits so far are added in the accumulator 55, the carry is masked in the added value and given to the register 57 and also inputted to a carry/overflow detection logic 58, then the occurrence of the carry is checked at the least significant bit location of the transmission data, and when the overflow condition is not established, an encode counter 53 is incremented by 1.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to signal transmission using PCM (pulse code modulation), and particularly to differential PCM or DPCM (cliNe
The present invention relates to a transmitting device suitable for signal transmission using PCM>.

[Technical Background of the Invention] DPCM is known as an efficient PCM encoding method. While normal PCM encoding transmits values obtained by sampling an analog original signal such as an audio signal every moment as digital data, that is, a PCM code, D
PCM transmits only the difference from the previous value, that is, the difference between two samples, as digital data.

FIG. 1 shows an example of a transmission system using DPCM encoding.

In the system shown in FIG. 1, the difference is not taken in the form of analog values, but in the form of digital values. In other words, an analog original signal, for example an audio signal, is A
/D (analog-digital) converter 1 for example 15
The data is converted into bit digital data, and is sent to the difference unit 3 along with the data delayed by one sample in the delay circuit 2 using a register etc., and the difference difference between the two is D
The PCM code is sent to the transmission system in, for example, 16 bits I. Here, the transmission system is simply a ◆communication line with connection lines, conversion, and/or demodulation systems (there are cases where radio waves, light, etc. are used as a medium)
It refers to a so-called transmission system in a broad sense, including a recording/reproducing system (the recording medium serves as a transmission medium, so to speak) in addition to transmission lines such as the above. The difference data (in this case, 16 dots) - transmitted through the transmission system t is given to adder 4, and is added to the previous adder 4 output, which was delayed by 1 sample with a delay of 0, and is summed (integrated). For example, if the data is 15 pits 1~, /A(
The audio signal is applied to a digital to analog converter 6, and an analog audio signal is output.

In DPCM encoding, by transmitting the difference data between two temporally adjacent samples, the transmitted data value becomes smaller on average, or the rarely occurring maximum level data becomes PCM. The data values (levels) are almost the same.

In other words, the characteristics of DPCM are (a) the average level of transmitted data is very small, and (b) the maximum level of one frame of transmitted data is the same as that of ordinary PCM, but the probability of its occurrence is extremely low. At the point.

As a method for effectively transmitting data with a small average level and a low probability of occurrence of high-level signals, normal transmission is performed using a predetermined number of bits that is smaller than the original data, and the data can be expressed using this predetermined number of bits. It is conceivable that a high-level signal exceeding the range is transmitted to effective pin 1 by using only the predetermined number of upper bits as transmission data and truncating the lower bits. In this case, regarding the lower bits that were truncated, if you transmit only the truncated number of bits to the receiving side (and do not send the content of the truncated bits), the receiving side can return to the correct number of digits.
The playback can be performed accurately. In reality, for each data block consisting of a plurality of samples, the maximum level value of the samples in the block is detected, and the data in the block is digit-shifted accordingly, so that the data of the upper predetermined number of bits is used as the main data. The main transmission data and scale information are transmitted as transmission data, and the digit shift information is used as scale information corresponding to the number of cut-off bits. Like this
One piece of scale information is transmitted for each data block consisting of a large number of sample data (this enables efficient information transmission).

A specific example of such a method will be explained in detail. The example described here is for reducing the number of bits of transmission data by the above method in normal PCM transmission, and the configuration is shown in FIG.

In this case, on the transmitting side, the A/D converter 7 converts an input analog signal, for example, an audio signal, into digital preliminary conversion data of sufficient bits, for example, 15 bits, at scheduled time intervals, and then the digital level detecting means 8 converts the input analog signal into digital preliminary conversion data. For example, the maximum level of the scheduled period 1) 1 or a level approximately equivalent to it is detected, and scale information data of, for example, 4 dotsu I. Based on the information data, the output direct conversion data of the A/D converter 7 is digitally level-converted by rolling 1 to 1 to compress the data. For example, the main data of 8 pips 1- is 1q to 1, and this main data and the above scale are The information data are sent to the transmission system by a synthesizing means so that one scale information data corresponds to a large number of main data.

On the other hand, on the receiving side, a separation means 11 separates and extracts the main data and scale information data from the transmission signal received from the transmission system, and a digital level variable control means 12 constituting a data expansion section converts the main data into the scale information data. Based on this, digital level variable control (data expansion) is performed with control characteristics opposite to those on the transmitting side, and the signal is converted into an analog signal by the D/A converter 13 to obtain an output analog signal.

The digital level detection by the digital level detection means 8 is carried out by detecting the number of effective bits in the pre-converted data, that is, the most significant bit position of the effective bits excluding the sign pixel. The digital level variable control in the digital level variable control means 9 is performed by extracting the bit position portion approximately corresponding to the most significant effective bit position from the preliminary conversion data to create main data.

For example, if it is assumed that the shaded part in the 15-bit preliminary conversion data is a valid hit as shown in Figures 3(a) to (C), then in the case of Figure 3(a), the valid bit is in the preliminary conversion data. Of these, 6 hits 1~ are counted, and in order to take 8-bit main data, the lower 8 hits should be used as the main data (maybe. At this time, the positions where the main data is taken are the lower 8 hits, so There are no pins 1 to 1 from the preliminary conversion data.
This corresponds to extracting only the lower 8 bits as is without performing -, and the control level zunawamo scale information at this time becomes the shift 1-firo, . As can be seen from this example, shift ■ has the smallest O hit, so when the effective number of bits is 8 or less, the scale information is uniformly set to
Select "O". In addition, in the case of the same figure (b), the effective number of bits is 9 bins 1~-C, and as is clear from the figure, the main data extraction position is shifted upward (to the left) by 1~1~. The school information becomes 1J, and the main data is 8 Hiso (. This results in error 2. (At this time, it can be considered that the preliminary conversion data is shifted by 1 bit to the lower (right) position relative to the extraction position of the main data 8 hit I-, and the lower 1 bit is discarded.) In this case, the number of effective bits is 15 bits 1~, and the scale information is r7J, and in this case, the lower 7 bits of the preliminary conversion data are ignored.

That is, in this case, the scale information corresponds to the truncated number of pips. In this way, the effective bin 1 which is ignored and discarded when the number of effective bins 1 is large becomes an error, but it is a sufficiently small value with respect to the value of the main data. in this case,
Since the level of scale information is at most 8 x -2 to the 3rd power, the scale information data is expressed in 3 hits 1 to 3. In reality, scale information data corresponds to one piece of data for each large number of preliminary conversion data, so scale information is detected and set in advance by measuring or predicting the maximum value among a large number of corresponding preliminary conversion data. , common scale information (shift amount) for a large number of corresponding preliminary conversion data,
This scale information is detected and updated for each of the large number of preliminary conversion data.

Although it was composed only of the data extracted by bit shifting, this is an analog signal to be handled (a single-polar signal with only one positive or negative signal, and a sign (polarity) bit is not included in the preliminary conversion data), or a sign bit. This is the case when there is no need to transmit even if the pre-converted data contains a bipolar signal such as an input analog signal or an audio signal. I
The bit corresponding to ~l is usually at least ~l
5B (included as the most significant bit (~), and since this is actually an important effective bit, this code is also 19 (~1 bit is 1~ and the above pitch 1~ is shifted by 19))
It is natural for data to be used as main data. In other words, if the main data has 8 hits, the rear [Hira 1~] is taken as the code pitch 1~, so this code Hira 1- and the 7 hits 1- obtained by bit shifting constitute the main data. .

In this case, the digital level variable control means on the receiving side performs a bit shift by the shift amount indicated by the main signal separated from the transmission signal power to obtain reproduced data with the same number of bits as the preliminary conversion data. It turns out.

That is, in the case of the example shown in FIG. 3(a), even if the 8-bit main data is used as is with the lower 8 bits, 15-bit reproduced data equal to any preliminary conversion data is obtained. In the example of the same figure (b), the main data of 8 pits 1~ is similarly
In the example shown in Figure (C), the 8-bit main data is shifted 7 bits to the upper part and 7 bits of additional data is added to the lower part to create 15-bit playback data. is added to create 15-bit playback data. Here, as the data added to the lower order, data uniquely determined in advance, such as O data or average value data, is used. That is, for example, 15-bit preliminary conversion data is
Assume that the data is as shown in Figure (a). When transmitting 8-bit main data based on this (here we are considering the case where the sign bit is not considered), the upper 8 bits of the effective bits are extracted as main data as shown in the figure.
The bottom four hits are discarded. The receiving side receives the main data and shifts the main data by 1 according to the scale information corresponding to the extracted bit position of the 8 bits of main data in the preliminary conversion data to create 15 bits of main data. . At this time, basically, as shown in FIG. 4(b), O data corresponding to the number of shifted bits such as "o o o o" is added. In addition, in order to reduce the error from the original data on average, it is necessary to use a value that approximately corresponds to the average value of the data to be expressed with the corresponding number of bits, for example, the fourth
As shown in Figure <C>, it is effective to use the average value data of "0111" as the "I" addition data. Even if the additional data is data other than these O data or average value data, there is often no practical problem as long as the value is constant for each bit number. In addition, when these data are taken as values other than 0 data, the difference between the value indicated by the lower 1 pip 1- of the original data, that is, the preliminary conversion data, and the above additional data is effectively truncated. Needless to say, it is data.

By the way, although the method shown in the example shown in FIG. 2 can be used when transmitting regular PCM, ie, PCIvl data, as is, it is difficult and undesirable to apply it as is to DPCM.

The main reason for this is that, as shown in Figure 1, DPCM reception requires decoding by accumulating and integrating the received data, and errors caused by truncation on the transmitting side are added up on the receiving side, resulting in large errors. This is because it becomes .

For this reason, even if the average level of transmission data is lowered by DPCM, it has not been possible to reduce the number of bits of actual transmission data.

Nao, example, t[ADPcM (adaptive DP
Is it possible to reduce the number of transmission bits by setting a certain rule in advance between transmission and reception and performing non-linear transmission and reception while lowering the level resolution on the receiving side? etc., were not very accurate and had many problems, such as not only being unable to reproduce them well on the receiving side, but also making the equipment complicated.

On the other hand, the following transmission method can be considered as a transmission method that takes advantage of the effect of reducing the average level of transmitted data by DPCM and enables high-precision transmission with a small number of bits.

That is, in the first process of successively converting PCM code data into DPCM data, the size of the DPCM code data is tested based on the OPCM code data, and a predetermined number of samples are converted into one block. The DPCM is sequentially selected from the bit position with priority given to the upper effective filler 1 so that the maximum data in the data block can be sent.
Scheduled picks 1 to number (
Transmission) A second process of extracting the main data and extracting the position as scale information to the bin 1, and if there is lower-order data that is substantially truncated when the main data is divided by 1, the truncated data is a third process in which the DPCM code data obtained in the first process is added to the subsequent DPCM code data converted by the first process and subjected to the second process in place of the DPCM code data obtained in the first process; As a result of the third processing, a fourth processing sends the main data and scale information obtained in the second processing to the transmission system, and a fourth processing that receives the transmission data transmitted in this fourth processing and Based on the received data, the received main data is converted into DPCM using a bit shift according to the received scale information.
This method performs a fifth process of converting the data into data and decoding and demodulating the DPCM code.

By the way, in such a system, the second
．． Specifically, in the data compression unit which is the main part of the third process, for example, the accumulator is operated as follows.

That is, for example, 16-bit input DPCM code data is added to the lower residual data (i.e., truncated data) that remained in the accumulator without being extracted or transmitted due to the previous extraction of main transmitter data, and the upper valid data of the data after this addition is The bits from P1 to 8 bits, for example, are extracted and transmitted as main data.As a result, the lower residual data remains in the accumulator again.Here, the bit position (upper effective bit position @) from which the main data is extracted is the same data block. The information indicating this bit position is transmitted as a scale value for each block.

Here, a specific example of a transmission/reception system using such a transmission method will be described.

FIG. 5 shows the configuration on the transmitting side, and FIG. 6 shows the configuration on the receiving side.

In FIG. 5, parts similar to those in FIG. 1 are given the same reference numerals and detailed explanation thereof will be omitted.

That is, 1 is an A/D converter that converts an analog original signal input such as an audio signal into digital data, and 2 is an A/D converter.
A sample delay circuit delays the D-converted PCM code data by one sample, and 3 is a subtractor that takes the difference between consecutive 2I numbers of the PCM code data. DPCM code data is obtained. 14 is a block delay circuit configured using a memory, for example, and D P outputted from the differentiator 3
The CN11 code data is delayed by one data block.

15 is a scale detection circuit, which detects the maximum absolute value of sample data in each data block from all the data for one block of DPCM code data output from the subtractor 3, and calculates the maximum value based on the detected value. A scale value is set for each block, and the set scale value is output as data of 4 pits 1, including cases where digit shift is not required.

Note that the above is based on the case where 2''s complement 1~ where the sign t is positive or negative is used, and the scale value is determined by the maximum absolute value of the sample data, but other When a code is used, it may be necessary to detect the scale value using another method suitable for the code.

16 is a compression encoder equipped with an accumulator;
It realizes the function of the data compression section described earlier.

That is, in this case, the compression encoder 16 has a built-in accumulator consisting of, for example, a 16-bit full adder, and operates as follows. In this case, 16-bit DPCM code data given from the block delay circuit 14 is added to an accumulator, and based on the scale value detected and set by the scale detection circuit 15, the 8 bits of the bit position corresponding to the scale value are determined from the contents of the accumulator. Pitsu 1~(
The bit length of the main transmission data) is extracted, and the compressed data in the accumulator is cleared, leaving the missing portion of f (i) in the accumulator when the compressed data is extracted. The digit loss part is applied to the subsequent DP given from the block delay circuit 14.
The compressed data is added to the CM code take, and the compressed data is extracted from the contents of the accumulator which is the result of this addition, as described above. The compressed data extracted in this way is output as transmission main data.

This 8-bit transmission main data and the scale information data of 4 bits 1 to 1 for each block output from the scale detection circuit 15 are supplied to the transmission circuit 17, where both data are converted from parallel data to serial data and time It is multiplexed in sections and sent out serially to the transmission system.

In addition, 18 is a controller 1 to roll sequencer section, which operates based on clock number 8 of a built-in clock generator, and includes the above-mentioned parts A, /D conversion model 1, sample delay circuit 2, and difference generator. 3. In order to operate each part of the block delay recall 14, scale detection circuit 15, compression encoder 16, and transmission circuit 17 in a predetermined manner at a predetermined timing, control signals are given to each part.

The above is the configuration of the transmitting side, and next, the configuration of the receiving side will be explained.

In FIG. 6, 19 is used to separate 8-bit main data and 4-bit scale information data from the transmission signal input from the transmission system, and to convert both data from serial data to parallel data. This is the receiving circuit.

Reference numeral 20 denotes a shift 1 to clock generation unit, which outputs a shift clock corresponding to (the number of pins to be shifted by 1) based on the scale information data inputted from the receiving circuit 19.

21 is a data expansion circuit using, for example, a shift I-register, and in this case, the main data, that is, the compressed DPCM code data (8 hits) inputted from the receiving circuit 19 is processed by the shift clock provided from the shift clock generator 20. 16-bit DPCMPCM with upper bit shift
Receive data. In addition, if the entire operation is made to be performed in 11 times using a 2-S combination code when decompressing this data, the M S B of the main data (compressed DPCM code) is The same polarity code (O or 1 or shift [-) is processed so that it is located consecutively at the top of the register.In other words, in this data decompression circuit 21, the main data of 8 bits 1~ is A bit shift 1- is applied according to the scale information of the i-flock, and the data is converted into D P CM reception data. In this case, 22 is an addition circuit consisting of 16 full adders, Corresponding to the adder 4 in the figure, the DPCMPCM received data output from the 7-total expansion circuit 21 is accumulated and outputted as 15-bit PCM received data. 23 is a data hold register, which is shown at a5 in FIG. The delay circuit 5 inputs the output PC (\4) of the adder circuit 22 of one sample before the output PC (\4 received data, that is, the accumulated four values up to one sample ago +-'i b, and directly outputs it to the adder circuit 22. input and output the latest data decompression circuit (D P
C; M received data) Which addition is used for? 24 is M1
This D/A converter almost corresponds to the D/A converter 6 shown in the figure, and returns the 15-bit PCM reception data held in the data hold register 23 to an analog value. 25 is D/A
This is a low-pass filter that removes unnecessary high frequency components from the output of the converter 24, and an analog signal such as an audio signal is obtained as the output.

Further, 26 is a control sequencer section, which includes the above-mentioned sections, ie, the receiving circuit 19 and the shift clock generating section 20.
, the data expansion circuit 21, the data hold register 23, etc., in order to operate each part at a predetermined timing and in a predetermined manner, control signals are given to each part, and the number of pins is applied when separating the main data of the receiving circuit 19 mentioned above. control.

Next, the operation in the above-described configuration will be explained.

First, on the transmitting side, an analog original signal (for example, an audio signal) is converted into PCM code data (15 bits) by an A/D converter 1, and then delayed by a sample delay circuit 2. The difference between the two is calculated by the subtractor 3 and converted into D P CMi''J@data (16 bits).

This data is given to the scale detection circuit]5, and the maximum difference is calculated from one block of DPCM code data consisting of a predetermined number of samples.Since differences can be positive or negative, to be more precise, the absolute value of the difference is the maximum difference. The scale value (digit shift information) data (4 bits 1~) corresponding to the maximum difference is output from the scale detection circuit 15.

The set scale value output of this scale detection circuit 15 is updated for each block, and becomes scale 1 direct data common to 110 pieces of DPCM code data.

In order to correct this time lag in scale information detection, the DPCM code data delayed by one block in the block delay circuit 14 is compressed in accordance with the sequential scale value of the compression encoder 16-C.

That is, in the compression encoder 16C, the D P CN□=1 code data delayed by one block in the block delay circuit 14 is added to the accumulator, and the data corresponding to the transmission digit of the contents of the A4-J muller, that is, the scale detection circuit 15
The compressed data that is the data of the transmission bit length portion of the digit position corresponding to the scale value set in is extracted, and the lower residual data when this compressed data is extracted is left in the accumulator. Thus, the compression encoder 1
6, the lower residual data generated by compressed data extraction is sequentially added to the subsequent DPCM code data, and compressed data is extracted from the addition result. This compressed data is output from the compression encoder 16 as transmission main data.

This main data and scale information data are sent to the transmission system via the transmission circuit 17. It goes without saying that processing such as time-axis compression of the main data string may be performed as necessary in order to insert scale information data during time-division synthesis in the transmitting circuit 17.

While PCM transmits a value that includes a sign from a reference level, such as the O level, DPCM transmits the difference between samples, so the frequency of the audio signal, etc. is higher than the sampling period by a non-1:3. In some cases, the difference between the vicinity of the positive peak value and the vicinity of the negative peak value may become the DPCM code, and for this reason, the maximum number of DPCM code data is required to be 1 hit 1 or more than the P Cfvl code data. . Therefore, in the above statement, the scale value required to transmit the 16-bit DP CIv1 code data of 16 bits of PC to 1 code data to 15 bits 1 as 8 and 9 bits of main data is a digit shift of 1. -9T including unnecessary cases
'F', which is the scale 1 blue report data of 4 people.

The operation of the receiving side that receives the transmission data sent to the transmission system in this manner will be explained.

The transmission signal given from the transmission system (in this case, consists of 8-bit main data consisting of serialized and time-division multiplexed compressed D P Clvl symbols and 4-bit scale information data for each data block (in this case) K has been completed.

A single receiving circuit to which this transmission signal is applied separates scale information data and main data from the received signal, parallelizes these data, and outputs them respectively. Specifically, for example, for each block from the received signal (
For example, scale information (based on synchronization data added as needed) is first separated and extracted, and the 8-bit data following that scale information data is used as main data to represent the period of that block, that is, the next scale information. are extracted sequentially up to the separation extraction of .

These reception main data and reception scale information data are inputted from the reception circuit 19 to the data expansion circuit 21 and shift 1 to tarok generation section 20, respectively. Shift clock generator 2
A shift clock corresponding to the reception scale information data is output from 0, and this shift clock is applied to the data expansion circuit 21, where the 8-bit reception main data is subjected to a digit shift (bit shift), and the 2-S complement 1 In the case of a code, the high-order bit is filled with the polarity bit and becomes 1
It is converted into 6-bit DPCM reception data. At this time, for example, O
Data is added. This DPCM reception data is given to the adder circuit 22 and added to the output data of the adder circuit 22 one sample before, which is held in the data hold register 23. However, the output data of this adder circuit 22 (
The cumulative (integral) value of PC~1 received data, that is, 15
This is PCM reception data from Pitsu1. This PCM reception data is sequentially D/A converted by a D/A converter 24 via a footer-bold register 23, and unnecessary high frequency components are removed by a low-pass filter 25, and output as an analog signal such as an audio signal. be done.

In this way, the transmitting side can accumulate the truncated part, or the missing part, and transmit the transmission data that is almost reflected in the subsequent transmission data, and the receiving side can receive it and perform effective decoding and demodulation. Therefore, just by transmitting 8-bit main data, the accuracy equivalent to reception at 9 hino) or more can be seen.

However, in this case, the compression encoder 161
As a result of adding the input D P CM code data to the lower residual data in the achiramerator, the transmission pitch of the main data [・
A carry that exceeds the range may occur, resulting in an overflow. The number of effective digits of the input DPC~1 code data is checked in advance in block units before addition in the accumulator, and the difference between the maximum value in the program and the number of digits of the main transmission data is calculated as a scale value (≧O ), so if the above-mentioned overflow occurs, the most important bit among the valid bits will not be transmitted, resulting in a large error.

Referring to FIG. 7, an example will be described in which a 2''s conjoint is used for the DPCM code and the scale value is constant at 6.

Due to the previous main data extraction, the lower residual data remaining in the accumulator is “110” as shown in Figure 7(a).
000'' in a certain state, the DP becomes ``0001111111011101'' as shown in Figure (b).
When CM code data is input, both are added in the accumulator, and '001000' is generated as shown in the same figure (C).
0000001101" is obtained. Since the scale (direct) is 6, the transmission main data (
As shown in the same figure (d), it becomes "10000000".

In this case, in the original data, the most significant sign bit strength (, even though the data is positive, due to the above-mentioned carry, it becomes '1' which indicates negative instead of 'o' which indicates positive, resulting in a big error. .

In order for this kind of inconvenience to occur, (a) there must be positive input data of 1° or 7 or more consecutively, and (b) there must be a difference between the contents of the accumulator (i.e., the previous lower residual data) and the like. Two conditions must be satisfied: the result of addition with the lower digits of the input data must carry beyond the transmission bit position from which the transmission main data is extracted. However, the probability of its occurrence is generally 9 out of 2 in J3.
It is as low as about 10 in -512 times (j, but it is not desirable.

If the scale 1 shift is significantly lower than the immediately preceding data block, an A-ha flow similar to the above iji will occur, and the probability of this (heavy overflow) occurring will be extremely high.

The occurrence of this type of overflow will be described in detail with reference to FIG. In this case, the DI) CM code is still 2'
s conbriment, and the scale) axis changes from 6 to 1.

The lower residual data remaining in the accumulator due to the previous main data extraction is as shown in FIG. 8(a)" 110
000'', the scale value changes from 6 to 1, and at the same time it changes to '000000' as shown in Figure (b).
When human data of 0011011101° is given, both are added in the accumulator. The data ``0000000100001101°'' as shown in Figure (C) is obtained.The scale value is ``1'' (A), so the main transmission data in this case is as shown in Figure (D). 10000110", and the most significant sign p1~ from yi means a negative value due to carry" 1
”.

Generally speaking, the probability of such a case occurring is
It is very high, about 10 times -16 times, and becomes a big problem.

In this way, when an overflow occurs in the transmission main data during signal transmission employing data compression as described above, a large error occurs between the transmitter and the receiver, such as positive data becoming negative data.

As mentioned above, an overflow error occurs when the high-order residual data (contents of the accumulator described above), which is a digit loss part, is added to the original data. ) There are several possible ways to prevent this.

For example, if the overflow shown in above) is to occur, the new original data and the lower residual data in the spacer are added one by one (TJ-c, with the straw addition being reserved). A possible method is to add and accumulate only the missing digits to an accumulator.

In addition, the probability of occurrence of the above-mentioned overflow, especially when the scale value decreases (when the absolute value of the data changes in the decreasing direction)
We focused on the fact that errors with a low probability of occurrence can be corrected using various methods. There are other possible methods.

By the way, as mentioned above, when correcting the transmitted data by adding the new original data and the previous low-order residual data, that is, the cumulative value of the lost bits, even if you try to simply add it using a full adder, etc. , the correction of the above data and the cumulative calculation of the lost bits can be performed simultaneously, and the IC
(Integrated circuit), etc., so it is almost impossible to check for carries from zero-digit pick 1 and overflow of compressed data that may occur due to these carries at the same time as the above addition. be. Therefore, in this case these checks must be performed in advance by external logic. Logic processing to enable these checks regardless of changes in scale values is not suitable for use with microprocessors due to processing speed, etc., so the scale is large and the processing algorithms, control logic, etc. Make it complicated.

For this reason, it is extremely difficult to implement it as an element of a system in terms of both cost and processing speed.

In this sense, even if the probability of overflow occurrence is reduced by using the method described above that limits the change in the scale value in the decreasing direction to "1" (i.e. "-1"), the fundamental It's not a solution.

[Object of the Invention] An object of the present invention is to correct the transmission data and to effectively calculate the cumulative total of lost bits with a simple configuration, including checking for carry from the lost bit 1 and overflow. The object of the present invention is to provide a transmitting device that can be realized.

[Summary of the Invention] The present invention provides a scale detection means for dividing PCM code original data into blocks for each predetermined data group continuous in time series and detecting a level representing each block as a scale value; Therefore, the upper effective bits of a predetermined bit length are extracted from the PCM code original data.
J'Ij=reducing and extracting means, a first adding means for adding and accumulating substantial lower residual data existing below the upper effective pips 1 to 1 of the PCM code original data, and this first adding means If the addition result is carried within the effective bit position to be transmitted, or if the effective bit position to be transmitted changes to the lower digits as the scale value decreases, the carry actually occurs. a second addition means that adds the carry amount to the transmission data obtained by the compression extraction means when a state corresponding to The present invention is characterized in that it includes a transmission stage that transmits the scale value obtained by the detection means to the transmission system.

[Embodiment of the Invention] FIG. 9 shows the configuration of an embodiment of the present invention. This example will be explained first)! The change in the IS solid scale value in the decreasing direction is expressed as “1”.
9 is an example of the case where the present invention is applied to a system that restricts the number of characters to Similar parts are given the same reference numerals.

In FIG. 9, reference numeral 51 is a data bold register that holds, for example, 16-bit DPCM original data read from the block delay circuit 14 made up of, for example, a delay memory. Reference numeral 52 denotes a compression/extraction circuit configured using, for example, a multiplexer, which outputs, for example, 8-bit transmission data to the D P held in the data bold register 51 according to the scale value given from the scale detection circuit 15.
This is extracted from the Clvl data. Reference numeral 53 denotes an encode counter consisting of, in this case, an 8-bit binary counter that obtains a count start value in parallel low 1-, and is loaded with the output of the compression/extraction circuit 52. 54 is a kind of first mask logic consisting of circuits, which is a type of first mask logic which is held in the data bold register 51 and which is a part of the 8-hit data corresponding to the maximum digit loss due to data compression and extraction in the compression and extraction circuit 52. , at the same point, only the Hi 1~ corresponding to the lower digit drop according to the scale 11Y1 given from the scale detection circuit 15 is outputted through, and the upper Phi 1~ without the digit drop is O゛'
It is masked and output. 55 is an accumulator that calculates the sum of the missing bit at the same point and the cumulative value δ1 to the missing bit 1 up to that point; in this case, an accumulator consisting of a full adder of 8 bits 1 to 1; A second mask logic consisting of a gate circuit for masking the carry focus position data to O'' according to the scale value, 57 holds the total cumulative value of the carry loss bits output from the second mask logic 56. 58 is a carry/overflow detection logic. This carry/overflow detection logic 58 detects the carry data from the output of the accumulator 55 from the digit part corresponding to the scale value to the transmission bit. A circuit using a multiplexer that detects when a certain carry bit becomes "1", and when the pick pattern of the encode counter 53 is "01111111", a condition is established that causes an overflow in the transmitted bit due to carry. It has a gate circuit that becomes active when the overflow condition is not met, and outputs an amplifier count clock (count pulse) to the encode counter 53 in response to the carry detection when the overflow condition is not satisfied.
@, and when the overflow condition 11 is satisfied, carry detection is ignored and a run 1-clock is given to the encode counter 53 in the case of exception handling, which will be described later. 1
7a is a register for Entsu 1 to Shift 1 which constitutes a part of the transmitting circuit 17 shown in FIG. A transmission signal is created by converting the scale value take into serial data and time-division multiplexing and combining. Controller 1 to roll sequencer section 18
are the same as in the case of FIG. 5, and the operation timings of each part of the data hold register 51, entsu 1 to count 53, digit drop holding register 57, kitley/'A-puff flow detection logic 58, and 0/encode shift register 17a are as follows. control etc.

Next, M1 will be explained about the operation 1v that is applied to such a configuration.

The 16-bit DPCM data read out from the block delay circuit 14 by the operation of the sequencer section 18 is latched into the data hold register 51 and applied to the compression extraction circuit 52. The data compressed to 8 bits by the compression/extraction circuit 52 is preset in the encode counter 53. The lower 8 bits 1~ of the output of the data hold register 51 are input to the first mask logic 54, and the first mask logic 54 controls the data of the 8 bits 1~ according to the scale value at that time. Only the cumulative target bits, that is, the zero-digit bits, are passed through as is, and the other non-accumulative target bits are set to 0'
The signal is masked to 0 and applied to the accumulator 55. For example, when the scale value is 3, the lower 3 bits 1 to 1 are passed through and the upper 5 bits are h'X''o''. The output of the digit loss holding register 57, which is the cumulative total of digit loss pins up to 1-, is also input, and the sum of the two is calculated.The output of the accumulator 55 is the carry/
It is input to the overflow detection logic 58, and it is checked whether a '1' (carry) appears at the carry detection position in the old city, that is, the bit position corresponding to the lowest transmitted bit.Carry/overflow detection logic 58 The output of the encode counter 53 is also input to
It is checked at the same time as the carry whether the compressed data pattern meets the above-mentioned overflow condition, that is, 01111111'', and only when a carry occurs and the A-buffflow condition is not satisfied, a certain The up-run 1-clock input at the sequence timing is given to the encode counter 53, and the encode power 1 is input to the up-run 1 of the counter 53.
〜data]+1''. What should be noted here is that 8
For the data of Pitsu 1~, with the condition of carrying from the cumulative total of falling digits Pi 1~
Incrementing by 1'' is equivalent to adding the carry from the digit 1 to the compressed 8 bits. In this way, the data correction function and the accumulator are used to correct the data using a counter.
A feature of this embodiment is that each check can be performed extremely easily by separating the 1m function.

FIG. 10 shows the processing process based on the basic principle, and FIG. 11 shows the processing process according to this embodiment.

FIG. 10(a) shows the DPCM original data, and the scale value at this time is assumed to be 5. The cumulative value of the digit loss bits as shown in FIG. 13(b) is added to this DPCM data to obtain the addition result data as shown in FIG. 14(c). From this addition result data, as shown in FIG. 2(d), a predetermined number of pitches corresponding to the scale value is extracted and transmitted as compressed data.

On the other hand, in this embodiment, the first
As shown in Figure 11 (a), 8-bit data is first extracted from the PCM data (the scale value is 5) from the bit position corresponding to the scale value 5, as shown in Figure 11 (b), and this is encoded. This becomes the load data to the counter 53. At the same time, the lower digits of the DPCM data in (a) of the same figure are the cumulative 51 values of the lower digits shown in (C) of the same figure [same as in Figure 10 (b)]. The result of addition is the addition of the missing digits as shown in FIG. condition is not satisfied), the compressed data shown in (e) of the same figure is 1
be qed.

This compressed data is the same as that shown in FIG. 10(d), and it can be seen that the results according to the principle were obtained in this example.

The output of the accumulator 55 is given to the carry/'overflow detection logic 58, and at the same time, it is also input to the second mask logic 56, and the carry generated by the addition is masked by the second mask logic 56, resulting in a loss of digits. 1 is given to the hold register 57, and the digit 1 of the digit loss bit is latched.

Note that this cumulative value indicates the error between the level decoded on the receiving side and the original level.

The output of the encode counter 53 corrected by such a sequence is input to the encode shift register 17a together with the scale value, converted into serial data by the shift l-clock from the control sequencer section 18, and synthesized. It is output as a transmission signal.

This is the main operation in the configuration of this embodiment, but in this configuration, there is a sequence activated as an exceptional operation in addition to the above-mentioned sequence. This is activated only for data at the beginning of a block when the scale value changes in a decreasing direction.

First, an example of the case where the above-mentioned exception handling is required will be described in detail with reference to FIG.

Figure 12 (a> is the cumulative H4 data from the decimal point 1 to 1 after the final data processing of the block with scale value "5", and Figure 12 (b) shows the scale value changing in the decreasing direction and becoming "4". DPCM data at the beginning of the block in the case of ) is obtained, and the MSB 1"° of the figure (a) is ignored. This is because the accumulated data of the precision bits shown in (a) of the same figure is ignored. MsB is the second mask logic 5
(The second mask logic 5G masks the focus other than the lower 4 bits to "0" in accordance with the scale 1 direct.) Since the masked MSB in FIG. 5A corresponds to the carry detection position when the scale value is "4", it cannot be ignored as is. Therefore, in this way, the number of digits dropped by 1
For the first data when the MSB of the cumulative data is 1'' and the scale value changes in the decreasing direction, before the normal sequence of cumulative missing bits is activated,
A sequence for absorbing the MSB of the above-mentioned decimal point] to cumulative t1 is exceptionally required.

The processing process when this exception handling is added will be explained with reference to FIG.

Figure 113 (a), (b > +, t respectively h Figure 12 (a)
, (b), and Fig. 13 (C) is similar to Fig. 12 (C
), but in this case it is the load data of the encode counter 53.

Figure 13 (1) is the compressed data obtained as a result of the above exception processing, and the MSB of the cumulative lost bits in Figure 13 (a) is
The encode counter 53 is incremented on the condition that the MSB of the accumulated bit loss bits in FIG. 5(a) is "1", and the data in FIG. This is the result of r+14. The same figure (e
) is the cumulative data of lost bits as a result of masking the MSB in (a), and (f) is the result of adding the lost bits of the DPCM data in (a) to (e). This is cumulative lost bit data.

FIG. 14 shows the control flowchart 1 to 1 of this embodiment including the above-mentioned exception handling sequence.

In the above, the carry/overflow detection logic 58 detects an overflow condition of the compressed data, and if a carry would cause an overflow, no carry is performed and the carry is ignored. This is to reserve the carry when the carry due to the accumulated data with dropped digits causes an overflow in the transmission hit.
When transmission is performed by adding the carry amount to the connected data so that the integral 1st shift becomes the correct value, if the above carry reservation occurs multiple times, there will be a problem with the accuracy of the data in terms of time. This is because, in contrast, if the above-mentioned procedure is adopted, a practically effective result can be obtained by performing an incomplete integral operation when performing integral addition on the receiving side. In addition, in this case the decreasing direction of the scale value l
Since the change in \ is limited, the occurrence of the above-mentioned A-buff flow is extremely small, and the above-mentioned processing can provide sufficient effects.

In this way, with a very simple configuration, it is possible to perform transmission-footer correction, correction based on cumulative loss of digits, and the accompanying checks extremely effectively.

It should be noted that the present invention is not limited to the embodiments described above and shown in the drawings, but can be implemented with various modifications without changing the gist thereof.

That is, in the above embodiment, the case where the present invention is used in combination with a technique that limits the change in the scale value in the decreasing direction to "1" will be described, and in such a case, the system configuration can be most simplified. Without a doubt, the most significant feature of the present invention is that by separating the cumulative compensation for lost bits and the transmission data correction function, the original data can be made longer, for example by 16
The point is that there is no need for a full adder for the maximum lost bit length (for example, 8-bit length) only for the total lost bit length. Therefore, if the configuration is such that the correction bit length with the compressed data can be varied in accordance with changes in the ζ scale value, it is possible to increase the precision to 1 by 1 even when the decrease in the scale value is not restricted.

Furthermore, it goes without saying that the present invention can be effectively applied not only to DPCM transmission but also to other PC and M transmissions including normal PCM.

[Effects of the Invention According to the tree - Supplementary data W) - Calculate the cumulative total of lost bits with a simple configuration, including checking for carry and overflow from the lost bits. A transmitting device that can be realized extremely effectively can be provided.

[Brief explanation of the drawing]

Fig. 1 is a system block diagram for explaining an example of differential PCM, Fig. 2 is a system block diagram showing an example of data compression going to p c '+, and Figs. 3 and 4 show the same side. Figures 5 and 6 are system block diagrams of the transmitting side and receiving side, respectively, showing the configuration of an example of the transmission system to which the present invention is applied, and Figures 7 and 8 are system block diagrams of the four sides. FIG. 9 is a block diagram showing the configuration of an embodiment of the present invention. FIGS. 10 to 13 are diagrams to explain data processing in the embodiment. Figure 1/1 is a control flowchart 1 to 1 showing the flow of processing in the same embodiment. 17a...Encode shift 1-register, 18...
51...f-hole 1-register, 52...compression/extraction memory, 53...en5-de counter, 54...first mask logic,
55...Accumulator, 56...Second mask logic. 57...Digit retention register, 58...Carry/overflow detection logic. Applicant's agent Patent attorney Takehiko Suzue

Claims (2)

[Claims] (1) scale detection means for dividing the PCM code original data into blocks for each predetermined data group that is continuous in time series, and detecting a level representing each block as a scale value;
compression extraction means for extracting the upper effective bits of a predetermined hit length from the PCM code original data according to the scale value; A first addition means for adding and accumulating the remaining data, and when the addition result of the first addition means carries within the effective bit position to be transmitted, or when the effective bit position to be transmitted is within the scale value. A second step for adding the carry amount to the transmission bit data obtained by the compression extraction means when a state corresponding to the above-mentioned carry has substantially occurred due to a change to the lower digits due to the decrease; A transmitting device comprising: an adding means; and a transmitting means for transmitting the transmission data obtained by the second adding means and the scale value obtained by the scale detecting means to a transmission system. (2) The second addition means checks the carry to the valid bit 1-position generated by the first addition means and the hit pattern of the valid bit position data extracted by the compression extraction means, and adds the above valid bit position data. means for determining whether an A-flow outside the effective hit position occurs in the bit position data; and control 2Il for determining whether or not to perform addition correction to the transmission data of the carry data according to the result of this determination;
2. The transmitting device according to claim 1, further comprising means for: 3) The second addition means is characterized in that the second addition means uses a counter in which the count start data is pre-selected at the input counter as an adder. Transmitting device.