JPS6226101B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an encoding and decoding method for encoding an analog signal into a digital signal and decoding a digital signal into an analog signal.

Figure 1 shows the audio file device.
Reference numerals 4 denote a clock, CRT display, keyboard, and printer, which are input/output devices for the computer 5. 6 is a magnetic disk device,
The audio signal is digitized and recorded.
Reference numeral 7 denotes an audio signal processing circuit that includes an encoder that digitizes the analog audio signal inputted from the terminal 13 and a decoder that converts the digital signal back into an analog signal and outputs it to the terminal 14. Reference numerals 8 and 9 are buffer memories for mutual speed conversion when writing to and reading from a magnetic disk, since the speed of encoding and decoding the audio signal and the transfer speed of the magnetic disk device are different. This is done by a so-called chaining method in which writing and reading are performed alternately. Reference numerals 10 and 11 are signal switching circuits for switching signal paths during chaining. A circuit 12 receives instructions from the computer 5 and controls the buffer memories 8, 9 and the magnetic disk device 6.

In the above-described system, while it is necessary to increase the compression ratio of the signal in order to substantially increase the recording capacity, there is no need to give much consideration to the continuity required for normal audio signal transmission. That is, although the audio signals at the terminals 13 and 14 must be continuous, even if the audio signals are discontinuously transmitted between the audio processing circuit 7 including the encoder/decoder and the buffer memories 8 and 9, I can't help it.

The encoding and decoding system according to the present invention is suitable for such uses and incorporates the ideas of variable length encoding and amplitude compression/expansion.

That is, when encoding and transmitting an analog signal, the present invention divides the signal to be transmitted into fixed periods, detects the number of bits required to transmit the sample value with the maximum absolute value in that period, and calculates the number of bits for each block. All the sample values included in the block are transmitted using the number of bits required to transmit the sample value, and if the maximum value exceeds a certain level, the m-th bit from the largest digit that produces a 1 is transmitted, excluding the sign bit. The sum of m-1 higher-order bits rounded off and the sign bit m
By transmitting only bits, the compression ratio is increased.

Next, one embodiment will be described according to the drawings. FIG. 2 shows an encoder, and FIG. 3 shows a decoder suitable for this. 13 is an analog audio signal input terminal, 4
0 is an AD converter, 15 is a bit number detection circuit that detects the required number of bits required to transmit the maximum sample value of the input signal for a certain period of time, and 16 is a circuit that delays the output of the AD converter 40 by this certain period of time. delay circuit, 1
7 is a quantization step control circuit, 18 is a buffer register control circuit, 19 is a compression circuit, 20 is a buffer register, 21 is a multiplex circuit, and 22 is an output terminal.

Next, the operation will be explained. The analog signal coming in from the terminal 13 is converted into a digital signal by the AD converter 40. Required bit number detection circuit 15
monitors the output code of the AD converter 40 for a time T (the block length) and detects the number of bits required to represent the sample value with the maximum absolute value during that time. The delay circuit 16 delays the output of the AD converter 40 for the period T mentioned above. The quantization step control circuit 17 controls the compression circuit 19 so that the output of the bit number detection circuit 15 to the output of the delay circuit 16 is optimally compressed and encoded. The compression circuit 19 is the delay circuit 16
This circuit obtains the code of m (m<n) bits/sample from the code of n bits/sample output from the circuit. The buffer register 20 writes and reads the output of the compression circuit 19 in accordance with the output of the buffer register control circuit 18. The buffer register control circuit 18 controls the timing and number of clocks when writing and reading the output of the compression circuit 19 to the buffer register 20 according to the output of the required number of bits detection circuit 15. , the output of the buffer register 20 becomes a signal with a reduced number of bits. The multiplex circuit 21 receives the output data of the buffer register 20,
A circuit multiplexes each T block sample with bit information indicating how many bits are being transmitted.

Next, an embodiment of the method for the above operation will be specifically described. FIG. 4 is a diagram explaining the compression method. As an example, the AD converter 40 is a 12-bit/sample AD converter, and this is converted to 8 bits/sample by amplitude compression. . Each bit of the 12-bit code is extracted from the MSD b ₁₁ b ₁₀
. . .b ₁ b ₀ , and this code is a folded binary code, that is, b ₁₁ is a code that indicates the positive/negative distinction, and b ₁₀ b ₉ . . . b ₀ is an absolute value expressed in natural binary. The best way to determine the quantization step is to minimize the quantization error power when converting 12 bits to 8 bits. A method is adopted in which the signal within the block is quantized using the minimum quantization step that can encode the maximum value within the block. Moreover, if the type of quantization step is minimized by Δ so that this can be done by a shift operation, then 2 ⁿ Δ(n=0,
1, 2...). That is, each sample value in block A _i is monitored, and the maximum absolute value is extracted. When the maximum bit of 1 is b _j and 10≧j≧7, for the sample value in A _i , b _j・b _j-1 . . .
When b _j-6 = 1, b ₁₁ b _j b _j-1 ...transmit b _j-6 as is, and when b _j・b _j-1 ... b _j-6 = 0, 2 ^j b _j +2 ^j-1 b _j-1 +
...+2 ^j-6 b _j-6 +2 ^j-6 b _j-7 is calculated, and the result is 2 ^j C _j +2 ^j-1 C _j-1 +...
+2 ^j-6 C _j-6 is obtained, then b ₁₁ C _j C _j-1 ……
Transmits 8 bits of C _j-6 . In Figure 4,
Let a be the code of 12 bits/sample before compression and belong to block Ai, and block Ai
In , 1 did not appear in b ₁₀ and b ₉ , but
If b ₈ =1, it is assumed that it exists. At this time, the code within block Ai can generally be expressed as a. b
is the code obtained by rounding _b1 to obtain an 8-bit signal for a, and c is the code actually transmitted. d is the sign in Ai, b ₈ , b ₁ ... b ₂ =
1, b ₁ and b ₀ are truncated,
f is the code to be transmitted. As a result, it is thought that the code d became e. When the signal level is small and 1 does not occur above b ₇ , for example, in Ai, 1 does not appear in b ₁₀ to b ₅ , but when b ₄ =1, it is assumed that 1 exists at least once. At this time,
The code within block Ai can generally be expressed as g. In this case, the code in Ai is transmitted to the next stage in the form of h or i.

FIG. 5a shows the output code of the AD converter 40,
Each Ai represents a block of time T. b is the output of the delay circuit 16, and is delayed by one block with respect to a. Detection of the required number of bits is performed for each Ai of the signal a, and the result is applied to each Ai of b.

6 and 7 illustrate a method for further reducing the number of transmission bits by extracting only the necessary number of bits from the 8-bit code output from the compression circuit 19. In both figures a, P ₁₁ ,...P ₀ ,
Q ₁₁ , . . . , Q ₀ , . . . are binary numbers representing each sample value of the input of the compression circuit 19 in a certain block. Fig. 6 shows the above j≦6, and Fig. 7 shows the above 10
This is the case when ≧j≧7. In FIG. 6, b represents the output of the compression circuit 19 in the same block, and this example shows the case where each bit is arranged as shown in FIG. 4i. In this block, if r ₁₁ 1r ₄ r ₃ r ₂ r ₁ r ₀ 0 is the sample value with the maximum absolute value, then the sample value in this block is the last 0.
The data is transmitted in a total of 7 bits, excluding the sign bit and the bit representing the absolute value of each sample value. In reality, the buffer memories 8, 9, etc. following the terminal 22 are often processed in 8-bit parallel fashion, so in this case, data is transmitted in an 8-bit array as shown in c. R ₇
. . . R ₀ is in this case a code indicating the number of bits for which the samples in this block are to be transmitted. * is the remainder generated when the total number of bits included in the block is not divisible by 8 when 8 bits are arranged in this way, and any sign may be used here. The changes a to c are made in the buffer register 20 according to the buffer register control circuit 18,
Codes representing bit number information R ₇ . . . R ₀ are multiplexed by a multiplexing circuit 21. Eventually, the symbol c appears at the terminal 22.

Figure 7 shows the case where 10≧j≧7, and r ₁₁
. . . If r ₀ is the maximum value within the currently focused block, the output of the compression circuit 19 will be as shown in b according to the above explanation. In b, the dashed line indicates the code obtained by rounding off the digit of 1 for each sample value. However, as mentioned above, rounding is done when the most significant digit j where "1" of the sample value with the maximum absolute value in the block occurs.
This is done for all sample values in the block only when is in the range of 10≧j≧7.
Rounding is also performed for the sample value where b _j ·b _j-1 ...b _j-6 =1. however,
At this time, in order to keep the quantization error power low, b
_j・b _j-1 ...b _j-6 is transmitted as is,
At this time as well, a dash has been added to indicate that rounding-related processing has been performed. Therefore, when b _j ·b _j-1 . . . b _j-6 = 1, those with and without dashes are equal. As mentioned above, it is rare that b _j・b _j-1 ... b _j-6 = 1, and even if this situation occurs, the error is negligible. be. In the case of FIG. 7, the output of the buffer register 20 is the same as the output of the compression circuit 19. This code _is multiplexed with bit information R ₇ . d is the code when finally decoded and returned to 12 bits.

Here, the bit information R _{7 .} . . R ₀ is a code indicating the maximum digit in which 1 appears in the sample value of the maximum absolute value in each block.

FIG. 3 shows a decoder, and 24 is a separation circuit that separates bit information and data R _{7 .} . . R ₀ from a code such as c in FIG. 6 or 7. The separated bit number information enters the buffer register control circuit 25 and controls the buffer register 27.
As a result, the output of the buffer register 27 is as shown in FIG.
The code becomes a code like , and a sample of the original number of bits is obtained (12 bits in this example). 28 is buffer register 2
This is a D/A conversion circuit for obtaining an analog signal from the output of 7. A decoded analog signal is obtained at terminal 29.

Figure 8 shows the buffer register 20 in Figure 2.
This is an example.

201 is a parallel/serial conversion register, and 202 is a serial/parallel conversion register. The 8-bit parallel code output of compression circuit 19 is loaded into 8-bit register 201 in parallel. The parallel code input to the shift register 201 is converted into a serial code and then transferred to the shift register 202 until new 8-bit parallel data is loaded into the shift register 201. Shift register 202 is an 8-bit register, and each time the transfer of 8-bit data is completed, it is transferred to buffer memories 8 and 9 in FIG. 1 as 8-bit parallel data.

At this time, the register 201 outputs 8 bits as a serial signal every time 8 bits of parallel data is loaded, but the register 202 outputs 8 bits as a serial signal every time 8 bits of parallel data is loaded. , capture only the necessary bits.

For example, in the example of FIG. 6, when the code P ₁₁ 01P ₃ P ₂ P ₁ P ₀ 0 is loaded into the register 201, the register 202 first takes in the first P ₁₁ 01P ₃ P ₂ P ₁ P ₀ , and then A zero following is not included. continue
Q ₁₁ 001Q ₂ Q ₁ Q ₀ 0 is loaded into 201, and when register 202 has taken in up to Q ₁₁ , register 2
02 is full and buffer memory 8 or 9
The data is transferred to 8-bit parallel data. similarly
When 001Q ₂ Q ₁ Q ₀ r ₁₁ 1 is taken into the register 202, the register 202 becomes full and is transferred to the buffer memory 8 or 9 as 8-bit parallel data. Similarly, if bit number information is multiplexed on the data transferred to the buffer memory every 8 bits, a code as shown in FIG. 6c is obtained. register 202
captures or ignores bits by controlling the clock provided to register 202, which follows instructions from buffer register control circuit 18.

Figure 9 shows the buffer register 27 in Figure 3.
This is an example. 271 is an 8-bit parallel/serial shift register, 272 is a 12-bit serial/parallel shift register, and 273 is a 12-bit latch. The register 271 is loaded with 8-bit parallel data from the buffer memory 8 or 9 each time the data transfer to the register 272 is completed. The register 272 writes the serial data from the register 271, and when it becomes full, it is latched into the latch 273 as 12-bit data, which becomes the output code to the DA converter 28.

For example, in the above example, when P ₁₁ 01P ₃ P ₂ P ₁ P ₀ Q ₁₁ is loaded into register 271, register 272 first captures the first P ₁₁ and for the next five clocks register 271 is not shifted. , register 272
is written as zero. The contents of 271 are then shifted again and register 272 is filled with the following bits.
Since the register 272 becomes full when 01P ₃ P ₂ P ₁ P ₀ is taken in, the contents of the register 272, P ₁₁ 0000001P ₃ P ₂ P ₁ P ₀ , are latched in the latch 273. At the same time as Q ₁₁ is taken into register 272, register 271
is loaded with the next 8 bits, 001Q ₂ Q ₁ Q ₀ r ₁₁ 1. Register 271 is then not shifted for the next five clocks, during which time register 272 is written with a zero. The contents of register 271 are then shifted again and register 272 is shifted back to the next bit.
001Q ₂ Q ₁ Q ₀ is fetched and the contents of register 272 are read.
Q ₁₁ 00000001Q ₂ Q ₁ Q ₀ is latched in latch 273. Similarly, the 8-bit code output from the buffer memories 8 and 9 is converted back to a 12-bit code as shown in FIG. 6a or 7d, and an analog audio signal is obtained by the DA converter 28.

As is clear from the above explanation, the bit number information _R7 ... _R0 is a code that indicates how many zeros the register 272 must take in while the register 271 stops shifting. It can be done. This number is the same within the same block, and is five in this example. Therefore, in this example, for example, the number 5 may be sent as R ₇ . . . R ₀ . In other words, this is the bit that represents the sign of the sample value with the largest absolute value within the block.
This is the number of zeros that exist between the MSD and the largest digit where a "1" appears first, excluding MSD.

FIGS. 10 and 11 show an embodiment in which the above method is applied to a predictive encoder. FIG. 10 shows an encoder, and FIG. 11 shows a decoder. In this embodiment, blocks with the same numbers as above perform the same operations as above.

In the predictive encoder 36, 33 is a subtracter, 19
is a compressor, 41 is an expander, 35 is an adder, and 34 is a predictor, which are the compressor 19 and the expander 4.
It has the same configuration as a normal predictive encoder except for 1,
It is also known about its operation. That is, the difference between the input signal to the predictive encoder 36 and the predicted value from the predictor 34 is taken by the subtracter 33, and the output signal of n bits/sample becomes the roughness of quantization according to its size. In the compressor 19 as described above, m
Converted to bit/sample code. The decompressor 41 converts this m-bit/sample signal back into an n-bit/sample signal (the companding rule is the same as above). Compared to the input of the compressor 19, the output of the decompressor 41 has a large quantization step when the input signal of the compressor 19 is large. The output of the decompressor 41 and the output of the predictor 34 are added by an adder 35, and the output of the adder 35 is applied to the predictor 34. The output of predictor 34 produces a value that predicts the next sample value to appear through delay circuit 16.

In the above configuration, the compressor 19 and the expander 41
A circuit for externally controlling the characteristics so that the quantization error power is as small as possible is 32,1.
5.17. That is, the analog signal input from the input terminal 13 is converted to n by the AD converter 40.
Digitized into a code of bits/sample. 32
is a predictor having the same configuration as 34, and the subtracter 31
The difference between the actual value and the predicted value is taken by . 16 is a delay circuit that performs a delay of T seconds as described above, and the output of the subtracter 33 is the output of the subtracter 31 delayed for T seconds, plus a quantization error due to companding by the compressor 19 and the expander 41. Almost equal except for The bit number detection circuit 15 monitors the output signal level of the subtracter 31 for each T seconds, and the quantization step control circuit 17 detects the output signal of the subtracter 33 in the same manner as explained in FIG. Compressor 19, expander 4
generates quantization information for controlling 1. The bit-reduced signal from the compressor 19 is variable-length encoded by the buffer register 20 in the same manner as described above, and the output of the buffer register 20 and bit number information are multiplexed by the multiplexing circuit 21, and the terminal 22 A compressed band signal is obtained. That is, in digital transmission, the number of bits of a signal to be transmitted can be reduced by band compression as described above.
FIG. 11 shows the decoder. The band compression signal obtained at the terminal 22 of the encoder shown in FIG. 10 is transmitted to the input terminal 23 of the decoder shown in FIG. 11 via a transmission system. The band compression signal obtained at the input terminal 23 passes through a separation circuit 24 to separate the bit number information, and the buffer register control circuit 25 performs the above-mentioned processing by the buffer register 27 in accordance with this information. As a result, the same signal as the output of the expander 41 in FIG. 10 is obtained at the output of the buffer register 27. Therefore, Figure 10 and Figure 1
The outputs of the adder 35 in Fig. 1 are equal and can be expressed as
If the DA converter 28 performs DA conversion, an analog audio signal is obtained at the terminal 29. By configuring the predictor in this way, the number of bits can be further reduced for highly correlated signals such as audio signals.

As described above, in the encoding and decoding method according to the present invention, data does not appear as encoded output with a clock of a fixed period, and therefore there is a problem if it is used as is for normal communication. When used in an audio file device or the like as shown, there is no problem at all as long as a continuous signal is finally obtained. Rather, here, the size of the quantization step for the signal to be recorded is controlled by the size of the input signal, and since it is only necessary to send only the necessary number of bits, albeit in block units, the information that the magnetic disk should store is It only takes a small amount, and the effects are significant.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the audio file device, Figure 2
The figure is a block diagram of a first embodiment of an encoder using the encoding method according to the present invention, FIG. 3 is a block diagram of a first embodiment of a decoder using the same decoding method, and FIG. 5, 6, and 7 are explanatory diagrams showing the code processing process according to the present invention, FIGS. 8 and 9 are explanatory diagrams showing the operation of the main parts of the present invention, and FIG. 10 is an explanatory diagram showing the code processing process according to the present invention. FIG. 11 is a block diagram of a second embodiment of the decoder. 15... Bit number detection circuit, 17... Quantization step control circuit, 19... Compression circuit, 24... Separation circuit, 25... Buffer register control circuit, 2
7... Batsufua register.

Claims (1)

[Claims] 1. In a coding method that encodes and transmits an analog signal, the signal to be transmitted is divided at regular time intervals, and the sample value with the maximum absolute value included in each block is transmitted. When transmitting all the sample values in the block containing the sample value with the number of bits required for the data, if the number of bits exceeds a certain value m, the maximum sample value is quantized so that it can be encoded with m bits. By changing the step, all the sample values in the block containing that sample value are encoded with that quantization step, and the maximum digit that occurs is 2, excluding the sign bit that represents the sign bit of the sample value with the maximum absolute value. An encoding method characterized in that, where ^j is the sample value, a number corresponding to j is multiplexed and transmitted as bit information for a block containing this sample value. 2 In a coding method that encodes and transmits an analog signal, the signal to be transmitted is divided at fixed time intervals, and each block is divided into blocks with the number of bits required to transmit the sample value with the maximum absolute value included in that block. When transmitting all sample values in a block containing sample values, if the number of bits exceeds a certain value m, the quantization step is changed so that the maximum sample value can be encoded with m bits, and the sample value is When all sample values in a block containing a value are encoded using the quantization step, and the maximum number of digits that result in 1 is 2 ^j , excluding the sign bit that represents the sign bit of the sample value with the maximum absolute value, then this For a block containing a sample value, a signal transmitted by multiplexing the number corresponding to j as bit information is received, and based on the bit information multiplexed for each block, a sign bit indicating positive or negative is transmitted. Insert "0" between the code representing the reduced absolute value of the number of bits, and insert the lower digits so that the total number of bits of that code is equal to the number of bits before the number of bits was reduced. A decoding method characterized in that decoding is performed by inserting "0" into the characters.