KR100686354B1 - Huffman decoding method and device for using variable length tree - Google Patents

Abstract

A Huffman decoding method using a variable length tree and an apparatus thereof are provided to reduce a waste of a memory by reducing a generation of a non-terminal node through the variable length tree. A storing unit(140) stores data information to include segment information and symbol information for a coded code word, and data information including stream information to be received in an n+1 clock. A demultiplexer(110) receives a stream input control order or offset information of an n-1 clock. The demultiplexer(110) receives a variable bit stream from an external buffer according to the stream input control order. A bit movement unit(120) performs an operation when a bit stream is below a reference bit stream, and generates offset information by shifting the bit stream. An address determining unit(130) receives the offset information and the segment information of the n-1 clock, and calculates an address value by adding the offset information to the segment information. A control unit(150) reads and analyzes the data information from the storing unit(140) based on the calculated address value. The control unit(150) outputs the symbol information if index information is included in the read data information. The control unit(150) generates and outputs the segment information and the stream input control order if the symbol information is not included in the data information.

Description

Huffman decoding method and device for using variable length tree

1 is a block diagram of a Huffman decoding apparatus according to an embodiment of the present invention.

2 illustrates a first Huffman codebook to a third Huffman codebook according to an embodiment of the present invention.

3 is an exemplary diagram showing a Huffman codebook in a variable tree according to an embodiment of the present invention.

4 is an exemplary diagram showing a memory structure for a variable length tree search in a table form according to an embodiment of the present invention.

5 illustrates an Huffman codebook as a conventional binary tree.

6 is an exemplary diagram showing a memory structure for a conventional binary tree search in a table format.

7A to 7C illustrate the format of an address and data stored in a storage unit according to an exemplary embodiment of the present invention.

8 is a flowchart illustrating an operation of an Huffman decoding apparatus according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

110: demultiplexer

120: bit moving part

130: address value calculation unit

140: storage unit

150: control unit

The present invention relates to a Huffman decoding method and apparatus, and more particularly, to a Huffman decoding method and apparatus using a variable tree.

In general, the Huffman algorithm is one of lossless compression techniques and is a compression technique capable of entropy compression. Huffman algorithm performs data compression by allocating codes of different lengths in consideration of the frequency of occurrence of data, and assigns small codes to frequently occurring data and long codes for less frequently occurring data. Improved data compression performance. Huffman algorithms are widely used to compress video, still images and audio data, as is well known.

The Huffman coding method using a conventional binary tree has been regarded as a very efficient method in terms of maximum and average search time and deviation of search time. However, the Huffman coding method using the binary tree is a complex method of constructing a binary tree and the characteristics of the binary tree prevent memory waste due to the generation of more non-terminal nodes than actual symbols, and the movement between nodes due to the binary tree search. Due to the increase in the number of comparisons performed, there are many problems such as overall performance degradation.

Accordingly, an object of the present invention to solve the above problems is to provide a Huffman decoding apparatus and method that can improve the overall performance by reducing the search step using the Huffman algorithm using a variable length tree.

Another object of the present invention is to provide a Huffman decoding apparatus and method that can reduce the generation of non-terminal nodes by using a variable length tree, and consequently a waste of memory.

It is still another object of the present invention to provide a Huffman decoding apparatus and method which can be applied to a Huffman decoder of an MPEG audio decoder using a small area of logic gate and a small memory.

It is still another object of the present invention to provide a Huffman decoding apparatus and method which can easily control a clock by significantly reducing a decoding period deviation and can reduce the total number of bits of a memory by half by not storing a codeword.

Other objects of the present invention will be easily understood through the description of the following examples.

In order to achieve the above object, according to an aspect of the present invention, there is provided a Huffman decoding apparatus that can variably receive and decode a bitstream.

According to a preferred embodiment of the present invention, a storage unit for storing data information including segment information and symbol information on a codeword coded using Huffman coding and stream information to be input at an n + 1 clock. ; a demultiplexer which receives a stream input control command or offset information of an n-1 clock and variably receives a bitstream according to the stream input control command from an external buffer; A bit shifter for performing offset operation to shift the bitstream to generate offset information when the bitstream is less than or equal to a reference bitstream; An address determination unit receiving the offset information and segment information of the n-1 clock and calculating the address value by adding the offset information and the segment information; And read and analyze data information from the storage unit using the calculated address value to output the symbol information if index symbol information is included. If the symbol information is not included, segment information and stream input control command are issued. A Huffman decoding apparatus including a control unit for generating and outputting may be provided.

If the input bitstream is 1 bit and its value is 0, the demultiplexer may receive and output offset information of n-1 clocks.

When the demultiplexer receives the bitstream for the first time from the buffer, the demultiplexer receives only 1 bit and transfers the bitstream to the bit shifter, and the bit shifter can generate offset information without shifting the 1-bit. have.

The stream input control command may be size information of a bitstream to be input from the buffer.

The bit shifter may generate offset information by shifting the bitstream to the left by performing an operation when the bitstream input from the demultiplexer is 2 bits or less.

According to another aspect of the present invention, a method for receiving a bitstream encoded by a Huffman algorithm using a variable length tree and outputting symbol information corresponding to an arbitrary codeword, and a recording medium having recorded thereon a program for performing the method. Is provided.

According to an embodiment of the present invention, in a method of receiving a bitstream encoded by a Huffman algorithm using a variable length tree and outputting symbol information corresponding to an arbitrary codeword, the stream input from an n-1 clock Receiving a bitstream variably according to an input control command; Determining whether the input bitstream is less than or equal to a reference bitstream; Generating offset information by shifting the input bitstream if it is less than or equal to the reference bitstream; Calculating an address value by adding the offset information and segment information of an n-1 clock; Reading and analyzing data stored in the address value to determine whether it includes symbol information of an index; And if the symbol information is included, a Huffman decoding method using a variable length tree including extracting and outputting the symbol information.

Determining whether the input bitstream is one bit and its value is zero; And if it is determined as 0 (zero), receiving and outputting offset information of the n-1 clock.

If the symbol information is not included, the method may further include generating segment information of the n + 1 clock and a stream input control command.

Determining whether the input bitstream is an initial input; Receiving only 1-bit data if it is the first input; And calculating an address value using the input 1-bit data.

If it is not less than the reference bitstream, the method may further include generating offset information without shifting the input bitstream.

According to another embodiment of the present invention, the digital processing apparatus may be executed by a digital processing apparatus to perform a decoding method of receiving a bitstream encoded by a Huffman algorithm using a variable length tree and searching index information of an arbitrary codeword. A recording medium in which a program of instructions is tangibly embodied, and recording a program that can be read by the digital processing apparatus, the recording medium comprising: receiving a bitstream variably according to a stream input control command input from an n-1 clock; Determining whether the input bitstream is less than or equal to a reference bitstream; Generating offset information by shifting the input bitstream if it is less than or equal to the reference bitstream; Calculating an address value by adding the offset information and segment information of an n-1 clock; Reading and analyzing data stored in the address value to determine whether it includes symbol information of an index; And a recording medium having a program for performing the step of extracting and outputting the symbol information, if the symbol information is included.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

According to the present invention, a desired code is received by receiving several bits at a time from a bitstream of audio data (for example, MP3 (MPEG-1 Layer3, AAC, etc.)) encoded using Huffman coding using a variable length tree. The index value of a word can be output.

In addition, numbers (eg, first, second, etc.) used in the present specification are for distinguishing the same or similar entities, but the scope of the rights or the objects thereof are not limited thereto.

1 is a block diagram of a Huffman decoding apparatus according to an embodiment of the present invention, Figure 2 is a diagram illustrating a first Huffman codebook to a third Huffman codebook according to an embodiment of the present invention, Figure 3 A Huffman codebook according to an embodiment of the present invention is shown in a variable tree, FIG. 4 is a memory structure for a variable length tree search according to an embodiment of the present invention in a table form, and FIG. 5 is a Huffman codebook. 6 illustrates a conventional binary tree, FIG. 6 illustrates a memory structure for searching a conventional binary tree in a table format, and FIGS. 7A to 7C illustrate addresses and data stored in a storage unit according to an exemplary embodiment of the present invention. A diagram illustrating the format of.

In addition, in this specification, one clock is defined as each component of the Huffman decoding apparatus 100 according to the present invention performing an operation once to output an arbitrary result.

Referring to FIG. 1, the Huffman decoding apparatus 100 according to the present invention includes a demultiplexer 110, a bit shifter 120, an address value calculator 130, a storage 140, and a controller 150. Include.

The demultiplexer 110 receives the bitstream variably among the bitstreams compressed using the Huffman code under the control of the controller 150 and transmits the bitstream to the bit shifter 120. In addition, the demultiplexer 110 may receive data output from the storage 140 under the control of the controller 150. Hereinafter, the bitstream may be binary data composed of first data (eg, '0') and second data (eg, '1'). That is, the demultiplexer 110 receives a stream input control command generated at n-1 clocks from the controller 150 and receives a bit stream from an external buffer variably according to the stream input control command. Can be delivered to. Hereinafter, for convenience of understanding and explanation, if the current clock is defined as n, the previous clock is defined as n-1 and the next clock is defined as n + 1. Here, n may be an integer of 0 or more.

In addition, the demultiplexer 110 does not output the input stream to the bit shifter 120 when the input stream input from the buffer (not shown) is 1 bit and the first data (eg, '0'). Instead, the offset information of the n-1 clock may be received from the controller 150 and output to the bit shifter 120.

In the present specification, the "input stream" refers to offset information of a bit stream received from the demultiplexer 110 or n-1 clock input from the control unit 150 at n clocks among the bit streams stored in an external buffer (not shown). Let's define.

In addition, hereinafter, the demultiplexer 110 assumes that the 1-bit to 3-bit streams are input.

If the input stream input from the demultiplexer 110 is less than or equal to the reference bitstream, the bit shifter 120 performs an operation by shifting the input stream to generate offset information and transmitting the offset information to the address value calculator 130.

For example, if the input stream input from the demultiplexer 110 is less than or equal to the reference bitstream, the bit shifter 120 may shift the input stream to the left to generate offset information. For example, assume that the input stream input to the bit shifter 120 is '10' and the bit shifter 120 is implemented to perform an operation when the input stream is 2 bits or less. Since the bit shifter 120 has two input bits or less, the bit shifter 120 shifts one bit to the left and generates' 4'h as offset information and transmits the offset to the address value calculator 130.

The address value calculator 130 receives offset information from the bit shifter 120, receives segment information from the controller 150, adds the segment information, calculates an address value of the memory, and transfers the segment information to the controller 150. Here, the address value calculator 130 may be implemented including one or more adders.

The storage 140 is a means for storing address information (eg, segment information), data information, symbol information corresponding to an index, and the like for one or more codewords. For example, the storage 140 may be configured as a ROM, or may be configured as other media. 7A to 7C illustrate formats of data information and address information stored in the storage 140. 7A to 7C are data and address formats according to a preferred embodiment, and may be other formats. FIG. 7A illustrates an address format stored in the storage 140. A total of 11 bit formats including 8 bit segment address information and 3 bit offset address information are illustrated. FIG. 7B illustrates a data format when data coincides with a codeword. The upper 2 bits may be represented by, for example, "00", and the lower 20 bits may store symbol information corresponding to the corresponding codeword. have. In addition, FIG. 7C illustrates a data format when data does not match a codeword. The upper 2 bits store information on the size of the input bitstream required for the next clock, and the lower 8 bits store information on the next clock. Segment information to be used may be stored. 7A to 7C illustrate an example and may be stored in a format other than this.

For example, the storage 140 may store symbol information which is sample data of a spectrum corresponding to an index of a codeword. The format of the symbol information to be stored may be, for example, the format illustrated in FIG. 7B.

The storage 140 may store and output index information corresponding to the codeword, but in the present specification, spectral sample (hereinafter referred to as symbol information) information corresponding to the index information is represented by Equations 1 and 2 below. After calculating using Equation 3, Equation 4, and storing it, the symbol information can be directly output.

Here, qp is an spectral sample information stored in the storage unit, and an integer value representing symbol information, off is offset information, idx is an integer value as index information, and mod is a user for efficient calculation to create a Huffman table. Is an integer value.

The controller 150 is a component of the Huffman decoding apparatus 100 according to the present invention (for example, the demultiplexer 110, the bit shifter 120, the address value calculator 130, the storage unit ( 140), etc.). In addition, the controller 150 reads data stored in the storage 140 corresponding to the address value calculated by the address value calculator 130 and determines whether the symbol information of the index of the codebook is included. If the symbol information is included, the controller 150 extracts and outputs the symbol information.

However, if the symbol information is not included, the controller 150 analyzes the data read from the storage 140, extracts segment information, transfers the segment information to the address value calculator 130, and generates a stream input control command. Transfer to the demultiplexer 110.

In the present specification, the "stream input control command" will be defined as a command for controlling the input stream inputted by the controller 150 to the demultiplexer 110.

In addition, when the input stream input to the demultiplexer 110 is one bit, and the bit data of the corresponding input stream is the first bit data, the controller 150 immediately transfers the bit shifter 120 to the center of the current clock. Offset information of all clocks and an operation start control command can be transmitted.

For convenience of understanding and explanation, the Huffman algorithm will be briefly described, and the steps performed to retrieve and output the index 29 using the conventional binary tree method and the variable length tree method according to the present invention will be described. It will be described in the clock unit of.

The Huffman algorithm calculates the statistical occurrence frequency of the raw data of arbitrary raw data, and assigns a short sign to the data according to the high occurrence frequency and a long code to the low occurrence data. For the sake of understanding, suppose the raw data is, for example, "THIS IS THE TEST SENTENCE." At this time, the occurrence frequency for each spell is calculated as shown in Table 1 below.

Table 1. Frequency of occurrence for the sample data

E T S Null H I N C . 5 5 4 4 2 2 2 One One

After calculating the frequency of occurrence for the raw data as described above, a binary tree is constructed using this to assign codes (ie, codewords) to the respective data, as shown in Table 2 below.

Table 2. Code implemented using binary tree Allocation Table

data Codeword data Codeword data Codeword E 11 Null 010 N 0001 T 10 H 0011 C 00001 S 011 I 0010 . 00000

As described above, the Huffman coding method is a method of variably assigning codes according to the frequency of statistical occurrence of raw data. Hereinafter, the Huffman decoding method using the conventional binary tree and the Huffman decoding method using the variable length tree according to the present invention will be briefly described for each clock cycle required to output an arbitrary index.

First, referring to FIG. 2, the first Huffman codebooks of the AAC (Advanced Audio Coding) to the third Huffman codebooks are illustrated by arranging 16 codewords per length in order of length. An example of implementing the first Huffman codebook of FIG. 2 as a binary tree is illustrated in FIG. 4. Here, when each node represents an index, the arc represented by the dotted line may be the first bit (eg, '0') and the arc connected by the solid line may be the second bit (eg, '1'). As shown in FIG. 4, each node may be implemented as two child nodes. The binary tree of FIG. 4 is composed of leaf nodes and non-leaf nodes. The memory data type of a leaf node may be represented, for example, as [0, index], and the memory data type of a non-leaf node may be represented as, for example, [1, segment]. Can be. Here, the segment represents an address of a child node and may be used as an offset address of a first bit (eg, '0') or a second bit (eg, '1') input from the bitstream. . As a method of determining an address of a memory for searching a binary tree, a method of determining a next address value by adding a segment and an offset may be used.

5 illustrates a memory structure of the first Huffman codebook of FIG. 2 for searching a binary tree. Referring to FIG. 2, a process for finding an index 29 located at level 5 will be briefly described. First, first input data (eg, '1') is input at a first clock. When the first input data is input, an address value of the memory is determined by adding a segment and an offset. That is, the address value of the memory in the first clock may be determined as' 01'h, for example. It is determined whether the data of the determined address value of the memory matches the data of the codebook. That is, since the data of the address value of the memory is, for example, [1, 02], the segment is extracted from the data because it does not match the codebook. For example, '02' may be extracted.

When the second input data (eg, 0) is input at the second clock, an address value of the memory may be determined by adding an offset and a segment extracted from the first clock. For example, the address value of the memory at the second clock may be determined as a segment extracted from the first clock, for example, '02'h plus an offset of the second clock, for example,' 02'h. Can be. It is determined whether the data of the determined address value matches the data of the codebook. That is, since the data of the determined memory address value (for example, '02'h) is, for example, [1, 04], it does not match the data of the codebook, and thus the segment is extracted.

When third input data (eg, '1') is input at the third clock, an address value of the memory is determined by adding an offset and a segment extracted from the second clock. For example, the address value of the memory may be determined as' 05'h. The data stored in the address is read using the determined memory address to determine whether the data corresponds to the data in the codebook. That is, since the data stored in the memory is, for example, [1, 0C], the segment is extracted because it does not match the data of the codebook.

When the fourth input data (eg, 0) is input at the fourth clock, the address value of the memory may be determined as' 0C'h. Since the data of the determined memory address value is [1, 0E], the data of the codebook Since it does not match, we extract the segment.

When the fifth input data (eg, 0) is input at the fifth clock, the address value of the memory may be determined as' 0E'h, and it is determined whether the data of the determined address value of the memory matches the data in the codebook. do. Here, since the data of the address value of the memory is [0, 29], since the data is identical to the data of the codebook, the index can be extracted and output.

As described above, since the binary tree receives 1 bit as an input from each clock, it took 5 cycles to retrieve the index data of the fifth level as described above. That is, it takes up to 19 cycles to perform a search for a codeword consisting of up to 19 bits in the binary tree. As illustrated in FIG. 4, in the case of a binary tree, a large number of non-terminal nodes are generated than actual symbols, and it can be seen that memory is wasted.

An example of implementing the first codebook of FIG. 2 using the variable length tree according to the present invention is illustrated in FIG. 3. In the present invention, a variable length is set to 3, and a bit string is variably input and decoded up to 3 bits. This will be described in detail with reference to FIG. 1 below.

3 illustrates the implementation of the first Huffman codebook illustrated in FIG. 2 using a variable length tree according to the present invention. The variable length tree according to the present invention receives an input of 1 bit to 3 bits from the bitstream to lower the tree level, thereby reducing the number of non-terminal nodes. That is, memory waste due to non-terminal nodes can be reduced. 4 is a diagram illustrating a memory structure for searching for a variable length tree represented as shown in FIG. 3. A method of searching index 29 will be described with reference to FIG. 4.

One bit is input to the first input data from the first clock. In the search using the variable length tree according to the present invention, when a bit is first input in the bitstream, only one bit is received. That is, when the first input data (eg, '1') is input, the memory address value of the first input data is determined by adding the segment and the first input data. That is, the address value of the memory of the first input data in the first clock may be determined as' 01'h, for example. The stored data is read using the determined address value of the memory to determine whether it matches the data of the first codebook. If it does not match, the data is determined to determine how many bits of the next bitstream to receive from the next clock, and the segments are extracted to determine the address value of the next clock's memory. Since the data of the determined address value of the memory is, for example, [3, 08], it may be determined that the data of the first codebook does not coincide with the data of the first codebook, and that a 3-bit bitstream should be input from the second clock. In addition, the segment '08'h is extracted and used to determine the memory address value of the input data of the second clock.

The second input data is received at the second clock. Here, it is determined that a 3-bit bitstream must be input from the first clock, and the 3-bit stream is received. That is, the second input data may be, for example, '010'. The address value of the memory of the second input data is determined by adding the offset of the segment extracted from the first clock and the second input data. Therefore, the address value of the memory of the second input data may be determined as' 0A'h, for example. It reads the data of the address value of the determined memory and determines whether it matches with the data of the first codebook. If it matches, it outputs index data. If it does not match, the number of bitstreams to be input at the next clock is determined, and the segment is extracted. . For example, it can be seen that the address value of the determined memory does not match the data of the first codebook because the data of '0A'h is [1,10]. Therefore, the number of bitstreams to be input at the third clock is determined as' 1 ', and the segment' 10'h is extracted.

The third input data is received at the third clock. Here, as determined in the second clock, one bit stream (eg, '0') is received. If the third input data is not a 3-bit stream, the previous offset data is shifted to the left corresponding to the 3-bit stream. That is, since the third input data is' 0 ', the offset' 2'h of the second clock is shifted to the left once. That is, the offset value of the third input data may calculate '4'h. In addition to the segment of the second clock, an address value of the memory is determined. For example, the address value of the memory may be determined as' 14'h. The data of the determined address value of the memory is read, and it is determined whether the data corresponds to the data of the first codebook. Here, since the data of the determined memory address value is [0, 29], it can be seen that the data of the first codebook matches. Therefore, the index '29'h can be output.

As described above, it can be seen that the Huffman decoding method using the variable length tree according to the present invention has a shorter tree search time than the Huffman decoding method using the conventional binary tree.

8 is a flowchart illustrating an operation of an Huffman decoding apparatus according to an embodiment of the present invention. Hereinafter, a process of decoding a compressed bitstream using the Huffman encoding method will be described. Hereinafter, when the demultiplexing unit 110 is the first input, only one bit is input and a decoding process is performed. After this, the input stream according to the stream input control command input from the control unit 150 at n-1 clock is input. Receive the decryption process. Hereinafter, assuming that the demultiplexer 110 can receive a maximum of 3 bit streams, the description will be focused on the above. However, it is natural that the demultiplexer 110 may receive and process other bit streams at once. Also, for convenience of explanation and explanation, the following describes a process of outputting index data corresponding to an arbitrary codeword after one Huffman codebook is selected. In addition, the input streams input to the demultiplexer 110 may be stored in, for example, a 1KB input buffer and input to the demultiplexer 110 as 1 to 3 bit streams. Of course, the size of the input buffer may vary in addition to 1KB.

In operation 810, the demultiplexer 110 receives a stream input control command from the control unit 150 at n-1 clocks and variably receives a bitstream from an external buffer (not shown) according to the corresponding stream input control command (hereinafter, referred to as a multiplexer). In the following description, it is transmitted to the bit moving unit 120.

Here, the stream input control command may be a command for controlling how many bits the demultiplexer 110 receives a stream from an external buffer as described above.

In addition, when the input multiplexer 110 receives an input stream of 1 bit and is the first data, the demultiplexer 110 does not transmit the input stream to the bit shifter 120, and controls the offset information of the n−1 clock. Received from the bit transfer unit 120 may be delivered.

For example, the input stream input to the demultiplexer 110 is 1 bit, for example, the first data (for example, '0'), and the offset information of the n-1 clock is '10'. Suppose Then, since the input multiplexer 110 is a 1-bit stream including only the first data, the demultiplexer 110 may receive the offset information of the n-1 clock from the controller 150 and transmit the received offset information to the bit shifter 120.

In addition, when the first multiplexer 110 receives an input stream from an input buffer (not shown) for the first time, the demultiplexer 110 may receive only one bit and transmit the received bit to the bit shifter 120. In this case, the bit shifter 120 Even if the input 1 bit is less than or equal to the reference bitstream, the offset information may be generated and transferred to the address value calculator 130 without shifting.

In steps 815 to 820, the bit shifter 120 determines whether the input stream input from the demultiplexer 110 is less than or equal to the reference bitstream, and if it is less than or equal to the reference bitstream, performs the operation to shift the input stream to the left. The offset information is generated and transmitted to the address value calculator 130.

For example, assume that the input stream input from the demultiplexer 110 is "10" and the reference bitstream is 2 bits. Since the input stream is less than or equal to the reference bitstream, the bit shifter 120 may shift the input stream by one bit to the left to generate offset information and transmit the offset information to the address value calculator 130.

The bit shifter 120 may generate the input bitstream as offset information and transmit it to the address value calculator 130 without performing an operation if the input stream exceeds the reference bitstream or is initially input.

In operation 825, the address value calculator 130 calculates an address value by adding the offset information input from the bit shifter 120 and the segment information extracted from the n-1 clock and input from the controller 150 to calculate the address value. To pass.

For example, assuming that the input stream is the first input to the demultiplexer 110 and the bit data of the input stream is' 1 ', for example, the address value calculator 130 may set the address value to' 01'h. It can be calculated and delivered to the controller 150.

For example, the segment information extracted from the n-1 clock and input to the address value calculator 130 of the n clock is' 10'h, the input stream of the n clock is' 0 ', and the offset of the n-1 clock. Suppose the information is' 10'h. In this case, since the n clock input stream is '0', the demultiplexer 110 may transmit the offset information '10' of the n-1 clock to the bit shifter 120. If the bit shifter 120 receiving the offset information of the n-1 clock is less than or equal to the reference bitstream (for example, 2 bitstream or less), the bit shifter 120 shifts the n-1 offset information by 1 bit. The offset information '100' may be transmitted to the address value calculator 130. Therefore, the address value calculator 130 may add the offset information '04'h and the segment information' 10'h to calculate the address value '14'h and transmit the address value' 14'h to the controller 150.

In step 830, the controller 150 reads and analyzes the data stored in the address value in the storage 140 using the address value calculated and input from the address value calculator 130 to include symbol information corresponding to the index. Determine whether or not.

If it does not include symbol information corresponding to the index, in step 835, the controller 150 extracts the segment from the read data and transfers the segment to the address value calculator 130, and the demultiplexer 110 at the next clock. After generating a stream input control command for the input stream to receive the input and delivers to the demultiplexer 110 proceeds to step 810.

If the symbol information corresponding to the index is included, the controller 150 extracts the corresponding symbol information corresponding to the index and outputs the symbol information corresponding to the index.

As described above, the Huffman decoding method according to the present invention has an advantage that the decoding period deviation is significantly reduced compared to the conventional method, so that the clock can be easily controlled. In addition, in the Huffman decoding method using the conventional binary tree, the search time required up to 100 clocks can be reduced to 6 clocks.

As described above, by providing a Huffman decoding apparatus using a variable length tree according to the present invention, it is possible to reduce the search step to improve the overall performance.

In addition, the present invention can reduce the generation of non-terminal nodes by using a variable length tree can reduce the waste of memory.

In addition, the present invention has an effect that can be applied to the Huffman decoder of the MPEG audio decoder using a small area logic gate and a small memory.

In addition, the present invention can easily control the clock by significantly reducing the decoding period deviation, and has the effect of reducing the total number of bits in the memory by halving the codeword.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art to which the present invention pertains without departing from the spirit and scope of the present invention as set forth in the claims below It will be appreciated that modifications and variations can be made.

Claims (11)

A storage unit which stores data information including segment information, symbol information about the coded codeword, and stream information to be input at an n + 1 clock; a demultiplexer which receives a stream input control command or offset information of an n-1 clock and variably receives a bitstream according to the stream input control command from an external buffer; A bit shifter which performs an operation when the bitstream is equal to or less than a reference bitstream and generates offset information by shifting the bitstream; An address determination unit receiving the offset information and segment information of the n-1 clock and calculating the address value by adding the offset information and the segment information; And Read and analyze data information from the storage unit using the calculated address value to output the symbol information if index symbol information is included, and generate segment information and stream input control command if the symbol information is not included. Huffman decoding apparatus including a control unit for outputting. The method of claim 1, And if the input bitstream is 1 bit and its value is 0, the demultiplexer receives and outputs offset information of n-1 clocks. The method of claim 1, When the demultiplexer receives a bitstream from the buffer for the first time, the demultiplexer receives only 1 bit and transfers the bitstream to the bit shifter, and the bit shifter generates HIP only without shifting the 1-bit. Decryption device. The method of claim 1, And the stream input control command is size information of a bitstream to be input from the buffer. The method of claim 1, And the bit shifter performs an operation when the bitstream input from the demultiplexer is 2 bits or less and shifts the bitstream to the left to generate offset information. A method of receiving a bitstream encoded by a Huffman algorithm using a variable length tree and outputting symbol information corresponding to an arbitrary codeword, receiving a bitstream variably according to a stream input control command input from an n-1 clock; Determining whether the input bitstream is less than or equal to a reference bitstream; Generating offset information by shifting the input bitstream if it is less than or equal to the reference bitstream; Calculating an address value by adding the offset information and segment information of an n-1 clock; Reading and analyzing data stored in the address value to determine whether it includes symbol information of an index; And If the symbol information is included, extracting the symbol information and outputting the Huffman decoding method. The method of claim 6, Determining whether the input bitstream is one bit and its value is zero; And If it is determined to be zero, the Huffman decoding method using a variable length tree further comprising receiving and outputting offset information of the n-1 clock. The method of claim 6, Generating a stream input control command and segment information of an n + 1 clock if the symbol information is not included. The method of claim 6, Determining whether the input bitstream is an initial input; Receiving only 1-bit data if it is the first input; And Computing an address value using the input 1-bit data Huffman decoding method using a variable length tree. The method of claim 6, And generating offset information without shifting the input bitstream if the reference bitstream is not equal to or less than the reference bitstream. In order to perform a decoding method of receiving a bitstream encoded by a Huffman algorithm using a variable length tree and searching index information of an arbitrary codeword, a program of instructions that can be executed by a digital processing apparatus is tangibly implemented. In the recording medium recording a program that can be read by the digital processing device, receiving a bitstream variably according to a stream input control command input from an n-1 clock; Determining whether the input bitstream is less than or equal to a reference bitstream; Generating offset information by shifting the input bitstream if it is less than or equal to the reference bitstream; Calculating an address value by adding the offset information and segment information of an n-1 clock; Reading and analyzing data stored in the address value to determine whether it includes symbol information of an index; And And recording the symbol information, if the symbol information is included.

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