KR0139495B1 - Coding method of video signal by bit division - Google Patents

Abstract

In image signal encoding / decoding, the input 1-byte data of the image signal is divided into upper and lower bits to separate a portion containing a large amount of energy, and an upper portion containing a large amount of energy separated from the input data. 1-bit data of the original size is converted using the partial bits, and the probability of repeating the same pattern is increased, and 1 bit of the original size size is processed for processing by using a lower bit containing low energy separated from the input data. Increase the probability of repeating the same pattern by converting the byte data. The energy-rich bit-converted output is coded losslessly, and the energy-low bit-transformer output is coded lossy. The lossless coding output is losslessly decoded in the same manner as the coding, the lossless coding output is decoded in the same manner as the coding, and the output including the high energy of the lossless coding unit is separated into original pixel data to have the same size. . And combine the bit separation and lossy decoding output.

Description

Method and apparatus for encoding / decoding of image signal by bit division

1 is a block diagram for explaining a coding example of a conventional image.

2 is a block diagram for explaining a conventional example of decoding a picture.

3 is a diagram for explaining an image data configuration.

4 is a coding system diagram using a nonblocking principle and using a lossless and lossy coding method according to an embodiment of the present invention.

5 is a decoding system diagram using a nonblocking principle and using a lossless and lossy decoding method according to an embodiment of the present invention.

FIG. 6 is a diagram showing a conversion state in respective configuration data in the second bit conversion units 204 and 206 of FIG.

FIG. 7 illustrates an example of separating the decoding bits of FIG. 5 in the bit separator 216. FIG.

8 is a circuit diagram of a specific embodiment of FIG. 4 in accordance with the present invention.

9 is a clock timing diagram of clock stages CLK0 to CLK4 of FIG.

10 is a detailed implementation circuit diagram of FIG. 5 according to an embodiment of the present invention.

11 is a timing diagram for selecting clock stages CLK0 to CLK4 and multiplexer 428 of FIG. 10 according to an embodiment of the present invention.

12 is a view for explaining a separation example according to an embodiment of the present invention.

13 is a coding system diagram using a block principle as an embodiment according to an embodiment of the present invention and using a lossless and lossy coding method.

14 is a diagram of a decoding system using the principle of enabling and using a lossless and lossy coding method as another embodiment according to an embodiment of the present invention.

FIG. 15 is a detailed circuit diagram of FIG. 13 according to an embodiment of the present invention. FIG.

16 is a detailed circuit diagram of FIG. 14 according to an embodiment of the present invention.

17 and 18 are detailed circuit diagrams and operation timing diagrams of the first clock generator 601 of FIG.

19 and 20 are specific circuit diagrams and operation timing diagrams of the second clock generator 603 of FIG.

21 and 22 are detailed circuit and operational waveform diagrams of the clock generator 755 of FIG.

23 and 24 are concrete circuit diagrams and operational waveform diagrams of the clock generator 756 of FIG.

The present invention relates to a method and apparatus for encoding / decoding an image. In particular, high-order bits having high energy by bit-segmenting an input video signal are coded with loss less without loss and most of low energy. The lower bits of the present invention are related to a method and apparatus for encoding / decoding an image by bit division, which can realize high compression and high image quality by coding lossy that can be taken even with some loss.

In general, in order to efficiently transmit or accumulate an image or an audio signal as a digital signal, entropy coding (eg, entropy coding) that compresses the amount of data is used.In contrast, the same method of coding and decoding is used for transmission. Decrypted by the method.

In the conventional coding method, 8-bpp (bits-per-pel or pixel) (or 12bpp) images per color element are used for compression / restore for compression / restore.

Looking in detail with reference to Figure 1,

Sub-blocks (n × m 4 × 4, 8 × 8) of a certain range are taken for the image data input to the input terminal 101 and stored in the storage unit 102, and the data stored in the storage unit 103 is The DCT processing unit 104 processes the compression, and according to the Discrete Cosine Transform (DCT) method, it shows a good performance for a highly correlated video signal. The transformed value is input to the quantization processing unit 106 and quantization is performed according to a difference from an already encoded and predicted value stored in the first table unit 110.

The value quantized by the quantization processing unit 106 is input to the Hoffman de-toding unit 108 and assigned to be encoded according to the occurrence probability of run-length, which is an output value of the second table unit 112 already stored. See the process from. The Huffman coding unit 108 converts and outputs a shorter code as a signal having a higher frequency of occurrence of the same signal when the signals are not correlated with each other according to the probability of generating the output signal of the quantization processor 106. The output value is input to the Huffman decoding unit 114 of FIG.

The Hoffman decoding unit 114 receives the output of the Hoffman coding unit 108 and decodes the received HBrman coding unit 108 by referring to a value stored in the third table unit 122 and inputs it to the dequantization processing unit 116. The inverse quantization unit 116 performs inverse quantization according to the difference between the predicted value recorded in the fourth table unit 124 and inverse DCT processing in the inverse DCT processing unit 118 to restore and store the original signal. It is stored in the unit 120.

In the above processing method, the input data is 8 bits, and in the case of FIG. 3, most energy is concentrated in Bit- _{7 to} Bit4 (B _{7 to} B ₄ ), and the remaining lower bits have little or no energy. Due to this, if entropy coding is applied, the compression rate cannot be increased. This is because the full resolution reduces the probability of matching the pattern provided by the entropy coder. Conventional techniques to improve this method take a pre-processing process using DCT and quantization method to generate data that conforms to the pattern of entropy coder, but does not provide a fundamental solution such as requiring an expensive chipset.

Accordingly, an object of the present invention is to provide a method and apparatus for simultaneously obtaining high quality and high compression by lossless coding of high energy bits and lossy coding of most low energy bits using lossy coding. .

Another object of the present invention is to provide an image compression / restore method and apparatus that can be easily implemented.

Converted to short code and output. The output value is input to the Huffman decoding unit 114 of FIG.

The Hoffman decoding unit 114 receives the output of the Hoffman coding unit 108 and decodes the received HBrman coding unit 108 by referring to a value stored in the third table unit 122 and inputs it to the dequantization processing unit 116. The inverse quantization unit 116 performs inverse quantization according to the difference between the predicted value recorded in the fourth table unit 124 and inverse DCT processing in the inverse DCT processing unit 118 to restore and store the original signal. It is stored in the unit 120.

In the above processing method, the input data is 8 bits, and in the case of FIG. 3, most energy is concentrated in Bit- _{7 to} Bit-4 (B _{7 to} B ₄ ), and the remaining lower bits have little or no energy. . Due to this, if entropy coding is applied, the compression rate cannot be increased. This is because the full resolution reduces the probability of matching the pattern provided by the entropy coder. Conventional techniques to improve this method take a pre-processing process using DCT and quantization method to generate data that conforms to the pattern of entropy coder, but does not provide a fundamental solution such as requiring an expensive chipset.

Accordingly, an object of the present invention is to provide a method and apparatus for simultaneously obtaining high quality and high compression by lossless coding of high energy bits and lossy coding of most low energy bits using lossy coding. .

Another object of the present invention is to provide an image compression / restore method and apparatus that can be easily implemented.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 4 is an exemplary block diagram according to the present invention, which is an example of non-blocking. FIG.

An input data bit divider 202 for separating input one-byte data such as FIG.

A first bit converter 204 for converting the data into a one-byte data having an original size by using upper part bits including a large amount of energy separated by the input data bit divider 202, and repeating the same pattern; ,

A second bit converter 206 for converting the input data bit divider 202 into 1-byte data having an original size by using the lower partial bits having low energy separated therefrom, and repeating the same pattern;

A lossless coding unit 208 which encodes the output of the first bit converting unit 204 without loss as lossless by entropy encoding,

A lossy coding unit 210 for encoding the output of the second bit converting unit 206 as lossless by entropy encoding and having some loss;

A lossless decoding unit 212 which decodes the output of the lossless coding unit 208 without loss by entropy decoding in the same principle as the above-described coding,

A loss decoding unit 214 for decoding the output of the loss coding unit 210 in consideration of loss by entropy decoding in the same principle as coding;

A bit separator 216 for dividing the output containing a large amount of energy of the lossless coding unit 212 into original pixel data and having the same size;

Composed of the bit separator 216 and the synthesizer 218 for combining the output of the loss decoding 214, the input pixel data of a certain block is divided in the input data bit divider 202 by the bit division method as shown in FIG. do. Here, the high-order bits 221 having high energy are converted by the first bit converter 204 as in P _{0 to} P ₁ of FIG. That is, the first bit converter 204 converts the probability of repeating the same pattern to the size of the original size so that the lossless coding unit 208 performs lossless coding on the output without loss. 0 in FIG. 7 is the lower bits that contain less energy, and the second bit converting unit 206 converts the original bits to the original size state so that the pattern is repeated. Use lossy coding to recognize that there is some loss.

The outputs of the lossless / lossy coding units 208 and 210 of FIG. 4 are decoded according to the same entropy coding principle in the lossless / lossy decoding units 212 and 214 of FIG.

5 is a diagram of a decoding system using a nonblocking principle according to an embodiment of the present invention and using a lossless and lossy decoding method.

A lossless coding unit 212 which decodes the output of the lossless coding unit 208 without loss by entropy coding principle;

A lossy coding unit 214 which decodes the output of the lossy coding unit 210 while taking into account some loss due to entropy coding principle;

A bit separator 216 for separating the bits of the output decoded by the lossless decoding unit 212,

The synthesizer 218 combines the output of the bit separator 216 and the output of the lossy decoder 214. That is, when the decoding is performed by the lossless decoding unit 212 of FIG. 5, the signal is output in the state of 231 of FIG. 6. This is the same sized byte, which is separated from the bit separator 216 of FIG. 5 by a certain number of bits as in 232 to 235 of FIG. 6, and then outputs from the loss decoding unit 214 and pixel by pixel in the synthesizer 218. The synthesized decoded original image data can be obtained.

FIG. 8 is a circuit diagram illustrating a specific embodiment of FIG. 4. For example, when there is pixel data blocked by 2 × 2, one pixel data P ₀ is input to the input terminal 201 and the first clock of FIG. When latching by the latch circuit 301 according to the clock of the stage CKO, a and b in FIG. 7 are output.

Next, when the second bit is shifted by the 2-bit shift register 303 according to the clock of the second clock stage CK1 of FIG. 8 and latched by the latch circuit 305, the pixel data P ₁ of FIG. d is output. Next, when the 4-bit shift register 307 is shifted 4 bits to the clock of the third clock stage CK2 of FIG. 8 and latched by the latch circuit 309, the next pixel data P ₂ , e and f are output. .

Next, by shifting 6 bits from the 6-bit shift register 311 according to the clock of the third clock stage CK3 of FIG. 8 and latching them in the latch circuit 313, g and h as the next pixel data P ₃ are Is output. Each data except for a, b to g, h of the pixel data P _{0 to} P ₃ is stored in the second memory unit 315.

The data output from the latch circuits 301 to 313 are added by the adder 317, output as shown in FIG. 251 of FIG. 7, and then written to the first memory 319. FIG. As a result, the data can be compressed by ¼ more than the original data amount, and the pixel data a, b to g, h can be compressed at high probability by repeating the same pattern.

Prefixes provided by the first and second prefix providing units 321 and 325 with respect to the output data of the first and second memories 319 and 315 are easily distinguished before the loss or lossless coding of the output data of the first and second memories 319 and 315. In addition, the lossless coding unit 208 performs coding without loss for the output, and the lossy coding unit 210 performs coding separately in consideration of the loss to some extent for the output.

The lossless and lossy coding may use JPEG or Block Truncation Coding (BTC) methods in addition to the Huffman and Arithemetic Based (Huffman) codes.

FIG. 10 is a detailed embodiment view of FIG.

Prefix data, a flag added to distinguish the coded data without loss from the output of the lossless coding unit 208 of FIG. 4, is separated from the first prefix removing unit 402 and inputted by the lossless decoder 404.

From the output of the lossy coding unit 210, the prefix data, which is an added flag, is separated from the second prefix elimination unit 402 and inputted to the lossy decoder 408 to distinguish the coded data having a certain degree of loss. In the lossless decoder 404 or the lossy decoder 408, the lossless coding unit 208 of FIG. 4 and the entropy processing method such as the processing method of the lossy coding unit 210 are used to process the third and fourth memories, respectively. (406, 410).

Data decoded without loss recorded in the third memory 406 (461 in FIG. 12) is read and latched in the latch circuit 418 in accordance with the clock of the clock terminal CLKO, as shown in 462 of FIG. Next, as shown in (11b) of FIG. 11, two bits are shifted in the shift register 412 according to the clock of the clock stage CLK1, and when the latch circuit 420 is latched, data about this occurs as shown in 463 of FIG. do.

Next, as shown in Fig. 11C (4C), the 4-bit shift register 414 is shifted by 4 bits according to the clock of the clock terminal CLK2, and the data latched by the latch circuit 422 464, and shifts 6 bits in the 6-bit shift register 416 according to the clock of the clock stage CLK3 as shown in FIG. 12 (4d), and the latched data in the latch circuit 424 Is generated as 465 of 12 degrees.

When the outputs of the latch circuits 418 to 424 are inputted from the multiplexer 428, the outputs of the latch circuits 418 to 424 are selected according to the output of the selection signal generation circuit 426, and the selection signal generation circuit 426 and (4a) to (11) of FIG. When the signal is logically generated, it is generated as (4e) and (4f), and finally, as in 462 to 465 in FIG.

The output of the selection signal generation circuit 426 is input to the NAND gate 432 and the oragate 434, and when this value passes through the oragate 436, the adder 430 as shown in FIG. The output of the decoded data is obtained by adding each output in units of pixels and pixels from the output of the multiplexer 428 and the output of the fourth memory 410. Can be.

FIG. 13 is a view showing another embodiment according to the present invention, in which a block-based process is performed.

A buffer 502 for blocking and storing input data in a predetermined range;

An average variance calculator 504 that averages and distributes the recorded values of the buffer 502 to calculate a smoothing or edge detection;

A smoothing processor 506 for processing a smoothing part according to the smoothing detection output of the average dispersion calculator 504 from the output of the buffer 502;

An edge processor 508 for processing an edge portion according to the edge detection output of the average dispersion calculator 504 at the output of the buffer 502;

A first data bit converter 510 for dividing the output constant bit of the smoothing processor 506 into upper and lower bits according to an energy distribution and converting the bit into a byte size;

A second data bit converter 512 for dividing an output constant bit of the edge processor 508 into upper and lower bits according to an energy distribution and converting the bit into a byte size;

Lossless coders 514 and 518 for encoding the energy-rich values in the first and second data bit converters 510 and 512 without loss by entropy coding;

Loss coders 516 and 520 that loss-encode low-energy low bits by entropy coding in the first and second data bit converters 510 and 512;

Lossless decoders / loss decoders 522 and 526 for lossless / lossy decoding the outputs of the lossless coders 514 and 518 and the lossy coders 516 and 520 with entropy coding;

Bit separators 530 and 532 for separating the decoded data of the lossless decoders 523 and 526 into a predetermined number of pixels;

The synthesizer 534 and 536 combine the outputs of the bit separators 530 and 532 with the outputs of the loss decoders 524 and 528.

Another embodiment of the present invention will be described in detail with reference to FIGS. 13 and 14.

The input image data of the image input terminal 501 is divided into n × n blocks (n: integers) and stored in the buffer 502. From the output of the buffer 502, the average dispersion calculator 504 detects edges and smoothing portions. When the average dispersion calculator 504 detects smoothing, the output of the buffer 502 is processed by the smoothing processing unit 506, and when the edge is detected, the edge part embedded in the buffer 502 is processed by the edge processing unit 508. do. In the output of the smoothing processor 506, the bit is divided into upper and lower bits by a predetermined bit according to the degree of energy inclusion, and then converted into an original one-byte unit. The upper bits, which contain a lot of energy from the values divided by the upper and lower bits divided by the first data bit converter 510, are encoded without loss by entropy coding in the lossless coder 514, and have a low energy amount. The bits are encoded in consideration of the loss so that there is no problem in the loss coder 516 in the entropy coding scheme for the output. The output data of the edge processor 508 is also divided into upper and lower bits, and is converted into the original one byte size by the second data bit converter 512, and then the data of the bits are lost by the lossless coder 518 in entropy coding. Encoding is performed without loss, and the lower bits, which contain less energy, are encoded in the loss coder 520 in consideration of some loss in the entropy coding scheme. The lossless decoders 514 and 518 and the lossy decoders 516 and 520 are decoded by the lossless decoders 522 and 526 and the lossy decoders 524 and 528. The data decoded by the lossless decoders 522 and 526 may be separated into original pixels by the bit separators 530 and 532, and may be synthesized by the outputs of the lossy decoders 524 and 528 and the synthesizers 534 and 536 to obtain decoded image data.

FIG. 15 is a detailed circuit diagram of FIG. 13 referred to in the practice of the present invention.

If there is pixel data blocked n × n (4 × 4) in the buffer 502, the average variance calculator 504 detects edges and smoothing areas for the image data.

When the edge is detected by the average dispersion calculator 504, the latch circuits 602 and 606 of the generation clocks CK0, CK1 and CK2 of the first clock generator 601 and the 4-bit shift register 604. And the adder 628.

Accordingly, the upper two bits of the eight bits of the output 1 byte (one pixel) of the buffer 502 are processed by the latch circuit 602, the 4-bit shift register 604, and the latch circuit 606, and the latch circuit 628 In the lossless coder 514, the lossless coder 514 is processed without loss, and the prefix providing unit 634 is provided to the lossless coder 514 and encoded without loss.

The specific circuits and the generated clock timing diagrams of the first clock generator 601 are shown in FIGS. 17 and 18.

The lower 6 bits of the pixel of the edge portion are written to the memory 608 so that its output is loss coded so that there is no problem even if there is some loss in the loss coder 516, and the prefix indicating the lower bit is a prefix provider 632 Is encoded by the loss coder 516. On the other hand, when the smoothing of the input image is detected by the average dispersion calculator 504, the clocks of the clock stages CK3 to CK7 generated by the second clock generator 603 are shifted by the latch circuits 610, 620, 622, and 624. The registers 612, 614, 616, and the adder 636 are configured to be input.

Accordingly, the most significant two bits with high energy in the latch circuits 610, 620, 622, and 624 and the 2-bit shift registers 612, 614, and 616 are added to the signal of the clock stage CK7 and output. The remaining six bits are then written to the buffer memory 618. The output data of the adder 636 is recorded in the buffer memory 638 and then coded without loss by the lossless coder 518, but using an entropy coding scheme and a prefix providing unit for prefix information indicating that it is higher information in the smoothing data. Provided at 639 and coded losslessly at lossless coder 518. On the other hand, the output of the buffer memory 618 is also coded in a state in which the loss coder 520 is lost to some extent, the prefix information indicating the low-bit information is provided from the prefix providing unit 640 in the loss coder 520 Is coded.

Specific circuits and clock timing diagrams of the second clock generator 603 are shown in detail in FIGS. 19 and 20.

16 is a detailed circuit diagram of FIG.

15 is inputted to the lossless decoders 522 and 518 and the lossy decoders 516 and 520 to the mark detector 650 at the same time as the outputs to the lossless decoders 522 and 526 and the lossy decoders 524 and 528. The control signal is generated in accordance with the lossless and is provided to the lossless decoders 522 and 526 and the loss decoders 524 and 528 for decoding.

The prefixes added during coding before decoding in the lossless decoders 522 and 526 and the loss decoders 524 and 528 are separated by the prefix remover 652, 654, 656, and 658, and the data having the separated prefixes is separated from the coder at each decoder. Decoded in reverse order by the same principle.

For example, in the case of edge implementation, the clock generated by the clock generator 755 is operated as the clock stages CLK0 to CLK2 as shown in FIGS. 17 and 18, and the lossless decoding is output decoded by the lossless decoder 522. Is written to the buffer 660, latched by the latch circuit 668 according to the signal of the clock terminal CLK0, and shifted 4 bits by the 4-bit shift register 670 according to the signal of the clock terminal CLK1. The latch circuit 672 selects and outputs the decoded data without loss from the multiplexer 690 in 4 bytes according to the output of the selection signal generator 692.

The data decoded in consideration of the loss in the loss decoder 524 and written to the buffer 662 is added to the output of the multiplexer 690 by the adder 694, which is output to the selection signal generator 692. Using the signal, an adder clock of the adder 694 is generated through the NAND gates 655 and the orifices 659 and 653, and is added and buffered in the tri-state buffer 696.

The clock generators 756 configured as shown in FIG. 23 and the clocks of clock stages CLK2 to CLK6 as shown in FIG. 24 are shifted for smoothing by decoding the smoothing region. 682, latch circuits 674, 678, 698, 680 and selection signal generator 669.

Decoded data deprecated by the decoding temporary prefix removing unit 656 without loss in the smoothing area decoding is written to the buffer 664, and the recorded value of the buffer 664 is read and latched by the latch circuit 674. The 2-bit shift registers 636, 684, and 682 are shifted by two bits to the clock stages CLK4, CLK5, and CLK6, and the latch circuits 678, 698, and 680 of the latch select signal generator 669 are shifted. The demultiplexer 653 is decoded by the multiplexer 653 according to the generated signal, and separated and output into 4 bytes according to the data.

The data decoded in consideration of the loss in the loss decoder 528 is buffered through the buffer 666 and input to the adder 667 as the output of the multiplexer 653, and the multiplexer 653 is a selection signal. The selector 667 is selected by the signals a and b generated by the generator 669, and the adder 667 is added according to the clock signals output through the NAND gate 665 and the oragate 661 and 663. That is, according to the subtraction clock, the output of the multiplexer 653 and the output of the buffer 666 are summed by the adder 667 to obtain a decoded output buffered by the tri-state buffer 671.

As described above, by using bit division, high-order bits having high energy may be losslessly coded and most of the low-order bits having low energy may be compressed by lossy coding to simultaneously realize high quality and compression.

Claims (8)

In a picture signal encoding / decoding device including a lossless coding unit 208, a lossy coding unit 201, a lossless decoding unit 212, and a lossy decoding unit 214, energy is input from the input 1-byte data of the image signal. The input data bit divider 202 which separates and outputs the upper and lower bits in order to separate a large portion, and the upper part which contains a lot of energy separated and output by the input data divider 202. The first bit converter 204 and the input data divider 202 separate the same pattern using the partial bits and convert the same pattern into 1-byte data having the original size and provide the same to the lossless coding unit 208. A second bit converter 206 for repeating the same pattern using low-order bits containing less energy and converting the same pattern into 1-byte data having an original size and providing the lossy coding unit 210 to the lossy coding unit 210; Combining the output of the bit-separator coding unit 208 with the same size by separating the output containing a large amount of energy into the original pixel data, and the output of the bit separator 216 and the loss decoding unit 214 And a device for decoding / decoding the image signal by bit division, characterized in that it comprises a synthesizer (218). 2. The input data bit divider 202 of claim 1 further comprises: a latch circuit 301 for latching and separating n bits from the top of all 1 bytes of data of the input terminal 201 and the input of the input terminal 201. The shift registers 303, 307 and 311 which latch the data in the latch circuit 301 and then increase by n + 2 from the bits and shift them in the order of input and separate output by n bits, and the outputs of the shift registers 303, 307 and 311. And a latch circuit (305, 309, 313) for latching the signal. The memory device of claim 1, wherein the first bit converter 204 includes an adder 317 for adding the outputs of the latch circuits 301, 303, 307, and 311, and a first memory 319 for writing the output of the adder 317. An apparatus for encoding and decoding an image signal by bit division, characterized by the above-mentioned. The video signal division by bit division according to claim 1, further comprising a first prefix providing unit 321 for adding information to the lossless coding unit 208 to distinguish lossless coding data. Decryption device. 2. The video signal by bit division according to claim 1, further comprising a second prefix providing unit 325 for adding information to the loss coding unit 210 to distinguish loss coding data. Decryption device. An image signal encoding / decoding method, comprising: a first process of separating input one-byte data of the image signal into upper and lower bits to separate a portion containing a large amount of energy, and energy separated from the input data The second process of converting the data into the one-byte data of the original size by using the higher part bits included in a large number, and increasing the probability of repeating the same pattern, and the lower bits containing low energy separated from the input data. A third process of converting 1-byte data of an original size using the third process to increase the probability of repeating the same pattern; and a fourth process of encoding the output of the second process with entropy coding to prevent loss. A fifth process of encoding the output of the third process with entropy coding and recognizing that there is a loss, and the losslessness of the fourth process A sixth process of losslessly decoding a coding output with entropy coding as in the coding; a seventh process of losslessly decoding the lossy coding output in the fifth process with entropy coding as in coding; and the lossless coded energy A seventh process of dividing a large amount of output into original pixel data to have the same size, and an eighth process of synthesizing the bit-separated value and the lossy decoding value of the seventh process. And decoding method of an image signal. Encoding / decoding of an image processing apparatus having a lossless / lossy coder 514,516,518,520 for lossless coding, and a lossless decoder / loss decoder 522,526,524,528 for lossless / lossy decoding the output of the lossless / lossy decoders 514,518,516,520 with entropy coding. An apparatus comprising: a buffer 502 for blocking and storing the image input data in a predetermined range, and an average dispersion calculator 504 for averaging and dispersing the recorded values of the buffer 502 to detect smoothing and edge portions. And a smoothing processor 506 for processing a smoothing portion according to the smoothing detection output of the average dispersion calculator 504 at the output of the buffer 502, and the average dispersion calculator at the output of the buffer 502. An edge processor 508 for processing an edge portion according to the edge detection output of 504, and a predetermined output bit of the smoothing processor 506 into upper and lower bits according to the energy-containing distribution. The first data bit converter 510 and the output data bits of the edge processor 508 are converted into upper and lower bits according to energy distribution. A second data bit converter 512 for converting the data into a byte size and providing it to the lossless / lossy coders 518 and 520, and a bit separator 530 for separating the decoded data of the lossless decoders 522 and 526 into a predetermined number of pixels. And 532, and a synthesizer (534, 536) for combining the outputs of the bit separators (530, 532) and the outputs of the lossy decoders (524, 528). A decoding / decoding method of an image processing apparatus, comprising: a first step of blocking and storing the image input data in a predetermined range; and a second step of detecting a smoothing part and an edge part by averaging and distributing the recording values of the first step. And a third step of processing a smoothing part according to the smoothing detection output of the second step at the output of the first step, and an edge part according to the edge detection output of the second step at the output of the first step. A fourth step of processing, a fifth step of dividing the output constant bit of the third step into upper and lower bits according to the distribution of energy into a byte size, and a lossless value containing a large amount of energy of the fifth step. A sixth step of encoding, a seventh step of loss encoding the low energy bits of the fifth step, and the lossless / lossy coding of the lossless coding and the lossy coding by entropy coding. And a tenth step of separating the decoded data of the eighth step into a predetermined number of pixels, and a tenth step of synthesizing the output and the lost decoding value of the ninth step. An encoding / decoding method of an image signal by bit division.