JPS62286279A - Charge transfer device - Google Patents

Abstract

PURPOSE:To decrease the area occupied by gate electrodes on the surface of a substrate and to improve sensitivity, by applying two-phase clock pulses to one-layer gate electrodes on the surface of the substrate and to the substrate, and transferring electric charge. CONSTITUTION:Electrodes 12 are formed on the upper part of an insulating layer 10 at regions I. The electrodes 12 are formed with polysilicon, used as gate electrodes for applying clock pulses for charge transfer and connected to a clock pulse source phi1. A substrate 2 is used as an electrode for applying clock pulses for the charge transfer and connected to a clock puse source phi2. Since the clock pulses phi1 and phi2 are applied to the gate electrodes 12 and the substrate 2 and the charge is transferred, only one-phase clock pulses are applied to the gate electrodes 12, which are provided on the surface of the substrate. Since the two-layer gate electrodes are not required on the surface of the substrate, the area occupied by the electrodes on the surface of the substrate is reduced, and sensitivity is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION 3. Detailed Description of the Invention Technical Field The present invention relates to a charge transfer device, and more particularly to a charge transfer device in which an inversion layer is included on the semiconductor surface of a portion of each cell, and the inversion layer acts as a virtual electrode. The present invention relates to a buried channel charge transfer device (COD) in which the cell region is protected from gate-induced potential changes.

BACKGROUND OF THE INVENTION Buried channel CODs involve storage and transfer of mobile charge within guided channels within thin semiconductor layers. In general surface-transfer type CCDs, a trapping effect usually occurs at the interface between oxide and silicon, but in buried channel type CCDs, this trapping effect can be prevented, thereby improving charge transfer efficiency. Furthermore, since carrier dispersion at the interface is eliminated, charge transfer efficiency is also improved. As a result, operation at a higher frequency than before is possible.

VP as such a buried channel type single phase CCU
-CCI) (Verticel phase cCn)
This means, for example, that each cell included in a multi-cell signal channel has four regions ll11111'7, into which impurities are implanted or diffused to an appropriate depth from the semiconductor surface. The impurity distribution of each is different. A gate electrode is provided on at least the upper surface of the region In, and the maximum potential generated in each region when the gate is on and when the gate is off is determined by the impurity distribution specific to each region.

An inversion layer is provided on the semiconductor surface of region II [1'V,
This inversion layer protects region IIIIV from changes in potential caused by the voltage applied to the gate electrode, and the potential does not change when the voltage applied to the gate electrode is turned on or off.

Therefore, by applying a single-phase clock signal to the gate electrode, the maximum potential value in region III is reduced to region ■
(2) Iteratively moves up and down based on the fixed potential maximum value. In both gate states, the maximum potential value of the region H is higher than that of the region H, and the maximum potential value of the region (2) is maintained higher than that of the region (2), so that the directionality of charge transfer can be obtained.

Since about half of the substrate surface of such a p-can is covered with a polysilicon gate electrode, it has a drawback of low sensitivity when used as a photosensitive section.

In addition, in order to easily set the impurity concentration of each region of the above-mentioned vp-ccn, 1, for example, each cell has three regions,
An inversion layer is formed in one region, and polysilicon gate electrodes are provided in each of the two regions where no inversion layer is formed, and charges are transferred by applying two-phase drive pulses to these gate electrodes. I can think of things. In a device in which two-phase gate electrodes are provided on the substrate surface in this manner, most of the substrate surface is covered with the polysilicon electrode, which has the disadvantage that the sensitivity is particularly reduced.

OBJECTS It is an object of the present invention to overcome the drawbacks of the prior art and to provide a buried channel charge transfer device with good sensitivity.

DISCLOSURE OF THE INVENTION According to the present invention, a semiconductor substrate of one conductivity type has a buried channel including a plurality of cells on one main surface thereof, and an inversion layer formed on a portion of the semiconductor surface of each cell allows a gate A charge transfer device in which a portion of each cell is selectively protected from potential changes due to induction is formed by forming a well on the main surface of a semiconductor substrate with a conductivity type opposite to that of the substrate; A buried channel including a plurality of cells is formed, and a gate electrode is formed on a portion of the surface of each cell where an inversion layer is not formed.

The shape of the inversion layer is such that the well has a different thickness in some parts thereof, and two-phase driving pulses are applied to the gate electrode and the substrate to transfer charge.

DESCRIPTION OF EMBODIMENTS Embodiments of a charge transfer device according to the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 shows a cross section in the channel direction of an embodiment of the charge transfer differential according to the present invention.

A p-type well 4 is formed on an n-type silicon substrate 2, and an n-type region 6 formed in the p-type well 4 allows n-type CCrJ to be formed.
A channel is formed. A plurality of cells are separated from each other and extend in the longitudinal direction of the channel, and each cell has three regions I■■. In the n-type head region B forming the n-type channel, a predetermined amount of impurity is implanted in each of the three regions IUm. P-type well 4 is formed shallower in region (2) than in region IDI.

Further, in the region m, a P-type head region 8 is formed above the n-type region 6. This p-type head region 8 is region ll111
It acts as a virtual electrode that has a shielding effect to prevent potential changes due to gate induction. p
The thickness of the mold head region 8 is 0.315 to 0.7 pm, preferably 0.
．． 2 to 0.4 gm.

The upper part of the P-type head area 8 in area ■■ and the n-type area 8 in area engineering
An insulated I& layer 10 of S + 02 is formed on top of the .

An electrode 12 is formed on the insulating layer 10 in the region 1 . In this embodiment, the electrode 12 is made of polysilicon, is used as a gate electrode for applying a clock pulse for charge transfer, and is connected to a clock pulse source φ1.

In this embodiment, the substrate 2 is used as an electrode for applying clock pulses for charge transfer, and is connected to a clock pulse source φ.
Connected to 2.

Therefore, two-phase clock pulses are applied to the electrode 12 and the substrate 2, thereby transferring charge. P-type well 4 is grounded.

The doping density of the substrate 2 is l! 10 ~1x1.01
6/C113. Further, the upper surface of each cell is covered with a passivation film (not shown) formed of PSG or the like.

The potential of the region I11[[ of the n-type channel 8 when no clock pulse is applied is shown in FIGS. 2(a) to 2(C).

The upper limit of the potential of the n-type channel 6 in region (2) is determined by the amount of implanted donor impurity and is fixed. On the other hand, the upper limit of the potential of the n-type channel 6 in the region I is determined by the gate potential due to the clock pulse φ1 applied to the electrode 12 and the amount of implanted donor impurity, and is variable. Further, the upper limit value of the potential of the n-type channel 6 in the region n is also determined by the gate potential due to the clock pulse φ2 applied to the substrate 2 and the amount of the implanted donor impurity, and is variable.

Charges are transferred in the direction of the arrow in FIG. 1 by the three potentials in these three regions.

FIG. 3 shows a timing chart of voltages applied from clock pulse sources φ1 and φ2.

FIGS. 4(a) to (c) show times t1 and t2 in FIG.
, t3, the maximum potential value φ layer aX of each region is represented by a stepped pattern of potential wells.

At time t1, clock pulse sources φ1 and φ2
No voltage is applied from any of them.

At this time, the potential pattern of each region is determined by the impurity concentration implanted into the n-type channel 6 of each region, and as shown in FIG. , and area ■ is at the lowest level.

At time t2, a high-level voltage Vg is applied from the clock pulse source φ1, and no voltage is applied from the clock pulse source φ2. Therefore, the potential of the region 1 decreases due to the voltage Vg applied to the electrode 12. As shown in Figure 4(b), the pattern of potential in each region is 3, starting from region ■ and descending to the right.
It has a step potential pattern, with region I being the lowest level.

At time t3, a high-level voltage Vg is applied from the clock pulse source φ1, and a voltage Vsub is applied from the clock pulse source φ2. Therefore, compared to time t2, by applying the voltage Vsub to the substrate 2, the voltage Vsub is applied to the region (2) through the shallow portion of the p-type well 4, and the potential of the region II is lowered. Therefore, as shown in FIG. 4(C), the potential pattern of each region starts from region T and descends to the right to become a three-stage potential pattern, with region (2) being at the lowest level.

Incidentally, at any time from t1 to 70, the potential level of area (2) is maintained at V (2).

For example, considering the signal charge accumulated in region m,
At time t1, the potential of region m is the lowest, so at time t2, when the signal charge is confined in region (2), the potential of region m becomes low. At this time, since the region m is shielded from the gate potential by the inversion layer of the p-type region 8, the potential does not change.

At this point, the potential of the region is lower than that of the region (2), so the charge accumulated in the region m moves to the region.

At time t3, voltage Vsub is applied to substrate 2, so the potential of region H becomes low. At this time, since the p-type well 4 is formed deeply in the region DII, the voltage Vsub from the substrate 2 is not applied, so the potential does not change.At this point, the potential of the region (2) becomes lower than that of the region I. Charges in the region move to region H.

According to this embodiment, since the clock pulses φl and φ2 are applied to the gate electrode 12 and the substrate 2 to transfer charges,
The gate electrode 12 provided on the substrate surface only needs to be one that applies a one-phase clock pulse.

Therefore, in a device that transfers charges by applying two-phase clock pulses to two-phase gate electrodes, two-phase clock pulses are applied to two-phase gate electrodes to transfer charges.
Since there is no need to provide a layer gate electrode, the area occupied by the electrode on the substrate surface is reduced and sensitivity is improved.

Note that the impurity concentration of the n-type channel 6 and the p-type well 4
What is necessary is to change the depth of the gate electrode 12 and the magnitude of the voltage Vg applied to the gate electrode 12 and the voltage Vsub applied to the substrate 2 accordingly.

FIG. 5 shows a cross section in the channel direction of another embodiment of a charge transfer device according to the invention.

In this embodiment, the p-type well 4 is formed deeper in region (2) than in region III. The rest of the configuration is the same as the embodiment shown in FIG. 1, so the explanation will be omitted.

In this embodiment as well, two-phase clock pulses φ1. φ2 is applied, thereby transferring charge.

The potential of the region llTm of the n-type channel 6 when no clock pulse is applied is shown in FIGS. 6(a) to 6(C).

The upper limit value of the potential of the n-type channel 8 in region (3) is determined by the amount of implanted donor impurity and is fixed. On the other hand, the upper limit of the potential of the n-type channel 6 in the region processing is determined by the gate potential due to the clock pulse φ1 applied to the electrode 12 and the clock pulse φ2 applied to the substrate 2, and the amount of implanted donor impurity. and is variable. Further, the upper limit value of the potential of the n-type channel 6 in the region m is also determined by the gate potential due to the clock pulse φ2 applied to the substrate 2 and the amount of the implanted donor impurity, and is variable. Charge is transferred in the direction of the arrow in FIG. 5 by the three button seals in these three areas.

FIG. 7 shows the timing chart of the voltages applied to the clock pulse sources φ1 and φ2, and FIGS. 8 (21) to (
In c), the maximum value φWaX of the potential in each region at each of times t1, t2, and t3 in FIG. 7 is represented by a stepped pattern of potential wells.

At time t1, clock pulse sources φl and φ2
No voltage is applied from any of them.

At this time, the potential pattern of each region is determined by the impurity concentration implanted into the n-channel 6 of each region as shown in FIG.
As shown in a), there is a three-stage potential pattern that starts at area m and goes down to the right, and area ■
is at its lowest level.

At time t2, no voltage is applied from clock pulse source φ1, and voltage Vsu is applied from clock pulse source φ2.
b is applied. Therefore, by applying the voltage V+ub to the substrate 2, the voltage Vsub is applied to the region III through the shallow portion of the P-type well 4, and the potential of the region III is lowered.

In this case, the potential of area ■ will drop significantly, but the potential of area engineering will only drop slightly. As a result, the pattern of potential in each region is as shown in Figure 8 (
As shown in b), there is a three-stage potential pattern starting from region I and going down to the right, and region m
becomes the lowest level.

At time t3, a high level voltage 1/g is applied from clock pulse source φ1, and clock pulse source φ2
A voltage Vsub is applied from. Therefore, compared to time t2, the voltage Vg is applied to the electrode 12, thereby lowering the potential of the area. Therefore, the pattern of potential in each region is as shown in Fig. 8(C).
As shown in FIG. 2, a three-stage potential pattern starts from region (2) and moves down to the right, with region I being the lowest level.

Note that the potential level of region (2) is maintained at VmlI at any time from tl to t3.

For example, considering the signal charge accumulated in region ■,
At time tl, the potential in region H is the lowest, so the signal charge is confined in region H. At time t2, the potential of region (2) becomes low. At this time, the potential of area engineering decreases slightly, but it is still higher than area ■, and in area ■, p
Since the mold well 4 is formed deeply, the voltage Vsub from the substrate 2 is not applied, so the potential does not change. At this point, the potential of region (2) becomes lower than that of region (2), so the charges accumulated in region (2) move to region (2).

At time t3, voltage Vg is applied to electrode 12, so the potential in region 1 becomes low. Since the region ■■ is shielded from the gate potential by the inversion layer of the p-type region 8, the potential does not change.At this point, the potential of the region ■ becomes lower than that of the region ■, so the charge in the region Move to.

In this embodiment as well, since the charge is transferred by applying a clock pulse to the gate electrode 12 and the substrate 2, the gate electrode 12 provided on the surface of the substrate only needs to be one that applies an l-phase clock pulse. Therefore, the area occupied by the electrodes on the substrate surface is reduced, and the sensitivity is improved.

In this embodiment as well, the impurity concentration of the n-type channel 6 and the depth of the p-type well 4 are changed, and the voltage V3 applied to the gate electrode 12 and the voltage Vsub applied to the substrate 2 are changed accordingly. Just change the size.

FIG. 9 shows a cross section in the channel direction of yet another embodiment of the charge transfer device according to the present invention.

In this embodiment, the n-type channel 6 is formed deeper in region H than in region Im. Further, as a result, the p-type well 4 is formed thinner in the region (2) than in the region I[. The rest of the configuration is the same as the embodiment shown in FIG. 1, so the explanation will be omitted.

The potential in each region of this example when no voltage is applied is the same as in FIGS. 2(a) to (C), and the timing chart of the voltages applied from the clock pulse sources φ1 and φ2 is the same as in FIG. 3. Yes, at times t1 and t2 in Figure 3
, t3 are shown in FIGS. 10(a) to 10(g).

First, an n-type single crystal silicon substrate 2 with a doping density of 2 x 1015/cm3 as shown in FIG. 10(a) is used. An insulating layer 10 of SiO2 is formed on the surface of the n-type substrate 2 to a desired thickness, for example, 300 angstroms, by an oxidation method.

Next, as shown in FIG. 10(a), boron (B) is introduced through the insulating layer 10 at an energy of 200 keV and a dose of 2 x 1.
0''/c112. This forms the p-type well 4 portion in region H.

Next, as shown in FIG. 10(b), a photoresist 20 is formed on the insulating layer 10 with an opening in region III, and boron (B) is applied through the insulating layer 10 at an energy of 200 keV and a dose of 2. Drive with K 1012/cm2.

By this implantation and the implantation in FIG. 10(a), the area m
A p-type well 4 of I is formed.

Next, as shown in FIG.
, with a dose of 2 x to12/am2, which forms the n-channel 6 portion of region I.

Furthermore, as shown in FIG. 10(d), a photoresist 22 is formed so as to open the region m, and phosphorus (P) or arsenic (As) is applied through the insulating layer IO at an energy of 200 keV and a dose of 2. ! 10 12 /cm 2 , which forms the n-channel 6 portion of region H.

Furthermore, as shown in FIG. 10(e), a photoresist 24 is formed so as to open the area m, and the insulating layer 1
Phosphorus (P) or arsenic (As) is implanted through 0 at an energy of 200 ksV and a dose of 2 x 1012/cm2. As a result, the n-channel 6 portion of region (2) is formed. By these implantations, the potential of region III becomes as shown in FIG. 4(a) when no voltage is applied.

Further, a polycrystalline silicon layer is formed on the insulating layer 10 and plasma etched using a photoresist (not shown) to form a gate electrode 12 as shown in FIG. 10(f).

Next, as shown in FIG. 10(g), using the gate electrode 12 as a mask with openings in the regions ■■, boron (B) is applied at an energy of 40 keV through the insulating layer IO.
Inject a dose of 1 x 1013/cvs2. The p-type head region 8, which becomes the virtual electrode of the region (■■), is formed by the metal implantation.

In this way, the charge transfer device shown in FIG. 1 is manufactured. Note that heat treatment is performed after implanting each impurity, and the implanted impurities are diffused to an appropriate depth in the silicon to form a correct potential distribution state.

An example of the manufacturing process of the charge transfer device shown in FIG.
1 (a) to (g).

First, an n-type single crystal silicon substrate 2 with a doping density of 2 x LO15/cya3 as shown in FIG. 11(a) is used. An insulating layer IO of Si02 is formed on the surface of this n-type substrate 2 to a desired thickness, for example, 300 angstroms, by an oxidation method.

Next, as shown in FIG. 11(a), boron (B) is introduced through the insulating layer 10 at an energy of 200 keV and a dose of 2 x 1.
Type in 012/cm2. As a result, a p-well 4 portion in region III is formed.

Next, as shown in FIG. 11(b), phosphorus (CP) or arsenic (As) is introduced through the insulating filO at an energy of 200
keV with a dose of 2.times.10@12 /c@-, this implant forms 6 parts of the n-channel in region (1).

Furthermore, as shown in FIG. 11(C), a photoresist 26 is formed so as to open the region In, and phosphorus (P) or arsenic (As) is applied through the insulating layer IO at an energy of 200 keV and a dose of 2×10 12 / Enter c112. This forms the n-channel 8 portion of region I.

Roughly, as shown in FIG. 11(d), the photoresist 28 is formed so as to open the area H, and the insulating layer 1
0 through phosphorus CP) or arsenic (As) at an energy of 200 keV and a dose of 2! Enter 1012/am2. As a result, the n-channel 6 portion of region H is formed. By these implantations, the potential of region III becomes as shown in FIG. 8(a) when no voltage is applied.

Next, a polycrystalline silicon layer is formed on the insulating layer 10 and plasma etched using a photoresist (not shown).
A gate electrode 12 is formed as shown in FIG. 11(e).

Furthermore, as shown in FIG. 11(f), a photoresist 30 is formed on the insulating layer 10 and the gate electrode 12 so as to open the region H, and boron (B) is applied through the insulating layer 10 at an energy of 400 keV. Dose 2 x IQ12
Type /cts2. This input and Figure 11(a)
A p-type well 4 in region (2) is formed by implanting.

Furthermore, as shown in FIG. 11(g), the photoresist 3
0 is removed, and using the gate electrode 12 as a mask with openings in the region
B) with an energy of 40 kaV and a dose of 1 x 1012/
Type in ClI2. By this implantation, the P region 8 which becomes the virtual electrode of the region (■) is formed.

In this way, the charge transfer device shown in FIG. 5 is manufactured. Note that heat treatment is performed after each impurity is implanted, and the implanted impurities are diffused into the silicon to an appropriate depth to form a correct potential distribution shape 7JJ.

An example of the manufacturing process of the charge transfer device shown in FIG.
2 (a) to (f).

First, an n-type single crystal silicon substrate 2 with a doping density of 2 x 1015/cm3 as shown in FIG. 12(a) is used. An insulating layer 10 of S + 02 is formed on the surface of the n-type substrate 2 to a desired thickness, for example, 3.
00 angstroms.

Next, as shown in FIG. 12(a), boron (B) was injected through the insulating layer lO at an energy of 200 keV and a dose of 2 x 1.
Type in 012/C112, this will move you to area III.
4 portions of the p-type well are formed.

Next, as shown in FIG. 12(b), phosphorus (P) or arsenic (AS) is introduced through the insulating layer 10 at an energy of 200k.
eV, dose 2! Enter 1012/cm2. The n-channel 6 portion of the region is formed by implantation.

Roughly, as shown in FIG. 12(C), the photoresist 24 is formed so as to have an opening in the region (2), and the insulating layer 1 is
Phosphorus (P) or arsenic (As) is implanted through 0 at an energy of 200 keV and a dose of 2 x 1012/clI2, thereby forming 6 portions of the n-channel in region (2).

Next, a polycrystalline silicon layer is formed on the insulating layer 10 and plasma etched using a photoresist (not shown).
A gate electrode 12 is formed as shown in FIG. 12(d).

Furthermore, as shown in FIG. 12 (14), a photoresist 30 is formed on the insulating layer 10 and the gate electrode 12 so as to open the region H, and phosphorus (P) or arsenic (Ar) is passed through the insulating layer 10. ) with an energy of 400 keV and a line [2! 1012/cm2, and by this implantation and the implantation shown in FIG. 12(b), the n-channel 8 in area ■
is formed deeper than region III. As a result, the potential of the region In[I is shown in Fig. 4 (
The potential is as shown in a).

Furthermore, as shown in FIG. 12D), a photoresist 30
The boron CB is removed through the insulating layer 10 using the gate electrode 12 as a mask with openings in the region
) with energy 40 kaV, line i1 x 1012/C
Type in layer 2. By this implantation, a p-type head region 8 is formed which becomes a virtual electrode in the region (■).

In this way, the charge transfer device shown in FIG. 9 is manufactured. Note that heat treatment is performed after implanting each impurity, and the implanted impurities are diffused to an appropriate depth in the silicon to form a correct potential distribution state.

In any of the above embodiments, when a p-channel CCD is manufactured using an n-type silicon substrate, the polarities may be reversed. In addition, ■-■, II-I such as indium antimonide and mercury cadmium telluride
Semiconductors containing V compounds may also be used.

Effects According to the present invention, since charges are transferred by applying two-phase clock pulses to one layer of gate electrodes on the substrate surface and the substrate, only one layer of gate electrodes is required on the substrate surface. Since the area occupied by the gate electrode is small, a charge transfer device with high sensitivity can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing an embodiment of the charge transfer device according to the present invention, and FIGS. 2(a) to (C) are diagrams showing the potential of the region In[111 of the device shown in FIG. 1 when no voltage is applied. , FIG. 3 is a timing chart showing an example of the voltages applied to the clock pulse sources φl and φ2 of the device in FIG. 1, and FIG. 4(a) shows the potential state of the region In■ at time t1 in FIG. 3. The graph, Figure 4 ('0) is the area In■ at time t2 in Figure 3.
FIG. 4(c) is a graph showing the potential state of region r at time t3 in FIG. 3. FIG. 5 is a cross section showing another embodiment of the charge transfer device according to the present invention. 6(a) to 6(c) are diagrams showing the potential of region III of the device in FIG. 5 when no voltage is applied, and FIG. 7 is a diagram showing the potential in region III when no voltage is applied to the device in FIG. 5. FIG. 8(a) is a timing chart showing an example of the voltage in the region III■ at time tl in FIG.
FIG. 8(b) is a graph showing the potential state of region In■ at time t2 in FIG. 7. FIG. 8(C) is a graph showing the potential state of region In■ at time t3 in FIG.
9 is a cross-sectional view showing another embodiment of the charge transfer device according to the present invention, and FIGS. 10(a) to (g) show the manufacturing process of the charge transfer device shown in FIG. 1. 11(a) to (g) are diagrams showing the manufacturing process of the charge transfer device shown in FIG. 5, and FIGS. 12(a) to (f) are diagrams showing the manufacturing process of the charge transfer device shown in FIG. 9. It is a figure showing a process. Explanation of part symbols 2: Substrate 4, P-type well 8, N-type region 8, P-type region 10, Insulating layer 12, Gate electrode φ1 ．． φ2. Clock pulse source patent applicant Fuji Photo Film Co., Ltd. Agent Takao Katori Takao Maruyama Figure 1 Figure 3 Figure 2 I I -I I I
I leaning castle 11 engineering I I
■18 Figure 8 Figure 7 No changes to the contents of the drawing) Figure 8 I I 4 I I I Frog 1 1 I
I I III-a Figure 9 Figure 10 Figure 11 Figure 12 B Procedural amendment (method) % formula % ■, Indication of case 1985 Patent Application No. 129129 2, Title of invention Charge transfer device 3, Relationship with the case of the person making the amendment Patent applicant address 210 Nakanuma, Minamiashigara City, Kanagawa Prefecture Name (5)
20) Fuji Photo Film Co., Ltd. 4. Address of agent: 2-4-1 Nishi-Shinbashi, Minato-ku, Tokyo 105 5. Date of amendment order: August 6, 1985 (Shipping date: August 26, 1986)
6. Target of correction (1) Figure tfE ””“□
7. Contents of amendment (1) Figures 4, 6 and 8 of the drawings attached to the application
The figures will be replaced with the replacement drawings attached to this written amendment. 8. List of attached documents

Claims (1)

[Claims] 1. A buried channel including a plurality of cells is provided on one main surface of a semiconductor substrate of one conductivity type, and an inversion layer formed on the semiconductor surface of a part of each cell allows gate In a charge transfer device in which a portion of each cell is selectively protected from induced potential changes, the device comprises: forming a well on one major surface of the semiconductor substrate with a conductivity type opposite to that of the substrate; forming a buried channel including the plurality of cells of opposite conductivity type to the well, forming a gate electrode on a portion of the surface of each cell where the inversion layer is not formed; A charge transfer device, wherein the well has a different thickness in a part of the well, and charges are transferred by applying two-phase drive pulses to the gate electrode and the substrate. 2. The charge transfer device according to claim 1, wherein the well is formed shallowly in a part of the portion where the inversion layer is formed. 3. The charge transfer device according to claim 1, wherein the well is formed deeply in a part of the portion where the inversion layer is formed. 4. The device according to claim 1, wherein the buried channel is formed deeply in a part of the part where the inversion layer is formed, and the well is formed thinly in this part. charge transfer device. 5. In the device according to any one of claims 1 to 4, the semiconductor substrate is n-type silicon, the well is a p-type well, and the buried channel exhibits n-type conductivity. A charge transfer device featuring: