JPH0722610A - Electric charge transfer apparatus and its manufacture - Google Patents

Abstract

PURPOSE:To increase a handling electric charge amount without deteriorating transmission efficiency, and also readily control and stabilize the potential, and further readily realize in a process and sufficiently scope with a lower voltage. CONSTITUTION:An electric charge transfer apparatus comprises a substrate 1; an embedded channel region 3 formed in this substrate 1; and a gate insulating film 2 formed in the substrate 1, and a peak value of an impurity concentration distribution of the embedded channel is set to be within the substrate 1. In a method of manufacturing the electric charge transfer apparatus, after a gate insulating film 2 is formed in the substrate 1, an embedded channel is formed within the substrate 1 by ion implantation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge transfer device applied to a solid-state image pickup device or the like.

[0002]

2. Description of the Related Art In a conventional charge transfer device, as shown in FIG. 3A, a P-type substrate 41 having an N-type region 43 forming a buried channel CCD (hereinafter referred to as BCCD) is formed.
Then, after forming the gate insulating film 42, the polysilicon electrode 44 to be an electrode is selectively formed.

This charge transfer device completely depletes the N-type region 43 by completely eliminating the electrons in the N-type region 43, and the potential 46 is generated in the potential depression 45 shown in FIG. The electrons of the signal charge are accumulated so that The charges are transferred by applying a voltage V _G to the polysilicon electrode 44 and providing a potential difference between adjacent electrodes.

In manufacturing the charge transfer device, N
The shaped region 43 is formed by selectively introducing one or both of N-type impurities such as phosphorus and arsenic into the P-type substrate 41 by ion implantation. The condition of the ion implantation is 50
The acceleration voltage is about 100 KeV and the dose is 1 to 5E12 cm ^-2 , and the impurity concentration distribution is shown in FIG. 47 is the distribution of the N-type region 43, and 48 is the signal charge distribution.

[0005]

According to this conventional example, the peak of the impurity concentration distribution of the buried channel is the P-type substrate 41.
Since it is not within the range, the signal charge is less accumulated and the transfer efficiency is deteriorated, so that there is a drawback that the amount of charge handled is reduced. Although this conventional example is easy to manufacture, it has a drawback that it is difficult to control and stabilize the potential. That is, the factor that determines the potential is the gate insulating film 4
The film thickness is 2 and the impurity distribution 47 in the N-type region 43. If these changes, the potential changes. For example, if the gate insulating film 42 becomes thicker, the potential becomes deeper, and the impurity concentration in the N-type region 43 becomes higher. , Or the potential becomes deeper even if the diffusion length becomes longer.

However, the controllability of the film thickness of the gate insulating film 2 is about ± 5% with respect to the center, and if the center is 100 nm, the variation is 10%, which is 10%, so that the potential fluctuation is about 1 V or more. . In addition, the gate insulating film 4
Since the control of the film thickness of 2 is performed by adjusting the processing time, the thermal history at the time of forming the gate insulating film 42 directly affects the distribution of impurities in the N-type region 43, which further increases the variation in potential.

Therefore, the object of the present invention is to solve the above-mentioned drawbacks of the prior art, to increase the amount of charge handled without deteriorating the transfer efficiency, and to easily control and stabilize the potential, and to realize it in the process. It is an object of the present invention to provide a charge transfer device and a method for manufacturing the same, which are easy to operate and can sufficiently cope with a reduction in voltage.

[0008]

According to another aspect of the present invention, there is provided a charge transfer device including a substrate, a buried channel region formed on the substrate, and a gate insulating film formed on a surface of the substrate. It is characterized in that the peak value of the concentration distribution is inside the substrate.

A second aspect of the present invention is the charge transfer device according to the first aspect, wherein the gate insulating film has a three-layer structure including an oxide film, a nitride film and an oxide film in the order of stacking. According to a third aspect of the present invention, there is provided a method of manufacturing a charge transfer device, which comprises forming a gate insulating film on a substrate and then implanting ions to form a buried channel in the substrate.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a charge transfer device according to the third aspect, wherein the gate insulating film comprises an oxide film, a nitride film and an oxide film in the order of stacking, and the first oxide film and the nitride film are sequentially formed on the substrate. Ion implantation after stacking,
After that, an oxide film is formed on the nitride film.

[0011]

According to the charge transfer device of the first aspect, since the peak value of the impurity concentration distribution of the buried channel is inside the substrate, the center of the signal charge distribution coincides with the impurity concentration distribution even if the charge increases. Therefore, the accumulation of signal charges is effectively kept inside the substrate, and the amount of charges to be handled can be increased without deteriorating the transfer efficiency. In addition, since it is possible to increase both the amount of signal charges accumulated and the transfer efficiency, it is possible to cope with miniaturization and increase the dark current suppressing capability.

According to a second aspect of the charge transfer device of the present invention, in the first aspect, the gate insulating film has a three-layer structure including an oxide film, a nitride film and an oxide film in the order of lamination. In addition to the above action, it is possible to prevent the oxidation of the substrate. According to the method of manufacturing the charge transfer device of claim 3,
Since the buried channel is formed in the substrate by implanting ions after forming the gate insulating film on the substrate, the thermal history at the time of forming the gate insulating film does not affect the impurity concentration distribution and the impurity concentration in the buried channel region is increased. The depth of the distribution has a negative correlation with the thickness of the gate insulating film, and it is possible to self-control the fluctuation of the potential due to the fluctuation of the manufacturing process, so that the potential can be kept constant and stabilized. It is possible to reduce the voltage. Further, the peak position of the impurity concentration of the buried channel can be determined with good controllability by the acceleration voltage, and since it is formed inside the substrate, there is the same effect as in claim 1.

According to a fourth aspect of the present invention, there is provided the method of manufacturing a charge transfer device according to the third aspect, wherein the gate insulating film comprises an oxide film, a nitride film and an oxide film in the order of stacking, and the first oxide film and the nitride film are sequentially formed. Since ion implantation is performed after stacking on the substrate, and then an oxide film is formed on the nitride film, the nitride film is used for the enhanced diffusion due to the oxidation during the formation of the oxide film after the ion implantation, in addition to the function of claim 3. Since it is suppressed, the impurity concentration distribution during ion implantation is kept substantially constant.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. That is, this charge transfer device is provided with the substrate 1
And a buried channel region 3 formed inside the substrate 1, and a gate insulating film 2 formed on the surface of the substrate 1. The gate insulating film 2 has a three-layer structure including an oxide film 2a having a silicon oxide film as an embodiment, a nitride film 2b having a silicon nitride film as an embodiment, and an oxide film 2c having a silicon oxide film as an embodiment in the order of stacking. .

The peak value of the impurity concentration distribution of the buried channel region 3 is located inside the substrate 1 as shown in FIG. 1 (b). In this figure, 5 is the impurity concentration distribution,
6 is a distribution in the substrate 1 other than the buried channel region 3, and 7 is a signal charge distribution. Further, FIG. 1C is a potential distribution, 8 is a potential distribution when there is no signal charge, and 9 is a potential distribution when there is signal charge. Note that V _G is a voltage applied at the time of transferring charges.

Next, in the method of manufacturing the charge transfer device, after the gate insulating film 2 is formed on the substrate 1, ion implantation is performed to form the buried channel 1 in the substrate 1. That is, first, the gate insulating film 2 is formed on the P-type substrate 1.
After forming the oxide film 2a and the nitride film 2b that form the N, a phosphorus ion is selectively ion-implanted at an acceleration voltage of 160 KeV and a dose amount of 2E12 cm ⁻² to form an N-type region forming the buried channel region 3, Further, after forming the oxide film 2c of the gate insulating film 2, the polysilicon electrode 4 is selectively formed.

According to this embodiment, the gate insulation is provided on the substrate 1.
After the film 2 is formed, ions are implanted into the substrate 1
Since the buried channel is formed in the gate insulating film 2
The thermal history during the formation of the impurities does not affect the impurity concentration distribution
And the impurity concentration distribution in the buried channel region 3
Has a negative correlation with the thickness of the gate insulating film 2.
Like That is, (a in FIG.₁), (B₁) Is
The charge transfer devices having different thicknesses of the gate insulating film 2 were compared.
Of. Then, in FIG.₂) Is (a₁) Device
Pure substance concentration distribution map, (a₃) Is (a₁) Device signal charge
Distribution diagram in the state without₂) Is (b₁)
Concentration distribution diagram of the equipment of (b)₃) Is (b₁) Equipment
FIG. 6 is a potential distribution diagram in a state in which there is no signal charge. Figure
2 of (b ₁), The thickness of the insulating film 2 is (a₁) To
If it is thicker, the buried channel region 3 is formed shallower.
2 (a₁) If the insulating film 2 is thin,
The channel region 3 is deeply formed. Therefore, Ion
Important for CCD characteristics when the accelerating voltage for injection is constant
The potential of the gate insulating film 2 is (b₁) Like thick
It becomes deeper as it gets deeper, but the buried channel region 3 becomes shallower
If this happens, the potential will be shallower and will be canceled out.
(B₃)become that way. On the contrary, the gate insulating film 2
(A ₁When it is thin like), the potential becomes shallow
However, since the buried channel region 3 becomes deep,
This is offset by the fact that₃) Like
Figure (a₃), (B₃) Voltage of each potential distribution
αV and βV are α≈β.

As described above, even if the gate insulating film 2 fluctuates due to fluctuations in the manufacturing process, fluctuations in the potential are suppressed in a self-controlled manner, so that the potential can be kept constant and stabilized. Therefore, it is possible to further reduce the voltage. Further, as shown in the impurity concentration distribution of FIG. 1, a buried channel region 3 having a concentration peak is obtained at a position deeper than the interface between the gate insulating film 2 and the substrate 1 (eg, about 0.1 μm). This peak position can be determined with good controllability by the acceleration voltage. Since the peak position of the impurity concentration of the buried channel is formed inside the substrate 1 as described above, the center of the signal charge distribution coincides with the impurity concentration distribution even if the charge increases, as shown in FIG. To do. Therefore, since the accumulation of signal charges is effectively kept inside the substrate, it is possible to increase the signal amount at which the transfer efficiency begins to deteriorate as compared with the conventional example, and the handled charge amount is increased without deteriorating the transfer efficiency. Since it is possible to achieve both the increase in the amount of signal charges accumulated and the transfer efficiency, it is possible to cope with the miniaturization of the CCD.

Further, since this charge transfer device can reduce the N-type impurity concentration at the interface between the gate insulating film 2 and the substrate 1 as compared with the conventional structure, the pinning phenomenon (interface) which occurs when the voltage applied to the gate electrode is in the negative direction. When the potential at the point becomes the same as the P-type potential of the channel stopper, the supply of holes starts and the potential of the interface is fixed and the profile of the channel potential is also fixed even if the gate voltage is made negative). And the effect of reducing dark current increases.

Further, in the manufacturing process, the oxide film 2a and the nitride film 2b are sequentially laminated on the substrate 1, phosphorus ions are implanted, and then the oxide film 2c is formed on the nitride film 2b. Therefore, even if the step of forming an oxide film after the ion implantation is performed, the enhanced diffusion due to the oxidation is suppressed by the nitride film 2b, so that the impurity concentration distribution during the ion implantation is kept substantially constant, and the substrate 1 Oxidation is prevented.

Also, when the P-type region forming the channel stopper is formed by ion implantation after the gate insulating film 2 is formed, the heat treatment is reduced as compared with the conventional case and the lateral diffusion of the P-type region of the channel stopper is suppressed. And effective C
Since the CD channel width increases, the amount of charge handled increases. In the present invention, the acceleration voltage at the time of ion implantation may be 100 to 300 KeV.

[0022]

According to the charge transfer device of the first aspect, since the peak value of the impurity concentration distribution of the buried channel is inside the substrate, the center of the signal charge distribution is the impurity concentration distribution even if the charge increases. Since they coincide with each other, the accumulation of signal charges is effectively kept inside the substrate, and the amount of charges to be handled can be increased without deteriorating the transfer efficiency. Moreover, since it is possible to increase both the amount of signal charges accumulated and the transfer efficiency, it is possible to cope with miniaturization and to increase the dark current suppressing capability.

According to the charge transfer device of claim 2, in claim 1, the gate insulating film has a three-layer structure including an oxide film, a nitride film, and an oxide film in the order of stacking. In addition to the above effect, the oxidation of the substrate can be prevented. According to the method of manufacturing the charge transfer device of claim 3,
Since the buried channel is formed in the substrate by implanting ions after forming the gate insulating film on the substrate, the thermal history at the time of forming the gate insulating film does not affect the impurity concentration distribution and the impurity concentration in the buried channel region is increased. The depth of the distribution has a negative correlation with the thickness of the gate insulating film, and it is possible to self-control the fluctuation of the potential due to the fluctuation of the manufacturing process, so that the potential can be kept constant and stabilized. It is possible to reduce the voltage. Further, the peak position of the impurity concentration of the buried channel can be determined with good controllability by the accelerating voltage, and since it is formed inside the substrate, it has the same effect as claim 1.

According to the manufacturing method of the charge transfer device of claim 4, in claim 3, the gate insulating film comprises an oxide film, a nitride film and an oxide film in the order of stacking, and the first oxide film and the nitride film are sequentially formed. Since ion implantation is performed after stacking on the substrate and then an oxide film is formed on the nitride film, in addition to the effect of claim 3, enhanced diffusion due to oxidation at the time of forming the oxide film after ion implantation is caused by the nitride film. Since it is suppressed, the impurity concentration distribution during ion implantation is kept substantially constant.

[Brief description of drawings]

FIG. 1A is a sectional view of an embodiment of the present invention,
(B) is the impurity concentration distribution diagram, and (c) is the potential distribution diagram.

FIG. 2 is a diagram (a)₁), (B₁) Are mutually on the gate insulating film
Sectional views of examples of different film thickness, (a ₂), (B₂) Is an impurity
Concentration distribution map, (a₃), (B₃) Is the potential distribution map
Is.

3A is a sectional view of a conventional example, FIG. 3B is an impurity concentration distribution diagram thereof, and FIG. 3C is a potential distribution diagram.

[Explanation of symbols]

 1 substrate 2 gate insulating film 3 buried channel

Claims (4)

[Claims] 1. A substrate, a buried channel region formed on the substrate, and a gate insulating film formed on a surface of the substrate, wherein a peak value of an impurity concentration distribution of the buried channel is inside the substrate. A charge transfer device characterized by being present. 2. The gate insulating film has a three-layer structure including an oxide film, a nitride film and an oxide film in the order of stacking.
Charge transfer device. 3. A method of manufacturing a charge transfer device, comprising forming a buried channel in the substrate by implanting ions after forming a gate insulating film on the substrate. 4. The gate insulating film is composed of an oxide film, a nitride film and an oxide film in the order of stacking, and the first oxide film and the nitride film are sequentially stacked on the substrate and ion implantation is performed,
After that, an oxide film is formed on the nitride film.
A method of manufacturing the charge transfer device described.