JPH0714049B2 - Charge transfer device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge transfer device, and in particular, an inversion layer is included in a part of a semiconductor surface of each cell, and the inversion layer functions as a virtual electrode to gate-induce potential in the cell region. It relates to a buried channel charge transfer device (CCD) that is protected from changes.

BACKGROUND ART A buried channel CCD stores and transfers mobile charges in an induction channel in a semiconductor thin layer. Common surface-moving CCDs usually have trapping effects at the interface between oxide and silicon, but buried channel CCs
Since D can prevent this trapping effect,
The charge transfer efficiency is improved. Further, since carrier dispersion at the interface is eliminated, charge transfer efficiency is also improved. As a result, it is possible to operate at a higher frequency than before.

As such a buried channel type single-phase CCD, VP-CCD
There is (Virtual Phase CCD). For example, each cell included in the multi-cell type signal channel has four regions I.
II III IV, in which impurity implantation or diffusion is performed from the semiconductor surface to an appropriate depth,
The distribution of impurities in each region is different. A gate electrode is provided at least on the upper surface of the region I II, and the maximum potential generated in each region when the gate is on and when the gate is off is determined by the impurity distribution unique to each region. Area III
An inversion layer is provided on the semiconductor surface of the IV, and the inversion layer protects the region III IV from the potential change due to the voltage applied to the gate electrode, and the potential does not change when the voltage applied to the gate electrode is turned on and off. .

Therefore, by applying a single-phase clock signal to the gate electrode, the maximum potential of region I II is
It goes up and down repeatedly based on the maximum fixed potential of IV. In both gate states, the potential maximum value of the region II is higher than that of the region I, and the potential maximum value of the region IV is kept higher than that of the region III, so that the directionality of charge transfer can be obtained.

Such a VP-CCD has a drawback that its sensitivity is low when it is used as a photosensitive portion because about half of the substrate surface is covered with a polysilicon gate electrode.

Further, in order to facilitate setting of the impurity concentration in each region of the above VP-CCD, for example, each cell is made into three regions, an inversion layer is formed in one region, and two cells in which the inversion layer is not formed are formed. It is conceivable that a gate electrode made of polysilicon is provided in each region, and a charge is transferred by applying a two-phase drive pulse to these gate electrodes. In the case where the two-phase gate electrode is provided on the substrate surface as described above, since most of the substrate surface is covered with the polysilicon electrode,
Especially, there is a drawback that the sensitivity is lowered.

Aim The present invention aims to solve the above-mentioned drawbacks of the prior art and provide a highly sensitive buried channel type charge transfer device.

DISCLOSURE OF THE INVENTION According to the present invention, a gate having a buried channel including a plurality of cells is formed on one main surface of a semiconductor substrate of one conductivity type, and a gate is formed by an inversion layer formed on a part of the semiconductor surface of each cell. In a charge transfer device in which a part of each cell is selectively protected from potential changes caused by induction, a well of a reverse conductivity type with the substrate is formed on one main surface of a semiconductor substrate, and the well and the reverse conductivity type are formed in the well. A buried channel including a plurality of cells is formed, a gate electrode is formed on a portion of the surface of each cell where the inversion layer is not formed, and a well has a different thickness in a portion of the portion where the inversion layer is formed, A two-phase drive pulse is applied to the gate electrode and the substrate to transfer charges.

Description of Embodiments Embodiments of the charge transfer device according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows a cross section in the channel direction of an embodiment of the charge transfer device according to the present invention.

A p-type well 4 is formed in an n-type silicon substrate 2, and an n-type CCD channel is formed by an n-type region 6 formed in the p-type well 4. A plurality of cells are separated from each other and extend in the longitudinal direction of the channel, and each cell has three regions I II III. The n-type region 6 forming the n-type channel is implanted with a predetermined amount of impurities (donors) in each of the three regions I II III. The p-type well 4 is formed shallower in the region II than in the region I III.

Further, in the region II III, the p-type region 8 is formed above the n-type region 6. The p-type region 8 functions as a virtual electrode having a shielding effect for preventing the region II III from receiving a potential change due to gate induction. The thickness of the p-type region 8 is 0.15 to 0.7 μm, preferably 0.2 to 0.4 μm.
m.

An insulating layer 10 of SiO ₂ is formed on the p-type region 8 of the region II III and the n-type region 6 of the region I, and an electrode 12 is formed on the insulating layer 10 of the region I. The electrode 12 is made of polysilicon in this embodiment, is used as a gate electrode for applying a clock pulse for charge transfer, and is connected to the clock pulse source φ1.

In this embodiment, the substrate 2 is used as an electrode for applying a clock pulse for charge transfer, and the clock pulse source φ
Connected to 2.

Therefore, two-phase clock pulses are applied to the electrode 12 and the substrate 2, and the charges are transferred thereby. The p-type well 4 is grounded.

The doping density of the substrate 2 is 1 × 10 ^{14 to} 1 × 10 ¹⁶ / cm ³ . The upper surface of each cell is covered with a passivation film (not shown) formed of PSG or the like.

The potentials of the region I II III of the n-type channel 6 when no clock pulse is applied are shown in FIGS. 2 (a) to 2 (c).

The upper limit potential of the n-type channel 6 in the region III is determined and fixed by the amount of implanted donor impurities. On the other hand, the potential upper limit value of the n-type channel 6 in the region I is determined by the gate potential by the clock pulse φ1 applied to the electrode 12 and the amount of implanted donor impurities, and is variable. The upper limit value of the potential of the n-type channel 6 in the region II is also variable, which is determined by the gate potential by the clock pulse φ2 applied to the substrate 2 and the amount of the donor impurity implanted.
The charges are transferred in the direction of the arrow in FIG. 1 by the three potentials of these three regions.

FIG. 3 shows a timing chart of the voltages applied from the clock pulse sources φ1 and φ2.

4 (a) to 4 (c), φma is the maximum value of the potential of each region at times t1, t2, and t3 in FIG.
x is represented by a stepwise pattern of potential wells.

At time t1, no voltage is applied from either clock pulse source φ1 or φ2. At this time, the potential pattern of each region is the same as the n-type channel 6 of each region.
As shown in FIG. 4A, due to the impurity concentration implanted in the region 3, the region I has a three-step potential pattern that starts from the starting point and descends to the right, and the region III is at the lowest level.

At time t2, the high-level voltage Vg is applied from the clock pulse source φ1 and the voltage is not applied from the clock pulse source φ2. Therefore, the potential of the region I is lowered by the voltage Vg applied to the electrode 12, and the potential pattern of each region is a three-step potential pattern in which the potential starts from the region II and decreases to the right as shown in FIG. 4 (b). And region I is at the lowest level.

At time t3, the high-level voltage Vg is applied from the clock pulse source φ1 and the voltage Vsub is applied from the clock pulse source φ2. Therefore, as compared with the time t2, the voltage Vsub is applied to the substrate 2 so that the voltage Vsub is applied to the region II via the shallow portion of the p-type well 4.
Is applied, the potential of the region II decreases. Therefore, the potential pattern of each region is shown in FIG.
As shown in (3), a three-step potential pattern is formed in which the starting point is the region III and the potential pattern is lowered to the right, and the region II is at the lowest level.

The potential level of region III is kept at Vm III at any time from t1 to t3.

For example, considering the signal charge accumulated in the region III, at time t1, the potential of the region III is the lowest, so the signal charge is confined in the region III. At time t2, the potential of region I becomes low. At this time, since the region II III is shielded from the gate potential by the inversion layer of the p-type region 8, the potential does not change. At this point, the potential of the region I becomes lower than that of the region III, so that the charges accumulated in the region III move to the region I.

At time t3, the voltage Vsub is applied to the substrate 2,
The potential of region II becomes low. Area III I
In, the p-type well 4 is deeply formed, so that the voltage Vsub from the substrate 2 is not applied, the potential does not change. At this point, the potential of the region II becomes lower than that of the region I, so that the charges in the region I move to the region II.

According to the present embodiment, clock pulses φ1 and φ2 are applied to the gate electrode 12 and the substrate 2 to transfer charges, so that the gate electrode 12 provided on the surface of the substrate need only apply one-phase clock pulse. Therefore, unlike the case where a two-phase clock pulse is applied to a two-phase gate electrode to transfer charges, it is not necessary to provide a two-layer gate electrode on the substrate surface, and the area occupied by the electrode on the substrate surface is reduced. , The sensitivity is improved.

The impurity concentration of the n-type channel 6 and the p-type well 4
Of the voltage Vg applied to the gate electrode 12 and the magnitude of the voltage Vsub applied to the substrate 2 may be changed accordingly.

FIG. 5 shows a cross section in the channel direction of another embodiment of the charge transfer device according to the present invention.

In this embodiment, the p-type well 4 is formed deeper in the region II than in the region I III. Since the other structure is the same as that of the embodiment shown in FIG. 1, its explanation is omitted.

Also in this embodiment, the two-phase clock pulses φ1 and φ2 are applied to the electrode 12 and the substrate 2 to transfer charges.

The potentials of the region I II III of the n-type channel 6 when no clock pulse is applied are shown in FIGS. 6 (a) to 6 (c).

The upper limit potential of the n-type channel 6 in the region II is determined and fixed by the amount of implanted donor impurities. On the other hand, the upper limit potential of the n-type channel 6 in the region I is determined by the gate potential of the clock pulse φ1 applied to the electrode 12 and the clock pulse φ2 applied to the substrate 2 and the amount of the implanted donor impurities, It is variable. N-type channel 6 in region III
The potential upper limit value of is also determined by the gate potential by the clock pulse φ2 applied to the substrate 2 and the amount of implanted donor impurities, and is variable. The electric charge is fifthly divided by the three potentials of these three regions.
Transfer in the direction of the arrow in the figure.

FIG. 7 shows a timing chart of the voltages applied to the clock pulse sources φ1 and φ2. FIG. 8 (a)-
In FIG. 7C, the maximum value φmax of the potential of each region at times t1, t2, and t3 in FIG. 7 is represented by a stepwise pattern of potential wells.

At time t1, no voltage is applied from either clock pulse source φ1 or φ2. At this time, the potential pattern of each region is a three-step potential pattern that descends to the right from the region III as a starting point, as shown in FIG. 8A, depending on the impurity concentration injected into the n-channel 6 of each region. And Area II is at the lowest level.

At time t2, the voltage is not applied from the clock pulse source φ1 and the voltage Vsub is applied from the clock pulse source φ2. Therefore, when the voltage Vsub is applied to the substrate 2, the voltage Vsub is applied to the region III I via the shallow portion of the p-type well 4, and the potential of the region III I is lowered. In this case, the potential of the region III drops greatly, but the potential of the region I drops only slightly. As a result, the potential pattern of each region is a three-step potential pattern starting from the region I and descending to the right, as shown in FIG. 8B, and the region III is at the lowest level.

At time t3, the high-level voltage Vg is applied from the clock pulse source φ1 and the voltage Vsub is applied from the clock pulse source φ2. Therefore, as compared with the time t2, the potential of the region I is lowered by applying the voltage Vg to the electrode 12. Therefore, as shown in FIG. 8 (c), the potential pattern of each region is a three-step potential pattern starting from the region II and descending to the right, and the region I is at the lowest level.

The potential level of region II is maintained at Vm II at any time from t1 to t3.

For example, considering the signal charge accumulated in the area II,
At time t1, the potential of the region II is the lowest, so the signal charge is confined in the region II. Times of Day
At t2, the potential of region III becomes low. At this time, the potential slightly drops in the region I, but is still higher than that in the region II. Further, since the p-type well 4 is deeply formed in the region II, the voltage from the substrate 2 is
Since Vsub is not applied, the potential does not change.
At this point, the potential of the region III becomes lower than that of the region II, so that the charges accumulated in the region II move to the region III.

At time t3, since the voltage Vg is applied to the electrode 12, the potential of the region I becomes low. Since the region II III is shielded from the gate potential by the inversion layer of the p-type region 8, the potential does not change. At this point, the potential of region I becomes lower than that of region III,
The charges in II move to region I.

Also in the case of this embodiment, since the clock pulse is applied to the gate electrode 12 and the substrate 2 to transfer the charges, the gate electrode 12 provided on the surface of the substrate only needs to apply the one-phase clock pulse. Therefore, the area occupied by the electrodes on the substrate surface is reduced, and the sensitivity is improved.

Also in the case of this embodiment, the impurity concentration of the n-type channel 6 and the depth of the p-type well 4 are changed, and the voltage Vg applied to the gate electrode 12 and the voltage Vsub applied to the substrate 2 are correspondingly changed. You can change the size.

FIG. 9 shows a cross section in the channel direction of still another embodiment of the charge transfer device according to the present invention.

In this embodiment, the n-type channel 6 is formed deeper in the region II than in the region I III. Also,
As a result, the p-type well 4 has the region I III in the region II.
It is formed thinner than. Since the other structure is the same as that of the embodiment shown in FIG. 1, its explanation is omitted.

The potential when no voltage is applied in each region of this embodiment is the same as in FIGS. 2A to 2C, and the timing chart of the voltages applied from the clock pulse sources φ1 and φ2 is the same as in FIG. Yes, time t1, t2, t3 in FIG.
Maximum value of potential φma in each region
x is the same as in FIGS. 4 (a) to 4 (c).

An embodiment of the manufacturing process of the charge transfer device of FIG.
This is shown in Figures (a)-(g).

First, as shown in Fig. 10 (a), the doping density
A 2 × 10 ¹⁵ / cm ³ n-type single crystal silicon substrate 2 is used. An insulating layer 10 of SiO ₂ is formed on the surface of the n-type substrate 2 by an oxidation method so as to have a desired thickness, for example, 300 Å.

Next, as shown in FIG. 10A, boron (B) is implanted through the insulating layer 10 at an energy of 200 keV and a dose of 2 × 10 ¹² / cm ² . As a result, the p-type well 4 portion of the region II is formed.

Next, as shown in FIG. 10B, a photoresist 20 is formed on the insulating layer 10 so as to open a region III I portion, and boron (B) is passed through the insulating layer 10 at an energy of 200 keV,
Implant with a dose of 2x10 ¹² / cm ² . By this implantation and the implantation shown in FIG. 10 (a), the p-type well 4 in the region III I is formed.

Next, as shown in FIG. 10 (c), phosphorus (P) or arsenic (As) is passed through the insulating layer 10 at an energy of 200 keV and a dose of 2x10.
Drive at ¹² / cm ² . As a result, the n channel 6 portion of the region I is formed.

Further, as shown in FIG.
Is formed so as to open a region II III portion, and the insulating layer 10
Through phosphorus (P) or arsenic (As) with energy of 200k
Implant with eV and dose 2x10 ¹² / cm ² . As a result, n in the region I
The channel 6 part is formed.

Further, as shown in FIG.
Is formed so as to open a region III portion, and phosphorus (P) or arsenic (As) is passed through the insulating layer 10 at an energy of 200 ke
V, are implanted at a dose 2x10 ¹² / cm ^2. As a result, n in region III
The channel 6 part is formed. Due to these implantations, the potential becomes as shown in FIG. 4 (a) when the potential voltage of the regions I II III is not applied.

Further, a polycrystalline silicon layer is formed on the insulating layer 10 and plasma etching is performed using a photoresist (not shown) to form a gate electrode 12 as shown in FIG. 10 (f).

Next, as shown in FIG. 10 (g), the gate electrode 12 is formed on the region II.
The insulating layer 10 is used as a mask with an opening III.
Boron (B) energy through 40keV, dose 1x10 ¹³ / cm
Type in ² . By this implantation, a p-type region 8 to be a virtual electrode of the region II III is formed.

In this way, the charge transfer device shown in FIG. 1 is manufactured. Note that heat treatment is performed after the implantation of each impurity, and the implanted impurities are diffused into silicon to an appropriate depth to form a correct potential distribution state.

One example of the manufacturing process of the charge transfer device of FIG.
This is shown in Figures (a)-(g).

First, as shown in Fig. 11 (a), the doping density
A 2 × 10 ¹⁵ / cm ³ n-type single crystal silicon substrate 2 is used. An insulating layer 10 of SiO ₂ is formed on the surface of the n-type substrate 2 by an oxidation method so as to have a desired thickness, for example, 300 Å.

Next, as shown in FIG. 11A, boron (B) is implanted through the insulating layer 10 at an energy of 200 keV and a dose of 2 × 10 ¹² / cm ² . As a result, the p well 4 of the region IIII is formed.

Next, as shown in FIG. 11 (b), phosphorus (P) or arsenic (As) is supplied through the insulating layer 10 at an energy of 200 keV and a dose of 2x.
Drive at 10 ¹² / cm ² . By this implantation, n in region III
The channel 6 part is formed.

Further, as shown in FIG. 11 (c), the photoresist 26
Is formed so that the region I II is opened, and phosphorus (P) or arsenic (As) is applied to the insulating layer 10 at an energy of 200 keV,
Implant with a dose of 2x10 ¹² / cm ² . As a result, the n channel 6 portion of the region I is formed.

Further, as shown in FIG. 11 (d), the photoresist 28
Is formed so as to open a region II portion, and phosphorus (P) or arsenic (As) is implanted through the insulating layer 10 at an energy of 200 keV and a dose of 2 × 10 ¹² / cm ² . As a result, the n channel 6 portion of the region II is formed. With these implants, the area
The potential of I II III becomes a potential as shown in FIG. 8 (a) when no voltage is applied.

Next, a polycrystalline silicon layer is formed on the insulating layer 10, and plasma etching is performed using a photoresist (not shown),
11 A gate electrode 12 is formed as shown in FIG.

Further, as shown in FIG. 11 (f), a photoresist 30 is formed on the insulating layer 10 and the gate electrode 12 so as to open a region II, and boron (B) is supplied through the insulating layer 10 at an energy of 400 keV, Implant with a dose of 2x10 ¹² / cm ² . By this implantation and the implantation shown in FIG. 11 (a), the p-type well 4 in the region II is formed.

Further, as shown in FIG. 11 (g), the photoresist 30 is removed, and the gate electrode 12 is used as a mask having an opening in the region II III, and boron (B) is passed through the insulating layer 10 at an energy of 40 keV and a dose. Drive at 1x10 ¹² / cm ² . By this implantation, a p-type region 8 to be a virtual electrode of the region II III is formed.

In this way, the charge transfer device shown in FIG. 5 is manufactured. Note that heat treatment is performed after the implantation of each impurity, and the implanted impurities are diffused into silicon to an appropriate depth to form a correct potential distribution state.

An embodiment of the manufacturing process of the charge transfer device of FIG.
This is shown in Figures (a)-(f).

First, as shown in Fig. 12 (a), the doping density
A 2 × 10 ¹⁵ / cm ³ n-type single crystal silicon substrate 2 is used. An insulating layer 10 of SiO ₂ is formed on the surface of the n-type substrate 2 by an oxidation method so as to have a desired thickness, for example, 300 Å.

Next, as shown in FIG. 12 (a), boron (B) is implanted through the insulating layer 10 at an energy of 200 keV and a dose of 2 × 10 ¹² / cm ² . As a result, the p-type well 4 portion of the region IIII is formed.

Next, as shown in FIG. 12 (b), phosphorus (P) or arsenic (As) is passed through the insulating layer 10 at an energy of 200 keV and a dose of 2x.
Drive at 10 ¹² / cm ² . By this implantation, the n channel 6 portion of the region I is formed.

Further, as shown in FIG.
Is formed so as to open a region III portion, and phosphorus (P) or arsenic (As) is supplied through the insulating layer 10 at an energy of 200 keV,
Implant with a dose of 2x10 ¹² / cm ² . As a result, the n channel 6 portion of the region III is formed.

Next, a polycrystalline silicon layer is formed on the insulating layer 10, and plasma etching is performed using a photoresist (not shown),
12 A gate electrode 12 is formed as shown in FIG.

Further, as shown in FIG. 12E, a photoresist 30 is formed on the insulating layer 10 and the gate electrode 12 so as to open a region II portion, and phosphorus (P) or arsenic (As) is formed through the insulating layer 10. ) With an energy of 400 keV and a dose of 2x10 ¹² / cm ² . By this implantation and the implantation of Fig. 12 (b), the area
The n channel 6 of II is formed deeper than the region III I.
As a result, the potential of the region I II III becomes a potential as shown in FIG. 4 (a) when no voltage is applied.

Further, as shown in FIG. 12 (f), the photoresist 30 is removed, and the gate electrode 12 is used as a mask having an opening in the region II III, and boron (B) is passed through the insulating layer 10 at an energy of 40 keV and a dose. Drive at 1x10 ¹² / cm ² . By this implantation, a p-type region 8 to be a virtual electrode of the region II III is formed.

In this way, the charge transfer device shown in FIG. 9 is manufactured. Note that heat treatment is performed after the implantation of each impurity, and the implanted impurities are diffused into silicon to an appropriate depth to form a correct potential distribution state.

In any of the above-mentioned embodiments, when the p-type channel CCD is manufactured using the n-type silicon substrate as the material, the polarities may be reversed. Further, a semiconductor containing a III-V or II-IV compound such as indium antimonide or mercury cadmium telluride may be used.

Effect According to the present invention, since a two-phase clock pulse is applied to the gate electrode on one surface of the substrate and the substrate to transfer charges, the gate electrode provided on the surface of the substrate may be one layer. Therefore, the area occupied by the gate electrode on the surface of the substrate can be small, so that a highly sensitive charge transfer device can be obtained.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of a charge transfer device according to the present invention, and FIGS. 2 (a) to 2 (c) are diagrams showing the potential of a region I II III when no voltage is applied to the device of FIG. , FIG. 3 shows clock pulse sources φ1 and φ of the device of FIG.
2 is a timing chart showing an example of the voltage applied to No. 2, FIG. 4 (a) is a graph showing the potential state of region I II III at time t1 in FIG. 3, and FIG. 4 (b) is time t2 in FIG. 4 is a graph showing the potential state of the region I II III in FIG. 4, FIG. 4 (c) is a graph showing the potential state of the region I II III at time t3 in FIG. 3, and FIG. 5 is another graph of the charge transfer device according to the present invention. 6 is a sectional view showing an embodiment, FIGS. 6 (a) to 6 (c) are diagrams showing the potential of the region I II III of the device of FIG. 5 when no voltage is applied, and FIG. 7 is a clock of the device of FIG. Pulse source φ1, φ
8 is a timing chart showing an example of the voltage applied to No. 2, FIG. 8 (a) is a graph showing the potential state of region I II III at time t1 in FIG. 7, and FIG. 8 (b) is time t2 in FIG. 8 is a graph showing the potential state of the region I II III in FIG. 7, FIG. 8 (c) is a graph showing the potential state of the region I II III at time t3 in FIG. 7, and FIG. 9 is another graph of the charge transfer device according to the present invention. 10 is a sectional view showing an embodiment, FIGS. 10 (a) to 10 (g) are views showing a manufacturing process of the charge transfer device shown in FIG. 1, and FIGS. 11 (a) to 11 (g) are charges shown in FIG. FIGS. 12A to 12F are views showing the manufacturing process of the transfer device, and FIGS. 12A to 12F are views showing the manufacturing process of the charge transfer device shown in FIG. Explanation of symbols of main parts 2 ... Substrate 4 ... P-type well 6 ... N-type region 8 ... P-type region 10 ... Insulating layer 12 ... Gate electrode φ1, φ2 ... Clock pulse source

Claims (5)

[Claims] 1. A one-conductivity-type semiconductor substrate on one main surface,
A charge transfer device having a buried channel including a plurality of cells, wherein a part of each cell is selectively protected from a gate-induced potential change by an inversion layer formed on a part of the semiconductor surface of each cell. In the device, in the device, a well of opposite conductivity type to the substrate is formed on one main surface of the semiconductor substrate, and a buried channel including the plurality of cells of opposite conductivity type to the well is formed in the well. A gate electrode is formed on a portion of the surface of each cell where the inversion layer is not formed, and the well has a different thickness in a portion of the portion where the inversion layer is formed. A charge transfer device characterized by applying a phase drive pulse to transfer charges. 2. The charge transfer device according to claim 1, wherein the well is shallowly formed in a part of a portion where the inversion layer is formed. 3. The charge transfer device according to claim 1, wherein the well is deeply formed in a part of a portion where the inversion layer is formed. 4. The device according to claim 1, wherein the buried channel is deeply formed in a part of a portion where the inversion layer is formed, and the well is thinly formed in this portion. Charge transfer device characterized by. 5. The device according to any one of claims 1 to 4, wherein the semiconductor substrate is n-type silicon, the well is a p-type well, and the buried channel is n-type conductive. Shows a charge transfer device.