JPS6286862A - Charge transfer device - Google Patents

Abstract

PURPOSE:To raise the sensitivity of a charge transfer device by applying a clock pulse through an electrode arranged on an element separating region to a P-N junction diode to transfer the charge. CONSTITUTION:An N-type CCD channel is formed of an N-type region 4 formed on a P-type silicon substrate 2. Each cell has four regions I, II, III, IV, to which different impurities are respectively implanted. A P-type region 6 is uniformly formed on the region 4, and an n-type region 8 is formed on the region 6 in the region II and an element separating region 12. A diode formed of the regions 8, 6 is used as a gate electrode for applying a clock pulse for transferring the charge, and the region 8 is connected with the aluminum electrode 10 of the region 12. Thus, the incident light does not pass the gate electrode but is incident directly to the semiconductor, thereby improving a sensitivity.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to charge transfer devices, and more particularly to charge transfer devices, in which an inversion layer is included on the semiconductor surface of a portion of each cell, and the inversion layer acts as a virtual electrode to connect the cell region to a gate-induced potential. The present invention relates to a buried channel single phase charge transfer device (CAN) that is protected against changes.

BACKGROUND ART Single-phase GCDs are known in which, for example, a continuous conductive gate layer is provided on a signal channel of a CCD. This single-phase COD is a surface channel device, ie, a COD in which signal charge packets move across the semiconductor surface. Such a single-phase CCD has a disadvantage in that it has a smaller signal processing ability than a normal multi-phase COD and requires a large-amplitude clock pulse.

Also, in buried channel CCDs, storage and transfer of mobile charges takes place in guided channels within a thin semiconductor layer. In general surface-transfer type CODs, a trapping effect usually occurs at the interface between oxide and silicon, but in buried channel type CCDs, this trapping effect can be prevented, thereby improving charge transfer efficiency. Furthermore, since carrier dispersion at the interface is eliminated, charge transfer efficiency is also improved. As a result, operation at a higher frequency than before is possible.

VP as such a buried channel type single phase CCD
-can (Birchself AIDS CCD). This means, for example, that each cell included in a multi-cell signal channel has four regions lllll11■, into which impurities are implanted or diffused to an appropriate depth from the semiconductor surface. Each impurity distribution is different. A gate electrode is provided at least on the top surface of the region, and when the gate is turned on, due to the impurity distribution specific to each region,
The maximum potential generated within each region at gate-off is determined.

An inversion layer is provided on the semiconductor surface of the region ■■, and this inversion layer protects the region ■■ from changes in potential due to the voltage applied to the gate electrode, and the potential changes depending on whether the voltage applied to the gate electrode is turned on or off. Therefore, by applying a single-phase clock signal to the gate electrode, the maximum potential value of the region ■■ will change to the area ■■
(2) Iteratively moves up and down based on the fixed potential maximum value. In both gate states, the maximum potential value of region H is higher than region I, and the maximum potential value of region (2) is maintained higher than that of region (2), so that directionality of charge transfer can be obtained.

In this way, when p-can is used as an image sensor,
Unlike the conventional FT-CC, D, in which the entire surface of the semiconductor layer is covered with a polysilicon electrode for charge transfer, only region III needs to be covered with a polysilicon electrode, so it is less sensitive to incident light. Good sensitivity. However, since at least half of the light-receiving area (2) is covered with a polysilicon electrode, there is a drawback that the sensitivity to light incident from this area, particularly the sensitivity to blue light, is low.

A conceivable solution to this drawback is to contact the region ILT with a pn junction diode, apply a voltage to the pn junction diode, and use it as a gate electrode. With this configuration, since region III is not covered with a polysilicon electrode, the sensitivity of light incident from this portion can be improved. However, since the pn junction diode is used as the charge transfer electrode, the resistance of the electrode becomes large and high-speed transfer is not possible. Furthermore, since light also enters the element isolation region, there is a drawback that color separation is degraded.

the purpose The present invention overcomes these drawbacks of the prior art.

An object of the present invention is to provide a buried channel type single-phase charge transfer device that has good sensitivity to incident light and can be driven at high speed when used as an image sensor.

DISCLOSURE OF THE INVENTION According to the present invention - a semiconductor substrate of a conductive type has a buried channel of a reverse conduction type in a main surface of a portion thereof, the channel comprising a plurality of cells, each cell having a buried channel formed in the semiconductor surface of a portion of the conduction type; A charge transfer device, in which a portion of each cell is selectively protected from gate-induced potential changes by an inversion layer, is formed by a region of P-type conductivity and a region of N-type conductivity at the surface of each cell. It has a diode and an electrode arranged in the element isolation region and connected to the diode,
A voltage for charge transfer is applied to the diode through the electrode.

DESCRIPTION OF EMBODIMENTS Embodiments of a charge transfer device according to the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 shows an example of a cross section in the channel direction of a charge transfer device according to the present invention and a cross section perpendicular to the cross section.

The n-type region 4 formed on the p-type silicon substrate 2
A type CCD channel is formed. A plurality of cells are separated from each other and extend in the longitudinal direction of the channel, and each cell has four regions I■■■. As described later, different amounts of impurities (donors) are implanted into each of the four regions rnmrv of the n-type region 4 that forms the n-type channel. In the region I[11'V, the p5 region 6 functions as a virtual electrode having a shielding effect to prevent potential changes due to gate induction. The thickness of the P-type region 6 is 0.15 to 0.7 Bm, preferably 0.2 to 0.7 Bm.
4pm. In region III and the element isolation region 12 extending in the longitudinal direction of the channel, an n-type region 8 is formed above the p-type region 6 . The thickness of this n-type region 8 is 0.05 to 0.5 JLm, preferably 0.1 to 0.2
Named Hirom.

In region I[1, a diode formed by an n-type region 8 and a p-type region 8 is used as a gate electrode for applying a clock pulse for charge transfer, and is used as a gate electrode for applying a clock pulse for charge transfer, and is used in this embodiment through the n-type region 8 of the element isolation region 12. In the example, it is connected to the electrode IO of AI. The AI electrode 10 is disposed long and thin in the longitudinal direction of the channel on the element isolation region 12, and is connected to the n-type region 8 on the element isolation region 12, which is formed in a continuous manner with the n-type region 8 of the area process of each cell. p of the region In
A single-phase clock pulse is applied to the n-junction diode, and elements are separated in a direction perpendicular to the longitudinal direction of the channel. The electrode IO has a lower resistance than the n-type region 8, and an opaque material 1 such as metal or polysilicon is advantageously used.

FIG. 2(a) is a plan view of an embodiment of the present invention in which a plurality of CCD channels are formed, FIG. 2(b) is a sectional view taken along line B-B in FIG. ) in Figure 2(a)
A line cross section is shown. FIG. 2(b) shows a cross section in the longitudinal direction of the channel, and FIG. 2(C) shows a cross section taken through region I in a direction perpendicular to the longitudinal direction of the channel.

As can be seen from FIGS. 1 and 2(a) to (c), on the upper surface of the n-type region 8 of the region III of each cell and the upper surface of the p-type region 6 of the region III of each cell, there is an AI. Except for the element isolation region 12 where the main electrode is provided, SiO□ or PS
Insulation n914 of G is provided.

Potential upper limit 11 of n-type channel in region l11ff
11t is determined by the implanted donor impurity and is fixed. On the other hand, the upper limit of the potential of the n-type channel in region TTI is the n-type region 8 and the p-type region 6.
is determined by the gate potential due to the clock pulse applied through the A1 electrode 8i10 to the diode formed by the diode, and the amount of donor impurity implanted,
It is variable. The 'It load is transferred by the four potentials in these four regions.

The doping density of the substrate 2 is 1xlO"~1!101
6/Cff13. Further, the upper surfaces of the Al electrode 10 and the insulating film 14 of each cell are covered with a passivation film (not shown) formed of PSG or the like.

FIG. 3(a) shows the impurity concentration distribution in the region (■).The amount of phosphorus doped is small in the region I, and large in the region H. The boron doping amount is the same for both regions and is implanted shallower than the phosphorus doping. The doping amount of arsenic is also the same for both regions, and is implanted more shallowly than the doping of boron.

Figure 3 (b, l shows the impurity concentration distribution in region m).The amount of phosphorus doped is small in region m, and large in region The doping amount is the same for the region, and is implanted shallowly compared to the doping of phosphorus.Also, the amount of doping of phosphorus to the region (2) is larger than that to the region (2).

Figures 4(a)-(d) show the potential state of each of the four buried channel regions in each cell under the established gate potential conditions as a function of distance from the semiconductor surface. . FIG. 4(a) shows the potential state of the region In when the gate is on (a state in which a relatively large positive voltage, for example, 7 to 15 ports, is applied to the n-type semiconductor side of the pn junction diode with respect to the substrate 2). FIG. 4(b) shows region I when the gate is on.
The potential state of IIIV is shown. FI114 diagram (C
) is when the gate is off (relatively small voltage across the pn junction diode).

For example, in region I (with 1 to 5 ports applied)
FIG. 4(d), which shows the potential state of region (2), shows the potential state of region (2) when the gate is off.

As can be seen from FIGS. 4(a) to 4(d), when the gate is on, the maximum value of the potential in each region φa! The following relationship holds true between them.

φmaxII>φmaxI>φmaxIV>
φ1rax m On the other hand, the following relationship holds true when the gate is off.

φtsax■＞φmaxlII＞φmaxU＞φwax
I charge transfer is performed by repeating the ON and OFF states of the gate voltage (voltage applied to the pn junction diode).

In FIG. 5, the maximum potential value φax in each region is represented by a stepped pattern of potential wells. The gate-on state is represented by a potential well pattern indicated by a thick line, and the pattern is a four-stage potential pattern starting from region (2) and going down to the right, with region (2) being the lowest level. On the other hand, in the gate-off state, there is a four-stage potential pattern that starts from region I and descends to the right.

For example, considering the signal charge accumulated in region H,
When the gate is on, the φ layer aX in the region (2) is at its highest level, so the electron charges are confined within this region. When the gate is turned off, both the φ layer ax II and the φ layer ax I decrease. At this time, since the region 111IV is shielded from the gate potential by the inversion layer of the p-layer region 6, φIIax m and φff1ax IV are constant. At this point, the potential of the region (2) becomes higher than that of the region H, so the signal charge moves to the region (2) through the region (2). P-layer region 6 forms a virtual electrode. When the gate potential is raised to the on state again, the charge changes to the area ■
flows to. Charge transfer is thus performed by applying a single pulse to the pn junction diode via electrode lO.

According to this embodiment, A1 disposed in the element isolation region 12
Since the charge is transferred by applying a clock pulse to the pn junction diode through the electric current pi10, there is no need to provide a gate electrode on the surface of region III for applying the clock pulse as in the conventional case.Therefore, it can be used as an image sensor. In this case, since the incident light directly enters the semiconductor without passing through the gate electrode, it is possible to prevent a decrease in sensitivity due to the gate electrode.

In particular, sensitivity to blue light is improved.

Moreover, p used as the gate electrode of region I II
Since the AI electrode 10 is connected to the n-junction diode, the resistance of the gate electrode is small and the driving frequency is high.
High-speed transfer is possible.

Furthermore, since the AI electrode 10 is provided in the element isolation region 12, no light is incident on the element isolation region 12, so that element isolation such as color separation is possible.

Furthermore, since the region In has a p-layer region 6 and an n-type region 8 forming a diode on the upper surface of the n-channel, a shallow region near the semiconductor surface is formed as shown in FIGS. In the third region, the potential becomes smaller due to the p-type head area θ, and furthermore, in the part near the semiconductor surface, the potential increases again due to the n-type region 8.
It is shown as a small mountain (an upwardly convex curve) in Figures (a) and (C). Therefore, due to such a mountain portion with a small potential, the excess charge accumulated in the region H flows to the n portion of the surface before overflowing to the adjacent picture element portion, so that plumping can be prevented.

FIG. 6 shows a cross-sectional view of another embodiment of the invention. This figure shows a cross section of the area cut in a direction perpendicular to the longitudinal direction of the channel, and corresponds to FIG. 2(c). In this embodiment, the electrode has a polysilicon portion 16 formed of polysilicon in the portion that contacts the n-type region 8 on the element isolation region 12, and an upper portion of the polysilicon portion 16 made of AI.
The aluminum portion 18 is made of aluminum.

According to this embodiment, the n-type region 8 is, for example, 0.1 to 0.
．． Even if the thickness is 2 gm and shallow, the polysilicon portion 16 can prevent aluminum spikes from occurring in the aluminum portion.

Therefore, p
The aluminum spike does not extend to the mold head area 6.

An embodiment of the manufacturing process of the charge transfer device of the present invention is shown in the seventh embodiment.
Shown in Figures (a) to (g).

First, a p-type single crystal silicon substrate 2 with a doping density of 2x 1015/cm3 as shown in FIG. 7(a) is used. An oxide layer 20 is formed on the surface of this p-type substrate 2 to a desired thickness, for example, 300 angstroms, by an oxidation method.

Next, as shown in FIG. 7(a), phosphorus (P) is irradiated through the oxide layer 20 with an energy of 200 keV and a line M3 x 1012.
Enter /cm2. This forms the n-channel portion of the region.

Next, a mask 22 with an opening in region H as shown in FIG. 7(b) is formed, and phosphorus (P) is passed through the oxide layer 20.
Energy 200keV, dose I x 1012/0
The n-channel portion in region (2) is formed by this implantation at step m2 and the implantation shown in FIG. 7(a).

Furthermore, a mask 24 having an opening in region m as shown in FIG.
) with an energy of 200 keV, ks, fii 3 x
1012/am2, and by this implantation and the implantations shown in FIGS. 7(a) and 7(b), an n-channel portion in region (2) is formed.

Furthermore, a mask 2B with an opening in the region (2) as shown in FIG. 7(d) is formed, and phosphorus (P) is passed through the oxide layer
) with an energy of 200 keV and a dose of 5 z 1012/c
This driving with m2 and Figure 7 (a) (b)
By the implantation in (c), an n-channel portion in region (2) is formed.

Roughly as shown in FIG. 7(e), the oxide layer 20 is
jl m (B) with energy 40keV and dose 1xl
O13/ Drive at 0m2. This implantation creates a virtual electrode in region IIIIV and a pn junction in region III.
A p-type head region 6, which becomes a type region, is formed.

Furthermore, the area In and as shown in FIG. 7(f).

A mask 28 with openings in the oxide layer 20 and the element isolation region is formed, and arsenic (As) is heated at 40 ke through the oxide layer 20.
V, implant with a dose of 1 x 1013/cta2,
This implantation forms an n-type region 8 which becomes the n-type region of the pn junction in region III and the n-type region of the element isolation region.

Note that heat treatment is performed after implanting each impurity, and the implanted impurities are diffused to an appropriate depth in the silicon to form a correct potential distribution state.

Next, the oxide layer 20 in the element isolation region 12 is removed by a well-known etching method, and an AI electrode 10 is provided on the exposed element isolation region 12, as shown in FIG. 7(g). Further, by forming a passivation film (not shown) such as PSG on the upper surface of the AI electrode 10, a charge transfer device can be obtained.

Note that using an n-type silicon substrate as a material, C of the p-type channel is
When manufacturing a CD, each polarity may be reversed, or a semiconductor containing a 1-v, 11-2 compound such as indium antimonide or mercury cadmium telluride may be used.

肱-1 According to the present invention, a clock pulse is applied to a pn junction diode through an electrode disposed in an element isolation region to transfer charge. There is no need to provide it on the surface.
Therefore, when the semiconductor device is used as an image sensor, incident light is directly incident on the semiconductor without passing through the gate electrode, so it is possible to prevent the sensitivity from decreasing due to the gate electrode, and the sensitivity to blue light in particular is improved.

Furthermore, since the electrode is connected to the pn junction diode used as the gate electrode, the resistance of the gate electrode is low, the driving frequency is high, and high-speed transfer can be performed.

Furthermore, since the electrodes are provided in the element isolation region, no light is incident on the element isolation region, which facilitates element isolation such as color separation.

Furthermore, since a peak of potential, that is, a vertical overflow drain structure is formed by the pn junction diode, blooming can be prevented.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional perspective view showing an embodiment of the charge transfer device according to the present invention, FIG. 2(a) is a plan view showing an embodiment of the charge transfer device according to the present invention, and FIG. BB-B cross-sectional view in Figure 2 (a), 7JS
Figure Z (C) is a sectional view taken along the line C-C in Figure 2 (a), and Figure 3 (
a) is a graph showing the impurity concentration distribution in region I, FIG. 3(b) is a graph showing the impurity concentration distribution in region m, and FIG. 4(a) is a graph showing the potential state of region In when the gate is on. , FIG. 4(b) is a graph showing the potential state of region ■■ when the gate is on, and FIG. 4(C) is a graph showing the potential state of region ■■ when the gate is off. FIG. 4(d) is a graph showing the potential state of the region ■■ when the gate is off, FIG. 5 is a graph showing the potential well of each region, and FIG. 6 is a graph showing another embodiment of the charge transfer device according to the present invention. Cross-sectional view, $711nCa) ~ (g) is ff1llN,
i2 is a diagram showing the manufacturing process of the charge transfer device shown in Figures (a) to CC). Explanation of some symbols 260. Substrate 4.1. N-type region 8 , P-type region 8 , N-type region 10 , Electrode 11 , Element isolation region 14 , Insulating film patent applicant Fuji Photo Film Co., Ltd. Representative Takao Katori Takao Maruyama 1 concave & 2 closed (0 con 2 diagram (b) 2 diagram (c) tail 4121 rQ) (C)
(b) (d)7
vFigure 3 (b
) 0 ] Kadeka 7 figure 7th leap (e)

Claims (1)

[Claims] 1. A reverse conduction type buried channel including a plurality of cells is provided on one main surface of a one conductivity type semiconductor substrate, and an inverted channel formed on the semiconductor surface of a part of each cell. A charge transfer device in which a portion of each cell is selectively protected from gate-induced potential changes by a layer, the device comprising: a region of p-type conductivity and a region of n-type conductivity on the surface of each cell; has a diode formed by
A charge transfer device comprising an electrode disposed in an element isolation region and connected to the diode, and a charge transfer voltage is applied to the diode through the electrode. 2. The device of claim 1, wherein the diode is formed on an unprotected surface of each cell, and a region of the diode with opposite polarity to the channel is continuous with the inversion layer. A charge transfer device characterized in that: 3. A charge transfer device according to claim 1, wherein the semiconductor substrate is p-type silicon and the buried channel exhibits n-type conductivity. 4. The device according to claim 1, wherein each cell includes four regions with different impurity concentrations, and only the third region and the fourth region are selectively protected by the inversion layer. charge transfer device. 5. A charge transfer device according to claim 1, wherein the electrode is metal.