JPS6272165A - Charge transfer device - Google Patents

Abstract

PURPOSE:To prevent blooming by applying a clock pulse to an p-n junction diode to transfer charges, and forming a vertical overflow p-n junction diode to transfer charges, and forming a vertical overflow drain structure by the p-n junction diode, thereby enhancing the sensitivity to the blue light. CONSTITUTION:An n-type CCD channel is formed by an n-type region 4 which is formed in a p-type silicon substrate 2, and each cell has four regions I-IV. The n-type region 4 forming the n-type channel has different amounts of impurities driven into the four regions I-IV. Above the n-type region 4, a p-type region 6 is uniformly formed in the four regions I-IV. The p-type region 6 functions in the regions III, IV as a virtual electrode which has a shield effect for avoiding potential change due to the gate induction. In the regions I, II, an n-type region 8 is formed above the p-type region 6, and a diode formed by the n-type region 8 and the p-type region 6 is used as a gate electrode for applying a clock pulse for charge transfer, and connected to a clock pulse source.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to charge transfer devices, and more particularly to charge transfer devices, in which an inversion layer is included on the semiconductor surface of a portion of each cell, and the inversion layer acts as a virtual electrode to connect the cell region to a gate-induced potential. The invention relates to a buried channel single phase charge transfer device (can) that is protected against changes.

BACKGROUND OF THE INVENTION One known neutralizing CCD is, for example, one in which a continuous conductive gate layer is provided over the signal channel of the CCD. This neutralizing CCD is a surface channel device, ie a CCD in which signal packets are moved across the semiconductor surface. Such a medium-phase CC[l is a normal multi-phase 1; it has a disadvantage that its signal processing ability is smaller than that of a CD, and that it requires a large-amplitude clock pulse.

Also, in buried channel CCDs, storage and transfer of mobile charges takes place in guided channels within a thin semiconductor layer. In general surface-transfer type CCDs, a troughing effect usually occurs at the interface between oxide and silicon, but in buried channel type CODs, this trapping effect can be prevented, thereby improving charge transfer efficiency. Furthermore, since carrier dispersion at the interface is eliminated, charge transfer efficiency is also improved. As a result, operation at a higher frequency than before is possible.

VP as such a buried channel type single phase CCD
-cco (partial phase CCO), which means, for example, that each cell included in a multi-cell signal channel has four regions 1111IIIV, and within these regions, impurities are added to a suitable depth from the semiconductor surface. Each region is implanted or diffused and has a different impurity distribution. A gate electrode is provided on at least the upper surface of region III, and the maximum potential generated in each region when the gate is on and when the gate is off is determined by the impurity distribution specific to each region.

An inversion layer is provided on the semiconductor surface of region I11■, and this inversion layer protects region m■ from changes in potential caused by the voltage applied to the gate electrode, and the potential changes by turning on and off the voltage applied to the gate electrode. It does not change. Therefore, by applying a single-phase clock signal to the gate electrode, the maximum potential value in region III is repeatedly raised and lowered with respect to the fixed potential maximum value in region I[IIV. In both gate shapes 5a, the maximum potential value of the region H is higher than that of the region 5a, and the maximum potential value of the region 2 is maintained higher than that of the region m, so that the directionality of charge movement can be obtained.

In this way, when p-cCn is used as an image sensor,
Unlike conventional FT-CCDs, where the entire surface of the semiconductor layer is covered with a polysilicon electrode for charge transfer, only region III needs to be covered with a polysilicon electrode, so sensitivity to incident light is good. However, since at least half of the area II of the light-receiving section is covered with a polysilicon electrode, there is a drawback that the sensitivity to light incident from this part, particularly the sensitivity to blue light, is low.

Purpose The present invention solves the drawbacks of the prior art and improves the image element.
It is an object of the present invention to provide a buried channel type medium-phase load transfer device that has good sensitivity to incident light, especially high sensitivity when used as a receiver.

DISCLOSURE OF THE INVENTION According to the present invention, a semiconductor substrate of one conductivity type has a buried channel of an opposite conductivity type on one main surface thereof, which includes a plurality of cells, and an inverted channel formed on the semiconductor surface of a portion of each cell. In a charge transfer device where a layer selectively protects a portion of each cell from gate-induced potential changes, the surface of each cell is protected by a region of p-type conductivity and a region of n-type conductivity. It has a diode formed therein, and a voltage for charge transfer is applied to the diode.

DESCRIPTION OF EMBODIMENTS Next, embodiments of a charge transfer device according to the present invention will be explained in detail with reference to the accompanying drawings.

FIG. 1 shows an example of a cross section in the channel direction of a charge transfer device according to the present invention and a cross section perpendicular to the cross section.

The n-type region 4 formed on the p-type silicon substrate 2
A type CCD channel is formed. A plurality of cells are separated from each other and extend in the longitudinal direction of the channel, each cell having four regions III[1■]. n
In the n-type region 4 forming the type channel, different amounts of impurities (donors) are implanted into each of the four regions III [11V, as will be described later. Above the n-type region 4, the p-type region 6 is uniformly formed into four 'lWMIIImIV. This p-type region 6 operates as a virtual electrode having a shielding effect in order to prevent changes in potential due to gate induction in region (■). P
The thickness of the mold region 6 is 0.15 to 0.7 gm, preferably 0.
．． 2 to 0.4 pm. In region III, an n-type region 8 is formed above the p-type region 6;
A diode formed by p-type region 6 and p-type region 6 is used as a gate electrode for applying a clock pulse for charge transfer and is connected to a clock pulse source (not shown). The thickness of the n-type region 8 is 0.05 to 0.54 m, preferably 0.1 to 0.2 gm.

The upper limit value of the potential of the n-type channel in region (■) is determined by the amount of implanted donor impurity and is fixed. On the other hand, the upper limit of the potential of the n-type channel in region III is determined by the gate potential due to the clock pulse applied to the diode formed by the n-type region 8 and the p-type region 6 and the amount of donor impurity implanted, and is variable. be. Charges are transferred by the four potentials in these four regions.

The doping density of the substrate 2 is IxlO” ~l!101
6/cm3. The L side of each cell is covered with a puffy film (not shown) made of PSG or the like.

Figure 2(a) shows the impurity concentration distribution in region IIT.
For I, multi-value processing is performed. The boron doping amount is equal to the circular region and is implanted shallower than the phosphorus doping. The arsenic doping JM is also very deep in the circular region, and is implanted more shallowly than the boron doping.

FIG. 2(b) shows the impurity C degree distribution in region mff, and the doping amount of phosphorus is small IA for region m.

A large amount of this is done for area (■). The amount of ta element doped is equal to the circular region, and is implanted shallower than the phosphorus doping. Further, the phosphorus doping r4 in the region (3) is multivalued compared to the region H.

Figures 3(a) to (d) show the obtained gate buttons.
The potential state of each of the four buried channel regions in each cell under atomical conditions is expressed as a function of distance from the surface of the semiconductor. Figure 3 (
a) When the gate is on (a relatively large positive voltage is applied to the n-type semiconductor side of the pn junction diode with respect to the substrate, e.g.
Figure 3',b) shows the potential state of region I II in state 8) when 15 ports are applied, and Figure 3', b) shows the potential state of region m■ when the gate is on.
Figure 3(d) shows the potential state of region I■1 when the gate is off (with a relatively small voltage applied to the pnn association diode, for example, 1 to 5 ports).
indicates the potential state of the region mlV when the gate is off.

As can be seen from FIGS. 3(a) to 3(d), the following relationship holds between the maximum potential value φl1aX of each region when the gate is on.

φ1axII>φ+1axl>φIIax■>φmar
On the other hand, the following relationship holds during gate off.

φmax ■＞ φsaxm＞ φmaxII＞
φpus ax I charge transfer is performed by repeating the ON and OFF states yg of the gate voltage (voltage applied to the ρn junction diode).

In FIG. 4, the maximum value φwax of the potential in each region is represented by a stepped pattern of potential wells. In the case of gate-on state y5, it is represented by a potential well pattern shown by a thick line, and the pattern is a four-stage potential pattern starting from region m and moving toward F to the right, with region 11 being the lowest level. There is. -・Sword,
In the gate-off state, there is a four-stage potential pattern starting from region I and moving to the right.

For example, considering the signal charge accumulated in region H,
Since φwax in region II is highest when the gate is on, electron charges are confined within this region. When gated off, φwax II and φwax I
both decrease. At this time, area IIIIV is P5 area 6
Since it is shielded from the gate potential by the inversion layer of , φ■ax DI and φn+ax IV are constant. At this point, the potential of region m becomes higher than region 11, so the signal charge moves to region (2) through region (2). The p-required region 6 forms a temporary 5-electrode. When the gate potential is lowered to the I-on state, charges flow to the region (2). In this way, heavy duty transfer is accomplished by applying pulses of width to the pn junction diode.

According to this embodiment, since a clock pulse is applied to the pn junction diode to transfer charge, there is no need to provide a gate' center pole on the semiconductor surface for applying a clock pulse as in the conventional case. When used as a device, incident light enters the semiconductor directly without passing through the gate electrode, which prevents a decrease in sensitivity due to the gate electrode.

In particular, sensitivity to blue light is improved.

In addition, since region III has a p-type region 6 and an n-type region 8, which form a diode, formed on the upper surface of the n-channel, a shallow region near the semiconductor surface is formed as shown in FIGS. The potential is small due to the p-type region 6, and furthermore, the v-potential is large due to the n-type region 8 near the semiconductor surface.
Small mountains (upward convex curves) in Figures 3 (a) and (C)
It is shown as. Therefore, due to such a mountain portion with a small potential, excess charges accumulated in the region H flow to the n portion of the surface before overflowing to the adjacent picture element portion, so that blooming can be prevented.

An embodiment of the manufacturing process of the charge transfer device of the present invention is shown in the fifth embodiment.
It is shown in figures (a) to (r).

First, as shown in Fig. 5(a), dope density 1
A p-type medium crystalline silicon substrate 2 of 12 x 1015/Cm3 is used. An oxide layer 12 is formed on the surface of this p-type substrate 2 by an oxidation method to a desired thickness, for example, 300 angstroms.

Next, as shown in FIG. 5(a), the oxide layer 12 is passed through 7
(P) with energy 200keV, il, i3 x 1
012/c+s'', which forms the n-channel portion of region I.

Next, a mask 22 with an opening in region H as shown in FIG. 5(b) is formed, and phosphorus (P) is passed through the oxide layer 12.
is implanted with an energy of 200 keV and a line 11xLθ12/c-. By this implantation and the implantation shown in FIG. 5(a), an n-channel portion in region (2) is formed.

Furthermore, a mask 24 having an opening in region (2) as shown in FIG.
) with an energy of 200 keV, 1iQ3 x 1012
This driving and Figure 5 (a) (b)
) is used to form the n-channel portion of region (2).

Furthermore, a mask 26 having an opening in the region (2) as shown in FIG.
) with an energy of 200 keV and a dose of 5 x 1012/
This input with c+w2 and Figure 5(a) (
b) The n-channel portion in region (2) is formed by the implantation in (c).

Further, as shown in FIG. 5(e), boron (B) is introduced through the oxide layer 12 at an energy of 40 keV and a line g 1!1013.
/cm'', and by this implantation, a P-type head region 6 is formed, which becomes the virtual electrode in the region ■■ and the p-type region of the pn junction in the region III.

Furthermore, a mask 28 having an opening in the region 111 as shown in FIG.
This implantation forms an n-type region 8 which becomes the n-type region of the pn junction in region I2.

Note that heat treatment is performed after each impurity is implanted, and the implanted impurity is diffused into the silicon to an appropriate depth to form a Y-island with a correct potential distribution.

In addition, using an n-type silicon substrate as a material, a p-type channel C
When manufacturing an OD, each polarity may be reversed, or a semiconductor containing a -V, n-IV compound such as indium antimonide or mercury cadmium telluride may be used.

Effects According to the present invention, since a clock pulse is applied to the pn junction diode to transfer charge, there is no need to provide a gate electrode on the semiconductor surface for applying the clock pulse as in the conventional case. When used as a semiconductor device, the incident light directly enters the semiconductor without passing through the gate or electrode, which prevents a decrease in sensitivity due to the gate electrode and improves sensitivity, especially to blue light.

Furthermore, since a peak of potential, that is, a vertical overflow drain structure is formed by the pn junction diode, blooming can be prevented.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional perspective view showing an embodiment of the charge transfer device according to the present invention, FIG. 2(a) is a graph showing the impurity concentration distribution in region III, and FIG. 2(b) is the impurity concentration distribution in region mlV. FIG. 3(a) is a graph showing the potential state of region III when the gate is on. FIG. 3(b) is a graph showing the potential state of region III TV when the gate is on. FIG. 3(C) is a graph showing the potential state of region III TV when the gate is on. Figure 3(d) is a graph showing the potential state of region III at gate-off, Figure 4 is a graph showing potential wells in each region, Figure 5 ( 1A to 1F are diagrams illustrating the manufacturing process of the load transfer device shown in FIG. 1. Explanation of symbols of main parts 298. Substrate 4 , , n-type region 8 , , P-type region 8 , , n-type region! 2. ．． ．． Oxide film patent applicant Fuji Photo Film Co., Ltd. Representative Takao Katori Figure 1

Claims (1)

[Claims] 1. A reverse conduction type buried channel including a plurality of cells is provided on one main surface of a one conductivity type semiconductor substrate, and an inverted channel formed on the semiconductor surface of a part of each cell. A charge transfer device in which a portion of each cell is selectively protected from gate-induced potential changes by a layer, the device comprising: a region of p-type conductivity and a region of n-type conductivity on the surface of each cell; 1. A charge transfer device comprising a diode formed by a charge transfer device, wherein a voltage for charge transfer is applied to the diode. 2. The device of claim 1, wherein the diode is formed on an unprotected surface of each cell, and a region of the diode with opposite polarity to the channel is continuous with the inversion layer. A charge transfer device characterized in that: 3. A charge transfer device according to claim 1, wherein the semiconductor substrate is p-type silicon and the buried channel exhibits n-type conductivity. 4. The device according to claim 1, wherein each cell includes four regions with different impurity concentrations, and only the third region and the fourth region are selectively protected by the inversion layer. charge transfer device.