JPS6228620B2 - - Google Patents

Info

Publication number
JPS6228620B2
JPS6228620B2 JP56053842A JP5384281A JPS6228620B2 JP S6228620 B2 JPS6228620 B2 JP S6228620B2 JP 56053842 A JP56053842 A JP 56053842A JP 5384281 A JP5384281 A JP 5384281A JP S6228620 B2 JPS6228620 B2 JP S6228620B2
Authority
JP
Japan
Prior art keywords
circuit
counter
signal
clock
frame synchronization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56053842A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57168549A (en
Inventor
Masakazu Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56053842A priority Critical patent/JPS57168549A/ja
Publication of JPS57168549A publication Critical patent/JPS57168549A/ja
Publication of JPS6228620B2 publication Critical patent/JPS6228620B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/04Speed or phase control by synchronisation signals
    • H04L7/08Speed or phase control by synchronisation signals the synchronisation signals recurring cyclically

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP56053842A 1981-04-10 1981-04-10 Digital synchronizing circuit Granted JPS57168549A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56053842A JPS57168549A (en) 1981-04-10 1981-04-10 Digital synchronizing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56053842A JPS57168549A (en) 1981-04-10 1981-04-10 Digital synchronizing circuit

Publications (2)

Publication Number Publication Date
JPS57168549A JPS57168549A (en) 1982-10-16
JPS6228620B2 true JPS6228620B2 (uk) 1987-06-22

Family

ID=12954025

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56053842A Granted JPS57168549A (en) 1981-04-10 1981-04-10 Digital synchronizing circuit

Country Status (1)

Country Link
JP (1) JPS57168549A (uk)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01111055U (uk) * 1988-01-21 1989-07-26

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01111055U (uk) * 1988-01-21 1989-07-26

Also Published As

Publication number Publication date
JPS57168549A (en) 1982-10-16

Similar Documents

Publication Publication Date Title
US5864250A (en) Non-servo clock and data recovery circuit and method
JPH0150150B2 (uk)
KR100249718B1 (ko) 시간 간격 측정 시스템 및 시간 간격 측정 방법
US4453157A (en) Bi-phase space code data signal reproducing circuit
JPS6228620B2 (uk)
JPH0748725B2 (ja) フレーム同期回路
US7321647B2 (en) Clock extracting circuit and clock extracting method
US5101419A (en) Fixed duty cycle clock generator
JP2906966B2 (ja) パルス切換回路
US4741005A (en) Counter circuit having flip-flops for synchronizing carry signals between stages
JP3154302B2 (ja) 位相差検出回路
JPH0644756B2 (ja) 同期クロツク発生回路
JPH1168861A (ja) 同時双方向送受信方法および同時双方向送受信回路
KR0172459B1 (ko) 클럭재생방법 및 장치
JP3037209B2 (ja) 位相差検出回路
JPS6224736A (ja) スタツフ同期回路
TW294873B (en) Decoding apparatus for manchester code
KR950004542Y1 (ko) 서브코드 인터페이스 회로
JP3382020B2 (ja) 信号発生器用タイミング制御回路
JPH03204251A (ja) クロック同期回路
KR100333717B1 (ko) 입력신호의에지검출을이용한클럭발생장치
JP3514020B2 (ja) レート発生器
JPH05136774A (ja) クロツク乗換回路
JPH05347555A (ja) 可変分周回路
JPH03255743A (ja) ビット同期回路