JPS6228183U - - Google Patents
Info
- Publication number
- JPS6228183U JPS6228183U JP11806985U JP11806985U JPS6228183U JP S6228183 U JPS6228183 U JP S6228183U JP 11806985 U JP11806985 U JP 11806985U JP 11806985 U JP11806985 U JP 11806985U JP S6228183 U JPS6228183 U JP S6228183U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- lead wires
- wires connected
- test clip
- measured
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005259 measurement Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 4
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
第１図ａは本考案の一実施例を示す平面図、同
図ｂはその正面図、同図ｃは側面図、第２図は測
定時の信号系路を説明するためのブロツク図、第
３図は従来例による測定方法を示すブロツク図、
第４図は被測定集積回路の構成例を示す回路図、
第５図は従来例による測定時の信号系路を示すブ
ロツク図である。
１……被測定ＩＣ、３……測定器、１１……テ
ストクリツプ、１４……バツフア素子、１５，１
６……リード線。
FIG. 1a is a plan view showing an embodiment of the present invention, FIG. 1b is a front view thereof, FIG. 1c is a side view, FIG. 2 is a block diagram for explaining the signal path during measurement, and FIG. Figure 3 is a block diagram showing a conventional measurement method.
FIG. 4 is a circuit diagram showing an example of the configuration of the integrated circuit under test;
FIG. 5 is a block diagram showing a signal path during measurement according to a conventional example. 1... IC to be measured, 3... Measuring instrument, 11... Test clip, 14... Buffer element, 15, 1
6... Lead wire.
Claims (1)
を測定するための集積回路用テストクリツプにお
いて、測定側に接続するリード線と被測定側に接
続するリード線との間にバツフア素子を挿入した
ことを特徴とする集積回路用テストクリツプ。 In an integrated circuit test clip for measuring the output signal of an integrated circuit mounted on a board, a buffer element is inserted between the lead wires connected to the measurement side and the lead wires connected to the side to be measured. A test clip for integrated circuits featuring:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11806985U JPS6228183U (en) | 1985-08-02 | 1985-08-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11806985U JPS6228183U (en) | 1985-08-02 | 1985-08-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6228183U true JPS6228183U (en) | 1987-02-20 |
Family
ID=31004171
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11806985U Pending JPS6228183U (en) | 1985-08-02 | 1985-08-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6228183U (en) |
-
1985
- 1985-08-02 JP JP11806985U patent/JPS6228183U/ja active Pending
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