JPS62278852A - Phase synchronizing filter - Google Patents

Abstract

PURPOSE:To prevent the jitter and level fluctuation of a filter circuit output signal regardless of the height of a reference clock frequency by setting so that the ratio of the frequency of the reference clock to the frequency of an input signal can be equal to the ratio of the frequency of the reference clock to the central frequency of a filter circuit. CONSTITUTION:A central frequency f0 is made into 1/L of a reference clock frequency fc, a filter circuit 1, in which a band width is BW, a waveform shaping circuit 2, and a phase locked loop circuit PLL3, which a reference clock generating circuit to generate the reference clock of the frequency fc of N times of an input signal frequency fi, are connected in the sequence and the reference clock outputted by a PLL circuit 3 is inputted to a filter circuit 1. A ratio N of the frequency fc of the reference clock outputted by the PLL circuit 3 to the frequency fi of the input signal inputted through the filter circuit 1 is set so as to come to be equal to a ratio L of the frequency fc of the reference clock to the central frequency f0 of the filter circuit 1. Thus, the central frequency f0 of the filter circuit 1 is made coincident to the frequency fi of the input signal and the phase of the reference clock is synchronized to the phase of the input signal.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a phase synchronization filter used for tone signal detection in a communication device equipped with tone decoder and transponder functions. be.

[Prior art]

As a conventional filter, there is, for example, a capacitor switching type digital filter shown in FIG. This filter is
The input terminal 21 is connected to a plurality of sampling capacitors 23 and an output terminal 24 via a resistor 22, and the sampling capacitors 23 are connected to a reference clock whose frequency is divided by a counter 25 and which is further divided by a decoder 26. The selection is sequentially switched by the decoded selection signal. When a signal as shown in Fig. 4(a) is input to this filter, it outputs a staircase wave as shown in Fig. 4(b), but there is a beat due to the difference between the center frequency of the filter and the input signal frequency. Therefore, waveform fluctuations as shown in FIGS. 3(b) and 3(c) occur. Therefore, the output signal includes a shifter and a level fluctuation, and has the drawback of increasing unnecessary noise components when determining the frequency and level of the tone signal. To improve this drawback, increase the reference clock frequency of the filter to make the staircase waveform finer.
Methods such as applying the filter output to an analog filter to perform waveform shaping have been used, but these methods have not been sufficiently effective due to limitations in the reference lock frequency.

Another conventional filter is a switched capacitor filter shown in FIG. This filter has 2
Set of sampling capacitors 31, 31, amplifier 32,
32 and feedback capacitors 33. and,
The sampling capacitor 31 is switched to the input terminal 34 side and the amplifier 32 side by the reference clock,
With respect to the input waveform shown in FIG. 6(a), the output waveform is shown in FIG. 6(b), but it has the same drawbacks as the filter shown in FIG. 4.

[Purpose of the invention]

The present invention has been made in consideration of the above-mentioned conventional problems, and it prevents jitter and level fluctuation of the filter circuit output signal regardless of the high or low reference clock frequency, and enables frequency determination and level determination of tone signals. The object of the present invention is to provide a phase synchronization filter that reduces unnecessary noise components in the process.

[Structure of the invention]

In order to achieve the above object, the phase synchronized filter according to the present invention includes a filter circuit that determines the center frequency based on a reference clock frequency, and the above-mentioned filter circuit that is synchronized with an input signal inputted through this filter circuit. a reference clock generating circuit that generates a reference clock of 1, and the ratio of the frequency of the reference clock output from the reference clock ordering circuit to the frequency of the input signal is equal to the ratio of the frequency of the reference clock to the center frequency of the filter circuit. By setting the center frequency of the filter circuit to match the input signal of the filter circuit and synchronizing the phase of the reference clock, the occurrence of beat can be suppressed, regardless of the high or low frequency of the reference clock. The filter circuit is characterized in that it is configured to prevent jitter and level fluctuations in the output signal, and to reduce unnecessary noise components when determining the frequency and level of a tone signal.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

As shown in FIG. 1, the phase synchronized filter of the present invention has a center frequency f0 set to a reference clock frequency r.

A phase-locked loop that is a reference clock generation circuit that generates a reference clock with a frequency fe that is N times the input signal frequency f, a filter circuit 1 whose bandwidth is BW, and a waveform shaping circuit 2. Circuit 3 (hereinafter referred to as PL
The reference clock output from the PLL circuit 3 is input to the filter circuit 1.

However, the ratio N of the frequency f of the reference clock output from the PLL circuit 3 to the frequency "," of the input signal that is input after passing through the filter circuit 1 is the frequency fc of the reference clock relative to the center frequency f0 of the filter circuit 1. is set to be equal to the ratio of

Further, in this filter, the bandwidth BW of the filter circuit 1 is variable, and a bandwidth control signal based on the synchronization detection signal of the PLL circuit 3 is input to the filter circuit 1, and the bandwidth BW is changed according to this signal. It is determined.

A specific embodiment of the block diagram shown in FIG. 1 is as shown in FIG. 2, and the filter circuit 1 in FIG. It consists of a sampling capacitor 7 . The waveform shaping circuit 2 includes a bandpass filter 13 and a comparator 14. P.L.
The L circuit 3 includes a PLL integrated circuit 15 and a low pass filter 17 comprising a diode 16 for generating a bandwidth control signal.
and an inverter 18, and the phase comparison input of the PLL integrated circuit 15 is input from the counter 10 of the filter circuit 1.

Further, the multiplexer 9, counter 10, analog switch 12, PLL integrated circuit 15, and inverter 18 each include a standard CMOS logic integrated circuit.
51.4040.4066.4046 and 4049 are used.

In the above configuration, the center frequency f0 of the filter circuit 1
The ratio of the reference clock frequency fc to the reference clock frequency fc is L=fc/
f0=8, and an input signal having a frequency r that has passed through the filter circuit 1 is waveform-shaped by the waveform shaping circuit 2 and then inputted to the PLL circuit 3 as a synchronizing signal. The PLL circuit 3 uses the output reference clock as the counter 1 of the filter circuit 1.
By using the signal frequency-divided by 8 by 0 as the phase comparison input, the frequency fcO ratio N of the reference clock output from the PLL circuit 3 to the frequency f of the input signal is N=fc/f
Positive=8, and L and N are equal.

As a result, the center frequency f0 of the filter circuit 1 is f,
= (1/L) ・fc= (1/L) ・N・f
i=(1/8)x8xr==ji, which matches the frequency f1 of the input signal, and the phase of the reference clock is synchronized with the phase of the input signal.

Further, in this embodiment, when the output signal is synchronized with the input signal in the PLL circuit 3, a synchronization detection signal is output from the PLL integrated circuit 15, and this synchronization detection signal is passed through the low-pass filter 17 including the diode 16 and the inverter 18. Output as a bandwidth control signal. On the other hand, in the filter circuit 1, the analog switch 12 is first closed;
The bandwidth BW of the filter circuit 1 is: However, when the above-mentioned bandwidth control signal is input, the analog switch 12 is closed, and the bandwidth BW of the filter circuit 1 is narrowed as follows: BW=(LπCR)-'. Therefore, it is possible to improve the ability to eliminate input noise components other than phase-synchronized input signals.

〔Effect of the invention〕

As described above, the phase synchronized filter according to the present invention includes a filter circuit whose center frequency is determined by a reference clock frequency, and a reference clock which generates a reference clock for the filter circuit synchronized with an input signal inputted through this filter circuit. and a frequency ratio of the reference clock output from the reference clock generation circuit to the frequency of the input signal is set to be equal to a ratio of the frequency of the reference clock to the center frequency of the filter circuit. Σ. This has the effect of preventing shift and level fluctuation of the filter circuit output signal regardless of the high or low reference clock frequency, and reducing unnecessary noise components when performing frequency and level determination of tone signals.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIGS. 1 and 2 show an embodiment of the present invention, in which FIG. 1 is a block diagram showing a phase-locked filter, and FIG.
The figure is a circuit diagram showing details of a phase-locked filter, Figure 3 is a circuit diagram showing a conventional example, and Figures 4 (a), (b), and (c) are input signals and outputs of the filter shown in Figure 3. Graph showing signals, Figure 5 is a circuit diagram showing another conventional example, Figure 6 (a)
(b) is a graph showing the input signal and output signal of the filter shown in FIG. 5; 1 is a filter circuit, 2 is a waveform shaping circuit, and 3 is a phase filter circuit.
This is a locked loop circuit (reference clock generation circuit). Patent Applicant: Sharp Co., Ltd. Figure 3 $ 5 Figure Two Swords -----------1 -, --m-→] to -4 mouths/g Figure 4 (a) Input ~ ( b) Upper rゝh1゜Figure 6 (a) Input /''\, -27 (b) Upper blade ~

Claims (1)

[Claims] 1. A filter circuit that determines the center frequency based on a reference clock frequency, and a reference clock generation circuit that generates a reference clock for the filter circuit synchronized with an input signal input through this filter circuit, A phase synchronization filter characterized in that the ratio of the frequency of the reference clock output from the reference clock generation circuit is set to be equal to the ratio of the frequency of the reference clock to the center frequency of the filter circuit.