JP2560113B2 - Data demodulation circuit - Google Patents

Description

The present invention relates to a data demodulation circuit, and more particularly to a data demodulation circuit using a digital phase locked loop (DPLL) circuit.

[Prior Art] For example, in a digital audio interface (DAI) that functions when transmitting a digital audio signal from a CD player device to a main amplifier device, the main amplifier device correctly receives the transmitted digital audio signal. Thus, the data demodulation circuit is provided.

FIG. 3 shows a conventional data demodulation circuit. In FIG. 3, the input digital data (serial signal) is
The D-type flip-flop circuit 1 and the first analog configuration
It is given to the PLL circuit 2. The first PLL circuit 2 has a small time constant, forms a clock signal that follows input data, and supplies it to the second PLL circuit 3 having an analog structure. The second PLL circuit 3 is selected to have a large time constant, and stabilizes the frequency of the clock signal and outputs it.

As described above, the PLL circuit 2 having a small time constant and the PLL circuit 3 having a large time constant are combined to form a clock signal having good followability with respect to input data and being stable, and giving it to the D-type flip-flop circuit 1. . Thus, D
The demodulated data is taken out from the flip-flop circuit 1.

In this case, when it is detected that the data output from the D-type flip-flop circuit 1 is an error, the time constant of the second PLL circuit 3 is changed to a small amount so as to follow the error.

[Problems to be Solved by the Invention] However, when the analog PLL circuits 2 and 3 are used, even if the time constant is made small, it is not possible to achieve a quick response to follow a rapid change.

Therefore, it is conceivable to apply a so-called DPLL circuit having a very small time constant and a very fast response to the data demodulation circuit. The DPLL circuit demodulates the data by sampling the input data with the first clock signal which is an integer fraction of the bit period and fetching the sampled data with the second clock signal obtained by dividing the first clock signal. In addition, the frequency division ratio is immediately changed according to the bit period of the sampling data to change the period of the second clock signal to accelerate the response.

However, since the DPLL circuit is adapted to respond to an abrupt change by changing the frequency division ratio for the first clock signal in accordance with the bit period of the data, the period of the second clock signal is the first It changes with the cycle of the clock signal. Therefore, it is unavoidable that the demodulated data has a time axis fluctuation within a range of ± 1 cycle of the first clock signal. That is, the DPLL circuit demodulates the input data with good response by causing the generated second clock signal to have jitter (time-axis fluctuation).

For data demodulation where jitter is not a problem, DPLL
Although it is preferable to apply a circuit, the DPLL circuit is not suitable for demodulating data such as a digital audio signal that causes a harmful effect such as jitter, so that the digital audio signal is conventionally used. As described above, the configuration using two stages of analog PLL circuits has been applied to the data demodulation circuit of.

The present invention has been made in consideration of the above points,
An object of the present invention is to provide a data demodulation circuit which can enjoy the advantage that the response of the DPLL circuit is fast and solves the problem caused by the jitter component that occurs when the DPLL circuit is used.

[Means for Solving the Problem] In order to solve the problem, according to the present invention, a sampling circuit that samples input data with a first clock signal that is an integer fraction of a 1-bit period of the input data is sampled. A data demodulation circuit body that takes in data with a second clock signal, a variable frequency divider circuit that divides the first clock signal to form a second clock signal, and a bit period of the sampled data is monitored. , If the period is shorter than the reference period, the variable divider circuit outputs an up command signal to increase the dividing ratio, and if it is longer than the reference period, the variable divider circuit outputs a down command signal to decrease the dividing ratio. A ratio control circuit, a clock generator that controls a frequency based on a clock frequency control signal to generate a first clock signal, an up command signal, and a down command. And a clock frequency control circuit for detecting a change tendency of the input data on the time axis based on the command signal to form a clock frequency control signal and supplying the clock frequency control signal to the clock generator.

[Operation] In the present invention, basically, the sampling circuit samples the input data according to the first clock signal generated by the clock generator, and the first clock signal is frequency-divided via the variable frequency dividing circuit. The data sampled by the second clock signal obtained in this way is taken in and demodulated.

Here, the division ratio control circuit monitors the bit period of the sampling data by comparing the phase of the pulse signal corresponding to the second clock signal with the phase of the sampling data, and changes the bit period when the sampling period is shorter than the reference period. An up command signal for increasing the frequency dividing ratio is output to the frequency dividing circuit, and a down command signal for decreasing the frequency dividing ratio is output to the variable frequency dividing circuit when the frequency dividing period is longer than the reference period to control the frequency dividing ratio. Ie DP
An LL circuit is formed to change the cycle of the second clock signal and output demodulated data that immediately follows the change of the input data.

Even in this case, the cycle of the second clock signal is set to the first
Can be changed only in units of the cycle of the clock signal, and the demodulated data will have jitter if this is left as it is. Therefore, the clock frequency control circuit detects the change tendency of the input data on the time axis based on the up command signal and the down command signal, forms a clock frequency control signal, and supplies the clock frequency control signal to the clock generator. The frequency of is also changed. Thus, the demodulated data is prevented from having a jitter component.

Embodiment An embodiment of the present invention will be described in detail below with reference to the drawings.

In FIG. 1, input data DIN is supplied to a D flip-flop circuit 10 for sampling. The flip-flop circuit 10 is supplied with a first clock signal CK1 from a voltage controlled clock oscillator (VCXO) 11 described later. In the case of this embodiment, the clock signal CK1 is 1/6 of the normal bit period of the input data that has not been subjected to jitter or the like.
Of the reference period (this period changes as will be described later).

The digital data D2 whose waveform is shaped through such sampling is given to the data input terminal of the demodulation D-type flip-flop circuit 12. The clock input terminal of the flip-flop circuit 12 has a variable frequency divider circuit 13 described later.
Is supplied with the second clock signal CK2, sampling data D2 is taken in by the clock signal CK2 and demodulated data DOUT is taken out, and is given to the next processing circuit together with the second clock signal CK2.

Here, the variable frequency dividing circuit 13 is the flip-flop circuit 10
The first clock signal CK1 is normally divided by 1/6, that is, it forms the second clock signal CK2 having the bit period of the input data DIN, and the divided clock signal CK2 The timing of is located in the middle of the sampled data.

However, since the cycle of the input data DIN is changing,
In such a simple formation of the second clock signal CK2, it may not be possible to accurately demodulate. Therefore, input data DI
A configuration is provided that changes the timing of the second clock signal CK1 according to the variation of N.

The data D2 from the flip-flop circuit 10 synchronized with the first clock signal CK1 is given to the edge detection circuit 14. The edge detection circuit 14 is also supplied with the first clock signal CK1 from the clock generator 11. The edge detection circuit 14 forms an edge detection signal ED having a pulse width for one cycle of the clock signal CK1 to generate a frequency division ratio control circuit.
Give to 15.

The frequency division ratio control circuit 15 is supplied with the pulse signal PCK2 frequency-divided from the variable frequency division circuit 13 and the first clock signal CK1 from the clock generator 11. Pulse signal PCK2
Has a basic waveform of the second clock signal from the previous detection edge (a pulse having a duty ratio of 50% and having a cycle six times that of the first clock signal).

The frequency division ratio control circuit 15 compares the phase of the pulse signal PCK2 with the edge detection signal ED, and outputs the up command signal UP and the down command signal DW to the variable frequency divider circuit 13 according to the phase difference.

For example, when the edge detection signal ED changes from a state of maintaining 6 clock cycles to a cycle of 5 clocks, it is detected by the phase comparison with the pulse signal PCK2 that the cycle is shortened, and the variable frequency dividing circuit 13 divides the frequency. The ratio of the first clock signal CK1
The up command signal UP that increases by one cycle of is output,
After that, if there are 5 clock cycles, the up command signal UP is output each time. Further, when the edge detection signal ED changes from the state of maintaining 6 clock cycles to 7 clock cycles, it is detected by the phase comparison with the pulse signal PCK2 that the cycle has become longer, and the variable frequency dividing circuit 13 performs frequency division. Down command signal D that reduces the ratio by one cycle of the first clock signal CK1
W is output and the down command signal DW is output each time after that for 7 clock cycles.

In this way, the second clock signal CK2 having a cycle corresponding to the output data D2 from the flip-flop circuit 10 is formed, and the data demodulation D-type flip-flop circuit 12 demodulates the data DOUT.

The configuration described above is a so-called DPLL circuit.

However, with this alone, the second clock signal CK2 given to the data demodulation D-type flip-flop circuit 12 is
It can change only in one cycle of the first clock signal CK1, and may differ from the original data phase by the phase up to ± 1 cycle. That is, although the logical level of the data DIN is correctly demodulated through the data demodulation,
The phase of demodulated data DOUT is input data DI through demodulation processing.
It will have jitter that does not necessarily match the N phase.

Therefore, there is provided a configuration that does not have a jitter component even when demodulating while maintaining such a fast response.

The up command signal UP is given to the AND circuit 21 via the inverter circuit 20 and directly to the OR circuit 22. On the other hand, the down command signal DW is directly applied to the AND circuit 21 and the OR circuit 22. The output pulse signal AP from the AND circuit 21 is given as an input signal to the 3-state buffer circuit 23, and the output pulse signal OP of the OR circuit 22 is given to the 3-state buffer circuit 23 as a state control signal. The pulse signal AP from the AND circuit 21 has the same waveform as the down command signal DW and seems to have a useless nature, but is configured to have a predetermined logic level.

Therefore, the three-state buffer circuit 23 outputs the down command signal DW while the up command signal UP and the down command signal DW are being output, and is in a high impedance state when neither is output. Here, the buffer circuit 23 lowers the passed logic “L” level from the high impedance state level, and sets the passed logic “H” level higher than the high impedance state level. It is selected such that the low level and the high level are symmetrical with respect to the state level.

With this configuration, when the up command signal UP is output, a pulse having a level lower than the high impedance state level is output for the pulse width period, and the down command signal UP is output.
When DW is output, the pulse signal BP having a level higher than the high impedance state level is output for the pulse width period.

Such an output signal BP is passed through the resistance circuit 24 for high impedance state level regulation to the low pass filter circuit.
Given to 25.

The low-pass filter circuit 25 integrates this and gives the output signal INT to the voltage-controlled clock oscillator 11. The clock oscillator 11 includes a variable capacitance diode 30, an inverter circuit 31, a crystal oscillator 32, and a capacitor 33, and generates a first clock signal CK1 having a frequency according to the input voltage level INT. That is, the first clock signal CK1 whose frequency is changed according to the time-axis fluctuation tendency of the input data DIN is output.

In the above configuration, if the time axis of the input data DIN shifts to the shorter one, the flip-flop circuit 10
The sampling data D2 output from will have 5 clock cycles instead of the original 6 clock cycles.
The up command signal UP is output, the division ratio is increased, and the second clock signal CK2 for demodulation is changed to the first clock signal CK1.
Therefore, the data is correctly demodulated.

In such a state, the up command signal UP is continuously generated as shown in the first half of FIG. 2 (A), and the outputs AP and OP of the AND circuit 21 and the OR circuit 22 are shown in FIG. 2 (C) and (D). ), The buffer circuit 23 outputs the signal BP which takes the logic "L" only during the up command period. Thus, the low-pass filter circuit 25 outputs the voltage signal INT lower than the reference level to increase the frequency of the first clock signal CK1.

That is, as the time axis of the input data DIN becomes shorter, the cycle of the first clock signal CK1 becomes shorter, and the second cycle has a cycle that is 1/6 of the bit cycle of the input data DIN that has become shorter. Clock signal CK2 is generated and demodulated. In this way, the generation of the jitter component is prevented.

When the time axis of the input data DIN becomes longer from the stable state of the time axis, the sampling data D2 output from the flip-flop circuit 10 becomes 7 clock cycles instead of 6 clock cycles, and the down command signal DW becomes Second clock signal for demodulation, which is output and has a reduced division ratio
CK2 has 7 clock cycles of the first clock signal CK1, and the data is correctly demodulated except for the phase.

In such a state, the down command signal DW is continuously generated as shown in the latter half of FIG. 2 (B), and the outputs AP and OP of the AND circuit 21 and the OR circuit 22 are shown in FIGS. 2 (C) and (D). ), The buffer circuit 23 outputs the signal BP which takes the logic "H" only during the down command period. Thus, the low-pass filter circuit 25 outputs the voltage signal INT higher than the reference level to lower the frequency of the first clock signal CK1.

That is, as the time axis of the input data DIN becomes longer, the cycle of the clock signal CK1 becomes longer, and the second clock signal CK2 having a cycle of 1/6 is generated for the input data DIN having the longer cycle. To be done. In this way,
It also prevents the generation of jitter.

Therefore, according to the above-described embodiment, the frequency division ratio can be varied to immediately respond to the time base fluctuation of the input data, and at the same time, it is possible to detect the tendency of the frequency division ratio to increase or decrease.
Since the frequency of the clock signal itself is also controlled, it is possible to perform data demodulation with good responsiveness and without causing a jitter component.

Note that the present invention is particularly suitable for application to a digital audio signal demodulation circuit in which jitter is a problem, but can be applied to various data demodulation circuits.

The configuration of the voltage controlled clock oscillator is not limited to that shown in the embodiments.

As described above, according to the present invention, the DPLL circuit is used, and the frequency of the first clock signal is also changed based on the generation tendency of the up command signal and the down command signal. Therefore, it is possible to obtain an excellent data demodulation circuit that can prevent the demodulated data from having a jitter component while maintaining the responsiveness advantage when the DPLL circuit is used.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a data demodulating circuit according to the present invention, FIG. 2 is a timing chart of respective parts of a clock frequency control configuration, and FIG. 3 is a block diagram showing a conventional circuit. 10 ... D-type flip-flop circuit for sampling, 11 ...
… Voltage control type clock oscillator, 12 …… D-type flip-flop circuit for data demodulation, 13 …… Variable frequency divider circuit, 14 …… Edge detection circuit, 15 …… Division ratio control circuit, 20 …… Inverter circuit, 21 …… And circuit, 22 …… OR circuit, 23 …… 3
State buffer circuit, 25 ... Low-pass filter circuit.

Claims (1)

(57) [Claims] 1. A sampling circuit for sampling input data with a first clock signal which is an integer fraction of a 1-bit period thereof; a data demodulation circuit main body for fetching sampled data with a second clock signal; A variable frequency divider circuit that divides the first clock signal to form a second clock signal and a bit period of the sampled data is monitored. Output the up command signal to increase the frequency, and if it is longer than the reference period, output the down command signal to the variable frequency dividing circuit to decrease the frequency division ratio. A clock generator that controls the clock signal to generate the first clock signal, and the time of the input data based on the up command signal and the down command signal. Data demodulation circuit detects the change tendency of the shaft to form the clock frequency control signal, characterized in that a clock frequency control circuit for applying to the clock generator.