JPS622775Y2 - - Google Patents
Info
- Publication number
- JPS622775Y2 JPS622775Y2 JP1981160053U JP16005381U JPS622775Y2 JP S622775 Y2 JPS622775 Y2 JP S622775Y2 JP 1981160053 U JP1981160053 U JP 1981160053U JP 16005381 U JP16005381 U JP 16005381U JP S622775 Y2 JPS622775 Y2 JP S622775Y2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- resin layer
- integrated circuit
- semiconductor element
- sealing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 20
- 238000007789 sealing Methods 0.000 claims description 18
- 229920005989 resin Polymers 0.000 claims description 14
- 239000011347 resin Substances 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 11
- 229920002050 silicone resin Polymers 0.000 claims description 5
- 241000237509 Patinopecten sp. Species 0.000 claims description 2
- 235000020637 scallop Nutrition 0.000 claims description 2
- 238000000034 method Methods 0.000 claims 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 5
- 229910052799 carbon Inorganic materials 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000004840 adhesive resin Substances 0.000 description 1
- 229920006223 adhesive resin Polymers 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/298—Semiconductor material, e.g. amorphous silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
Description
【考案の詳細な説明】 本考案は混成集積回路の封止構造に関する。[Detailed explanation of the idea] The present invention relates to a sealing structure for a hybrid integrated circuit.
従来の混成集積回路は第１図に示す如く、表面
をアルマイト処理したアルミニウム基板等の混成
集積回路基板１と、該基板１上に設けた銅箔より
成る所望の導電路２と、導電路２上に銀ペースト
等で固着した半導体素子３と、所望の導電路２間
に設けたチツプコンデンサー４やスクリーン印刷
したカーボン抵抗体５と、半導体素子３を保護す
るエポキシ樹脂層６と、基板１を覆い基板１の周
端部に接着樹脂７により接着された樹脂製の蓋体
８より構成されている。 As shown in FIG. 1, a conventional hybrid integrated circuit includes a hybrid integrated circuit substrate 1 such as an aluminum substrate whose surface is anodized, a desired conductive path 2 made of copper foil provided on the substrate 1, and a conductive path 2 provided on the substrate 1. A semiconductor element 3 fixed with silver paste or the like on top, a chip capacitor 4 provided between desired conductive paths 2 and a screen-printed carbon resistor 5, an epoxy resin layer 6 for protecting the semiconductor element 3, and a substrate 1. It consists of a resin lid 8 bonded to the peripheral edge of the cover substrate 1 with an adhesive resin 7.
斯上した封止構造では基板１の周端部に蓋体８
を接着するスペースが必要であり、小型化する場
合の障害となる。特にカーボン抵抗体５等を保護
するシリコンレジン９が基板１の周端部にまで流
れると蓋体８の接着が不可能となるので、カーボ
ン抵抗体５等の設ける位置を基板１の内部にしな
ければならず、設計上の制約となり小型化の障害
となつている。 In the above-mentioned sealing structure, a lid body 8 is provided at the peripheral edge of the substrate 1.
This requires space for bonding, which is an obstacle when downsizing. In particular, if the silicone resin 9 that protects the carbon resistor 5 etc. flows to the peripheral edge of the substrate 1, adhesion of the lid 8 becomes impossible, so the carbon resistor 5 etc. must be placed inside the substrate 1. However, this is a design constraint and an obstacle to miniaturization.
本考案は斯点に鑑みてなされ、従来の欠点を完
全に除去した混成集積回路の封止構造を実現する
ものである。以下に第２図を参照して本考案の一
実施例を詳述する。 The present invention has been devised in view of this point, and is intended to realize a sealing structure for a hybrid integrated circuit that completely eliminates the conventional drawbacks. An embodiment of the present invention will be described in detail below with reference to FIG.
本考案は第２図に示す如く、表面をアルマイト
処理したアルミニウム基板等の混成集積回路基板
１１と、該基板１１上に設けた銅箔より成る所望
の導電路１２と、導電路１２上に銀ペースト等で
固着した半導体素子１３と、所望の導電路１２間
に設けたチツプコンデンサー１４やスクリーン印
刷したカーボン抵抗体１５と、半導体素子１３を
保護するエポキシ樹脂等の封止構脂層１６と、基
板１１を覆う樹脂製等の蓋体１７より構成されて
いる。 As shown in FIG. 2, the present invention includes a hybrid integrated circuit board 11 such as an aluminum board whose surface has been anodized, a desired conductive path 12 made of copper foil provided on the board 11, and a silver conductive path 12 on the conductive path 12. A semiconductor element 13 fixed with paste or the like, a chip capacitor 14 or a screen-printed carbon resistor 15 provided between a desired conductive path 12, and a sealing resin layer 16 made of epoxy resin or the like that protects the semiconductor element 13. It is comprised of a lid body 17 made of resin or the like that covers the substrate 11 .
本考案の特徴は封止樹脂層１６にある。この封
止樹脂層１６は半導体素子１３を被覆して約2.0
mmの高さになる様にポツテイングされる。なお、
封止樹脂層１６の周囲への流れを防止するために
半導体素子１３を囲む様にシリコンレジン層１８
をスクリーン印刷して基板１１表面に付着する。
この際にカーボン抵抗体１５などの上にも保護の
ためにシリコンレジン層１８を設けると良い。 The feature of the present invention lies in the sealing resin layer 16. This sealing resin layer 16 covers the semiconductor element 13 and has a thickness of approximately 2.0 mm.
It is potted to a height of mm. In addition,
A silicone resin layer 18 is formed around the semiconductor element 13 to prevent the sealing resin layer 16 from flowing to the periphery.
is attached to the surface of the substrate 11 by screen printing.
At this time, it is preferable to provide a silicone resin layer 18 on the carbon resistor 15 and the like for protection.
封止樹脂層１６の硬化前に2.0mmより若干低い
蓋体１７を基板１１を覆う様に所定の位置に配置
すると、封止樹脂１６は貝柱状に蓋体１７にも付
着する。この状態で封止樹脂層１６の硬化処理を
行うと、蓋体１７は基板１１に固着できる。 When the lid 17, which is slightly lower than 2.0 mm, is placed in a predetermined position so as to cover the substrate 11 before the sealing resin layer 16 is cured, the sealing resin 16 also adheres to the lid 17 in a scallop shape. If the sealing resin layer 16 is cured in this state, the lid 17 can be fixed to the substrate 11.
斯る本考案の封止構造では蓋体１７を封止樹脂
層１６で固着しているので、基板１１のほぼ中央
付近に半導体素子１３を配置するだけで良く、基
板１１周端部での蓋体１７の基板１１への接着性
はほとんど問題とならないので基板１１の周端ま
で自由に回路を形成でき小型化に寄与できる。ま
た従来では封止樹脂層の硬化と蓋体の接着は２工
程に分けて行つていたのが、本考案に依れば同時
に行なえるので量産性を向上できる。 In the sealing structure of the present invention, since the lid 17 is fixed with the sealing resin layer 16, it is only necessary to arrange the semiconductor element 13 near the center of the substrate 11, and the lid at the peripheral edge of the substrate 11 is not required. Since the adhesion of the body 17 to the substrate 11 is hardly a problem, circuits can be formed freely up to the peripheral edge of the substrate 11, contributing to miniaturization. Furthermore, conventionally the curing of the sealing resin layer and the adhesion of the lid were carried out in two steps, but according to the present invention they can be carried out simultaneously, thereby improving mass productivity.
第１図は従来例を説明する断面図、第２図は本
考案を説明する断面図である。
主な図番の説明、１１は混成集積回路基板、１
２は導電路、１３は半導体素子、１６は封止樹脂
層、１７は蓋体、１８はシリコンレジン層であ
る。
FIG. 1 is a sectional view illustrating a conventional example, and FIG. 2 is a sectional view illustrating the present invention. Explanation of main drawing numbers, 11 is a hybrid integrated circuit board, 1
2 is a conductive path, 13 is a semiconductor element, 16 is a sealing resin layer, 17 is a lid, and 18 is a silicone resin layer.
Claims (1)
該導電路上に半導体素子及びチツプ部品を固着
した混成集積回路において、前記半導体素子の
みを保護する封止樹脂層で前記基板を覆う蓋体
を前記基板に貝柱状に固着することを特徴とす
る混成集積回路の封止構造。 ２ 実用新案登録請求の範囲第１項に於いて、前
記半導体素子を囲む様に前記基板表面にシリコ
ンレジン層を設け前記封止樹脂層の流れを防止
することを特徴とする混成集積回路の封止構
造。[Claims for Utility Model Registration] 1. Providing a desired conductive path on a hybrid integrated circuit board,
A hybrid integrated circuit in which a semiconductor element and a chip component are fixed on the conductive path, characterized in that a lid body that covers the substrate with a sealing resin layer that protects only the semiconductor element is fixed to the substrate in a scallop shape. Sealing structure of integrated circuit. 2 Utility Model Registration Claim 1 provides a method for sealing a hybrid integrated circuit, characterized in that a silicone resin layer is provided on the surface of the substrate so as to surround the semiconductor element to prevent the sealing resin layer from flowing. Stop structure.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1981160053U JPS5866646U (en) | 1981-10-26 | 1981-10-26 | Sealing structure of hybrid integrated circuit |
| KR2019820003095U KR860000239Y1 (en) | 1981-10-26 | 1982-04-20 | Mould in compound integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1981160053U JPS5866646U (en) | 1981-10-26 | 1981-10-26 | Sealing structure of hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5866646U JPS5866646U (en) | 1983-05-06 |
| JPS622775Y2 true JPS622775Y2 (en) | 1987-01-22 |
Family
ID=29952483
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1981160053U Granted JPS5866646U (en) | 1981-10-26 | 1981-10-26 | Sealing structure of hybrid integrated circuit |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS5866646U (en) |
| KR (1) | KR860000239Y1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3539467B2 (en) * | 1997-03-25 | 2004-07-07 | ミツミ電機株式会社 | Electronic component module |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53139206U (en) * | 1977-04-07 | 1978-11-04 |
-
1981
- 1981-10-26 JP JP1981160053U patent/JPS5866646U/en active Granted
-
1982
- 1982-04-20 KR KR2019820003095U patent/KR860000239Y1/en active
Also Published As
| Publication number | Publication date |
|---|---|
| KR860000239Y1 (en) | 1986-03-05 |
| KR830004331U (en) | 1983-12-30 |
| JPS5866646U (en) | 1983-05-06 |
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