JPS6233330Y2 - - Google Patents
Info
- Publication number
- JPS6233330Y2 JPS6233330Y2 JP1982120432U JP12043282U JPS6233330Y2 JP S6233330 Y2 JPS6233330 Y2 JP S6233330Y2 JP 1982120432 U JP1982120432 U JP 1982120432U JP 12043282 U JP12043282 U JP 12043282U JP S6233330 Y2 JPS6233330 Y2 JP S6233330Y2
- Authority
- JP
- Japan
- Prior art keywords
- heat sink
- power transistor
- integrated circuit
- hybrid integrated
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000007789 sealing Methods 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 7
- 229920005989 resin Polymers 0.000 claims description 6
- 239000011347 resin Substances 0.000 claims description 6
- 229920002050 silicone resin Polymers 0.000 claims description 5
- 125000006850 spacer group Chemical group 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Description
【考案の詳細な説明】
(イ) 考案の技術分野
本考案は混成集積回路、特にパワートランジス
タを組込んだ混成集積回路の封止構造の改良に関
する。[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to an improvement in the sealing structure of a hybrid integrated circuit, particularly a hybrid integrated circuit incorporating a power transistor.
(ロ) 考案の背景技術
従来の混成集積回路は第１図に示す如く、セラ
ミツクスあるいは表面を陽極酸化したアウルミニ
ウム等の絶縁基板１と、該基板１上に任意の形状
に設けた導電路２と、該導電路２上に半田で固着
されたヒートシンク３と、ヒートシンク３に固着
されたパワートランジスタ４と、パワートランジ
スタ４を薄く保護するシリコン樹脂５と、基板１
の周端に接着シート６で接着され全体を覆う蓋体
７と、で構成されていた。(b) Background of the invention As shown in FIG. 1, a conventional hybrid integrated circuit consists of an insulating substrate 1 made of ceramics or aluminium whose surface has been anodized, and conductive paths 2 provided in an arbitrary shape on the substrate 1. , a heat sink 3 fixed to the conductive path 2 with solder, a power transistor 4 fixed to the heat sink 3, a silicone resin 5 thinly protecting the power transistor 4, and a substrate 1.
and a lid body 7 that is adhered to the circumferential edge of the body with an adhesive sheet 6 to cover the entire body.
斯る構造の混成集積回路はテレビ、ラジオ、ス
テレオ等の比較的良好な使用環境を有する電子機
器では十分な封止と評価されていた。 Hybrid integrated circuits with such a structure have been evaluated as having sufficient sealing for electronic equipment such as televisions, radios, stereos, etc. that have relatively favorable usage environments.
しかしながら自動車の電装部品等の如くきわめ
て使用環境の悪いものにおいては十分な封止構造
とは言えず、特に電力を消費するパワートランジ
スタの劣化がきわめて問題となつていた。 However, it cannot be said that the sealing structure is sufficient for items such as electrical components of automobiles, which are used in extremely poor environments, and deterioration of power transistors, which consume electric power, has become a serious problem.
(ハ) 考案の開示
本考案は斯上した欠点に鑑みてなされ、パワー
トランジスタの良好な封止構造を有する混成集積
回路を実現するものである。(c) Disclosure of the invention The present invention has been made in view of the above-mentioned drawbacks, and is intended to realize a hybrid integrated circuit having a good sealing structure for power transistors.
本考案は枠体１５によりヒートシンク１３を囲
みパワートランジスタ１４を選択的に封止樹脂層
１６で完全に被覆することに特徴を有している。 The present invention is characterized in that the heat sink 13 is surrounded by a frame 15 and the power transistor 14 is selectively completely covered with a sealing resin layer 16.
(ニ) 本考案の実施例
本考案に依る混成集積回路は第２図および第３
図に示す如く、セラミツクスあるいは表面を陽極
酸化したアルミニウム等の絶縁基板１１と、該基
板１１上に任意の形状に設けた銅箔より成る導電
路１２と、導電路１２上に半田で固着されたヒー
トシンク１３と、ヒートシンク１３上に固着した
パワートランジスタ１４と、本考案の特徴とする
樹脂整形された枠体１５と、枠体１５内に充填さ
れた封止樹脂層１６と、基板１１の周端に接着シ
ート１７で接着された全体を封止する蓋体１８よ
り構成されている。(d) Example of the present invention The hybrid integrated circuit according to the present invention is shown in Figs. 2 and 3.
As shown in the figure, an insulating substrate 11 made of ceramics or aluminum whose surface is anodized, a conductive path 12 made of copper foil provided in an arbitrary shape on the substrate 11, and a conductive path 12 fixed with solder on the conductive path 12. A heat sink 13, a power transistor 14 fixed on the heat sink 13, a resin-shaped frame 15 that is a feature of the present invention, a sealing resin layer 16 filled in the frame 15, and a peripheral edge of the substrate 11. The cover body 18 is bonded to the top with an adhesive sheet 17 to seal the entire body.
ヒートシンク１３は13mm角で厚さ３mmの銅片を
用いると、枠体１５はヒートシンク１３より１mm
程度全周で離間できる大きさに形成される。更に
枠体１５は内側に突出した複数の間隔片２０を設
け、第２図の如くどのように配置しても全周でヒ
ートシンク１３との間にすき間を形成する様に配
慮している。更にまた枠体１５の高さはヒートシ
ンク１３およびパワートランジスタ１４の厚みの
和より若干高くなる様に設計される。 If the heat sink 13 is a 13 mm square copper piece with a thickness of 3 mm, the frame 15 is 1 mm smaller than the heat sink 13.
They are formed in a size that allows them to be spaced apart from each other around the entire circumference. Furthermore, the frame body 15 is provided with a plurality of spacer pieces 20 that protrude inwardly, so that a gap is formed between the frame body 15 and the heat sink 13 around the entire circumference no matter how it is arranged as shown in FIG. Furthermore, the height of the frame 15 is designed to be slightly higher than the sum of the thicknesses of the heat sink 13 and the power transistor 14.
パワートランジスタ１４はシリコン樹脂２１で
薄く被覆した後、枠体１５内にエポキシ樹脂１６
を充填して完全に封止する。このときヒートシン
ク１３側面にもエポキシ樹脂１６が充填されるの
で完全な封止構造を実現できる。 The power transistor 14 is thinly coated with silicone resin 21 and then covered with epoxy resin 16 in the frame 15.
Fill and seal completely. At this time, the side surfaces of the heat sink 13 are also filled with the epoxy resin 16, making it possible to realize a complete sealing structure.
(ホ) 本考案の効果
本考案に依れば厚いヒートシンク１３上に固着
されたパワートランジスタ１４も選択的に封止樹
脂層１６により封止を行なえる。また完全な封止
を求められない小信号回路部分については従来の
簡便な封止構造を適用できる。この結果極めて量
産性に富み且つ良好な封止構造の混成集積回路を
実現でき、その応用範囲もきわめて広い。(e) Effects of the present invention According to the present invention, the power transistor 14 fixed on the thick heat sink 13 can also be selectively sealed with the sealing resin layer 16. Furthermore, a conventional and simple sealing structure can be applied to small signal circuit parts that do not require complete sealing. As a result, it is possible to realize a hybrid integrated circuit that is highly mass-producible and has a good sealing structure, and its range of applications is also extremely wide.
第１図は従来例を説明する断面図、第２図は本
考案を説明する上面図、第３図は本考案を説明す
る断面図である。
主な図番の説明、１１は基板、１３はヒートシ
ンク、１４はパワートランジスタ、１５は枠体、
１６は樹脂層、１８は蓋体、２０は間隔片であ
る。
FIG. 1 is a sectional view illustrating a conventional example, FIG. 2 is a top view illustrating the present invention, and FIG. 3 is a sectional view illustrating the present invention. Explanation of the main drawing numbers, 11 is the board, 13 is the heat sink, 14 is the power transistor, 15 is the frame,
16 is a resin layer, 18 is a lid, and 20 is a spacing piece.
Claims (1)
の上面をシリコン樹脂で被覆されたパワートラン
ジスタを具備する混成集積回路において、前記ヒ
ートシンクを取り囲み且つ内側に突出した間隔片
により前記ヒートシンクより離間して配置した枠
体と、該枠体内に充填され前記パワートランジス
タ上の前記シリコン樹脂及び前記ヒートシンクを
完全に被覆する封止樹脂層とを有し、前記パワー
トランジスタを前記シリコン樹脂と前記封止樹脂
層とで二重被覆することを特徴とする混成集積回
路。 In a hybrid integrated circuit comprising a power transistor fixed to an insulating substrate via a heat sink and having its upper surface covered with silicone resin, a frame surrounding the heat sink and spaced apart from the heat sink by a spacer piece projecting inward. and a sealing resin layer that is filled into the frame and completely covers the silicone resin and the heat sink on the power transistor, and the power transistor is sealed with the silicone resin and the sealing resin layer. A hybrid integrated circuit characterized by heavy coating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12043282U JPS5926253U (en) | 1982-08-06 | 1982-08-06 | hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12043282U JPS5926253U (en) | 1982-08-06 | 1982-08-06 | hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5926253U JPS5926253U (en) | 1984-02-18 |
| JPS6233330Y2 true JPS6233330Y2 (en) | 1987-08-26 |
Family
ID=30276021
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12043282U Granted JPS5926253U (en) | 1982-08-06 | 1982-08-06 | hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5926253U (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04184378A (en) * | 1990-11-19 | 1992-07-01 | Mita Ind Co Ltd | Belt transferring/carrying device |
| JP2689242B2 (en) * | 1990-11-24 | 1997-12-10 | 株式会社 堀場製作所 | Venturi exchange device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56119658U (en) * | 1980-02-15 | 1981-09-11 | ||
| JPS56129738U (en) * | 1980-02-29 | 1981-10-02 |
-
1982
- 1982-08-06 JP JP12043282U patent/JPS5926253U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5926253U (en) | 1984-02-18 |
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