JPH0338745B2 - - Google Patents
Info
- Publication number
- JPH0338745B2 JPH0338745B2 JP59071654A JP7165484A JPH0338745B2 JP H0338745 B2 JPH0338745 B2 JP H0338745B2 JP 59071654 A JP59071654 A JP 59071654A JP 7165484 A JP7165484 A JP 7165484A JP H0338745 B2 JPH0338745 B2 JP H0338745B2
- Authority
- JP
- Japan
- Prior art keywords
- heat sink
- groove
- power element
- power transistor
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000007789 sealing Methods 0.000 claims description 12
- 229920005989 resin Polymers 0.000 claims description 8
- 239000011347 resin Substances 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/183—Connection portion, e.g. seal
- H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
Description
【発明の詳細な説明】
(イ) 産業上の利用分野
本発明はヒートシンクの製造方法、特に混成集
積回路等に用いるヒートシンクの製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a method for manufacturing a heat sink, and particularly to a method for manufacturing a heat sink used for hybrid integrated circuits and the like.
(ロ) 従来技術
従来の混成集積回路は第１図に示す如く、セラ
ミツクスあるいは表面を陽極酸化したアルミニウ
ム等の絶縁基板１と、該基板１上に任意の形状に
設けた導電路２と、該導電路２上に半田で固着さ
れたヒートシンク３と、ヒートシンク３に固着さ
れたパワートランジスタ４と、パワートランジス
タ４を被覆保護する封止樹脂層５と、基板１の周
端に接着シート６で接着され全体を覆う蓋体７と
で構成されていた。(b) Prior Art As shown in FIG. 1, a conventional hybrid integrated circuit includes an insulating substrate 1 made of ceramics or aluminum whose surface is anodized, a conductive path 2 provided in an arbitrary shape on the substrate 1, and a conductive path 2 provided in an arbitrary shape on the substrate 1. A heat sink 3 fixed on the conductive path 2 with solder, a power transistor 4 fixed on the heat sink 3, a sealing resin layer 5 covering and protecting the power transistor 4, and bonded to the peripheral edge of the substrate 1 with an adhesive sheet 6. and a lid body 7 that covers the entire body.
斯る構造の混成集積回路はテレビ、ラジオ、ス
テレオ等の比較的良好な使用環境を有する電子機
器では十分な封止と評価されていた。しかしなが
ら自動車の電装部品等の如く極めて使用環境の悪
いものにおいては十分な封止構造とはいえず、特
に電力を消費するパワートランジスタの劣化が極
めて問題となつていた。即ちヒートサイクルの結
果、封止樹脂層５にクラツクが発生し、クラツク
から入る酸素により半田酸化が起こり、パワート
ランジスタ４とヒートシンク３との熱抵抗が増大
してパワートランジスタ４が二次破壊されるので
ある。 Hybrid integrated circuits with such a structure have been evaluated as having sufficient sealing for electronic equipment such as televisions, radios, stereos, etc. that have relatively favorable usage environments. However, it cannot be said that the sealing structure is sufficient for items such as electrical components of automobiles, which are used in extremely poor environments, and deterioration of power transistors, which consume electric power, has become a serious problem. That is, as a result of the heat cycle, cracks occur in the sealing resin layer 5, solder oxidation occurs due to oxygen entering through the cracks, and the thermal resistance between the power transistor 4 and the heat sink 3 increases, resulting in secondary destruction of the power transistor 4. It is.
(ハ) 発明の目的
本発明は斯点に鑑みてなされ、混成集積回路に
組み込むパワートランジスタの良好な封止構造を
実現するヒートシンクの簡便な製造方法を提供す
ることを目的とする。(c) Object of the Invention The present invention was made in view of the above, and an object of the present invention is to provide a simple method for manufacturing a heat sink that realizes a good sealing structure for a power transistor incorporated into a hybrid integrated circuit.
(ニ) 発明の構成
本発明に依れば、平板上のヒートシンク上面に
溝を形成し、該溝の内側端部をプレスして逆テー
パー面を形成する様に構成されている。(d) Structure of the Invention According to the present invention, a groove is formed on the upper surface of the heat sink on a flat plate, and the inner end of the groove is pressed to form a reverse tapered surface.
(ホ) 実施例
本実施例に依れば第２図Ａに示す如く、13mm角
で厚さ３mmの銅片より成る平板状のヒートシンク
１３を準備する。ヒートシンク１３の上面には第
２図Ｂに示す如く、周辺に連続してあるいは不連
続して溝１９をプレスにより形成する。溝１９は
巾500μｍ、深さ300μｍ程度の逆台形状に形成さ
れる。続いて第２図Ｃに示す如く、溝１９の内側
端部を部分的に平プレスしてプレスによる変形を
利用して逆テーパー面１８を形成する。(E) Embodiment According to this embodiment, as shown in FIG. 2A, a flat heat sink 13 made of a copper piece 13 mm square and 3 mm thick is prepared. As shown in FIG. 2B, grooves 19 are formed on the upper surface of the heat sink 13 by pressing, either continuously or discontinuously around the periphery. The groove 19 is formed in an inverted trapezoid shape with a width of about 500 μm and a depth of about 300 μm. Subsequently, as shown in FIG. 2C, the inner end of the groove 19 is partially flat-pressed to form a reverse tapered surface 18 by utilizing the deformation caused by the pressing.
なお逆テーパー面１８は溝１９の内側斜面でも
外側斜面でも形成して良い。 Note that the reverse tapered surface 18 may be formed on either the inner slope or the outer slope of the groove 19.
斯上した本発明に依るヒートシンク１３は第３
図に示す如く、混成集積回路に組み込まれる。混
成集積回路はセラミツクスあるいは表面を陽極酸
化したアルミニウム等の絶縁基板１１と、該基板
１１上に任意の形状に設けた銅箔より成る導電路
１２と、導電路１２上に半田で固着されたヒート
シンク１３と、ヒートシンク１３上に固着したパ
ワートランジスタ１４と、本考案の特徴とする溝
１９と、パワートランジスタ１４を被覆する封止
樹脂層１５より構成されている。 The heat sink 13 according to the present invention described above is the third heat sink 13 according to the present invention.
As shown in the figure, it is incorporated into a hybrid integrated circuit. The hybrid integrated circuit includes an insulating substrate 11 made of ceramics or aluminum whose surface is anodized, a conductive path 12 made of copper foil provided in an arbitrary shape on the substrate 11, and a heat sink fixed on the conductive path 12 with solder. 13, a power transistor 14 fixed on the heat sink 13, a groove 19 which is a feature of the present invention, and a sealing resin layer 15 covering the power transistor 14.
パワートランジスタ１４はヒートシンク１３の
溝１９の内側に半田で固着され、エポキシ樹脂等
の封止樹脂層１５を塗布してパワートランジスタ
１４を被覆して保護する。この際封止樹脂層１５
は溝１９内にも充填される。その結果、ヒートシ
ンク１３に溝１９に逆テーパー面が形成されてい
るためにヒートサイクルによつて封止樹脂層に応
力が加わつたとしても逆テーパー面がもどり形状
になつているために封止樹脂層の剥離を防止する
ことができる。 The power transistor 14 is fixed to the inside of the groove 19 of the heat sink 13 with solder, and a sealing resin layer 15 such as epoxy resin is applied to cover and protect the power transistor 14. At this time, the sealing resin layer 15
is also filled in the groove 19. As a result, since the groove 19 of the heat sink 13 has an inverted tapered surface, even if stress is applied to the sealing resin layer due to heat cycles, the inverted tapered surface returns to its shape, so the sealing resin Peeling of layers can be prevented.
(ヘ) 発明の効果
本発明に依ればヒートシンク１３に逆テーパー
面１８を２回のプレス工程で容易に形成できる利
点を有する。そして混成集積回路に組み込めばヒ
ートサイクルに強いパワートランジスタ１４の封
止構造を実現できる。(F) Effects of the Invention According to the present invention, there is an advantage that the reverse tapered surface 18 can be easily formed on the heat sink 13 by two press steps. If it is incorporated into a hybrid integrated circuit, a sealed structure for the power transistor 14 that is resistant to heat cycles can be realized.
第１図は従来の混成集積回路を説明する断面
図、第２図Ａ，Ｂ，Ｃは本発明のヒートシンクの
製造方法を説明する断面図、第３図は本発明のヒ
ートシンクを用いた混成集積回路を説明する断面
図である。
主な図番の説明、１３はヒートシンク、１９は
溝、１８は逆テーパー面である。
FIG. 1 is a cross-sectional view explaining a conventional hybrid integrated circuit, FIGS. 2 A, B, and C are cross-sectional views explaining the method of manufacturing the heat sink of the present invention, and FIG. 3 is a cross-sectional view of a hybrid integrated circuit using the heat sink of the present invention. FIG. 2 is a cross-sectional view illustrating a circuit. Explanation of the main figure numbers: 13 is a heat sink, 19 is a groove, and 18 is a reverse tapered surface.
Claims (1)
ー素子を封止する封止樹脂がその上面に配置され
る平板状のヒートシンクの製造方法において、 前記平板状のヒートシンク上に前記パワー素子
が固着される周辺近傍に、前記パワー素子を取り
囲むように溝を形成し、 前記パワー素子を取り囲む前記溝の内側端部を
プレスして逆テーパー面を形成することを特徴と
するヒートシンクの製造方法。[Scope of Claims] 1. A method for manufacturing a flat heat sink in which only a power element is fixed, and a sealing resin for sealing the power element is placed on the top surface, comprising: A heat sink characterized in that a groove is formed near the periphery to which the power element is fixed so as to surround the power element, and an inner end of the groove surrounding the power element is pressed to form a reverse tapered surface. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7165484A JPS6065538A (en) | 1984-04-10 | 1984-04-10 | Manufacture of heat sink |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7165484A JPS6065538A (en) | 1984-04-10 | 1984-04-10 | Manufacture of heat sink |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6065538A JPS6065538A (en) | 1985-04-15 |
| JPH0338745B2 true JPH0338745B2 (en) | 1991-06-11 |
Family
ID=13466807
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7165484A Granted JPS6065538A (en) | 1984-04-10 | 1984-04-10 | Manufacture of heat sink |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6065538A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54128279A (en) * | 1978-03-29 | 1979-10-04 | Hitachi Ltd | Heat sink for resin-sealed semiconductor device and its manufacture |
-
1984
- 1984-04-10 JP JP7165484A patent/JPS6065538A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54128279A (en) * | 1978-03-29 | 1979-10-04 | Hitachi Ltd | Heat sink for resin-sealed semiconductor device and its manufacture |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6065538A (en) | 1985-04-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR20010014930A (en) | Semiconductor device | |
| KR20010049363A (en) | Semiconductor device | |
| JP2698278B2 (en) | Hybrid integrated circuit device | |
| JPH10149901A (en) | Electric resistor, and manufacturing method of electric resistor | |
| JP3544757B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH0338745B2 (en) | ||
| JPH0338746B2 (en) | ||
| JP2698259B2 (en) | Heat sink manufacturing method | |
| JPH0410742B2 (en) | ||
| JPS6233330Y2 (en) | ||
| JPH025539Y2 (en) | ||
| JPS6311735Y2 (en) | ||
| JPH0210578B2 (en) | ||
| JPH09246433A (en) | Radiation structure of module | |
| JPH0159755B2 (en) | ||
| CN113841233B (en) | Semiconductor module | |
| US20230282566A1 (en) | Semiconductor package having negative patterned substrate and method of manufacturing the same | |
| JPH0561780B2 (en) | ||
| JP2019096827A (en) | Circuit structure | |
| JPS6334277Y2 (en) | ||
| JPH0354469B2 (en) | ||
| JPS6239036A (en) | Hybrid ic | |
| JPH0621231Y2 (en) | Electrolytic capacitor | |
| JPS6020942Y2 (en) | semiconductor equipment | |
| JPH0333071Y2 (en) |