JPH025539Y2 - - Google Patents
Info
- Publication number
- JPH025539Y2 JPH025539Y2 JP1984062144U JP6214484U JPH025539Y2 JP H025539 Y2 JPH025539 Y2 JP H025539Y2 JP 1984062144 U JP1984062144 U JP 1984062144U JP 6214484 U JP6214484 U JP 6214484U JP H025539 Y2 JPH025539 Y2 JP H025539Y2
- Authority
- JP
- Japan
- Prior art keywords
- heat sink
- power transistor
- integrated circuit
- hybrid integrated
- locking groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000007789 sealing Methods 0.000 claims description 18
- 239000011347 resin Substances 0.000 claims description 11
- 229920005989 resin Polymers 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 8
- 229910000679 solder Inorganic materials 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000005219 brazing Methods 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/183—Connection portion, e.g. seal
- H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
Description
【考案の詳細な説明】
(イ) 産業上の利用分野
本考案は混成集積回路、特にパワートランジス
タを組込んだ混成集積回路の封止構造の改良に関
する。[Detailed Description of the Invention] (a) Field of Industrial Application The present invention relates to an improvement in the sealing structure of a hybrid integrated circuit, particularly a hybrid integrated circuit incorporating a power transistor.
(ロ) 従来技術
従来の混成集積回路は第１図に示す如く、セラ
ミツクスあるいは表面を陽極酸化したアルミニウ
ム等の絶縁基板１と、該基板１上に任意の形状に
設けた導電路２と、該導電路２上に半田で固着さ
れたヒートシンク３と、ヒートシンク３に固着さ
れたパワートランジスタ４と、パワートランジス
タ４を被覆保護する封止樹脂層５と、基板１の周
端に接着シート６で接着され全体を覆う蓋体７と
で構成されていた。(b) Prior Art As shown in FIG. 1, a conventional hybrid integrated circuit includes an insulating substrate 1 made of ceramics or aluminum whose surface is anodized, a conductive path 2 provided in an arbitrary shape on the substrate 1, and a conductive path 2 provided in an arbitrary shape on the substrate 1. A heat sink 3 fixed on the conductive path 2 with solder, a power transistor 4 fixed on the heat sink 3, a sealing resin layer 5 covering and protecting the power transistor 4, and bonded to the peripheral edge of the substrate 1 with an adhesive sheet 6. and a lid body 7 that covers the entire body.
斯る構造の混成集積回路はテレビ、ラジオ、ス
テレオ等の比較的良好な使用環境を有する電子機
器では十分な封止と評価されていた。しかしなが
ら自動車の電装部品等の如く極めて使用環境の悪
いものにおいては十分な封止構造とは言えず、特
に電力を消費するパワートランジスタの劣化が極
めて問題となつていた。即ちヒートサイクルの結
果、封止樹脂層５にクラツクが発生し、クラツク
から入る酸素により半田酸化が起こり、パワート
ランジスタ４とヒートシンク３との熱抵抗が増大
してパワートランジスタ４が二次破壊されるので
ある。 Hybrid integrated circuits with such a structure have been evaluated as having sufficient sealing for electronic equipment such as televisions, radios, stereos, etc. that have relatively favorable usage environments. However, it cannot be said that the sealing structure is sufficient for items such as electrical components of automobiles, which are used in extremely poor environments, and deterioration of power transistors, which consume electric power, has become a serious problem. That is, as a result of the heat cycle, cracks occur in the sealing resin layer 5, solder oxidation occurs due to oxygen entering through the cracks, and the thermal resistance between the power transistor 4 and the heat sink 3 increases, resulting in secondary destruction of the power transistor 4. It is.
そこで本考案者が更に改良をした混成集積回路
を第２図に示す。斯る混成集積回路はセラミツク
スあるいは表面を陽極酸化したアルミニウム等の
絶縁基板１１と、該基板１１上に任意の形状に設
けた銅箔より成る導電路１２と、導電路１２上に
半田で固着されたヒートシンク１３と、ヒートシ
ンク１３上に固着したパワートランジスタ１４
と、ヒートシンク１３に設けた係止溝１９と、パ
ワートランジスタ１４を被覆する封止樹脂層１５
より成る。 FIG. 2 shows a hybrid integrated circuit further improved by the present inventor. Such a hybrid integrated circuit includes an insulating substrate 11 made of ceramics or aluminum whose surface is anodized, a conductive path 12 made of copper foil provided in an arbitrary shape on the substrate 11, and a conductive path 12 fixed on the conductive path 12 with solder. a heat sink 13 and a power transistor 14 fixed on the heat sink 13
, a locking groove 19 provided in the heat sink 13 , and a sealing resin layer 15 covering the power transistor 14 .
Consists of.
ヒートシンク１３は13mm角で厚さ３mmの銅片を
用い、第３図に示す如く逆テーパー面１８を有す
る係止溝１９を設け、封止樹脂層１５のヒートサ
イクルによるヒートシンク１３からの剥離を防止
する点に特徴を有している。しかしながらこの係
止溝１９は第４図に示す如く、ヒートシンク１３
の周辺に環状に形成されていた。このためにヒー
トシンク１３の面積の小さいものではパワートラ
ンジスタ１４を半田で固着する際に往復移動させ
て良好なろう付を実現するときに係止溝１９が障
害となり、パワートランジスタ１４を十分に往復
移動できない欠点があつた。 The heat sink 13 is made of a copper piece 13 mm square and 3 mm thick, and is provided with a locking groove 19 having a reverse tapered surface 18 as shown in FIG. 3 to prevent the sealing resin layer 15 from peeling off from the heat sink 13 due to heat cycles. It is characterized by the fact that However, as shown in FIG.
It was formed in a ring around the . For this reason, if the heat sink 13 has a small area, the locking groove 19 becomes an obstacle when moving the power transistor 14 back and forth to achieve good brazing when fixing the power transistor 14 with solder. There was a drawback that I couldn't do it.
(ハ) 考案の目的
本考案は斯上した欠点に鑑みてなされ、パワー
トランジスタの良好な封止構造を有する混成集積
回路を実現するものである。(c) Purpose of the invention The present invention has been made in view of the above-mentioned drawbacks, and is intended to realize a hybrid integrated circuit having a good sealing structure for power transistors.
(ニ) 考案の構成
本考案に依れば、絶縁基板上にヒートシンクを
介して固着したパワートランジスタを具備する混
成集積回路に於いて、前記ヒートシンクの四角に
逆テーパー面を有する係止溝を設け、該係止溝よ
り中央方向に延在するガイド溝を設け、前記パワ
ートランジスタを被覆し前記両溝内に充填される
封止樹脂層を設けて構成される。(d) Structure of the invention According to the invention, in a hybrid integrated circuit including a power transistor fixed on an insulating substrate via a heat sink, a locking groove having a reverse tapered surface is provided in a square of the heat sink. , a guide groove extending toward the center from the locking groove is provided, and a sealing resin layer is provided to cover the power transistor and fill both the grooves.
(ホ) 実施例
本考案の一実施例を第２図および第５図を参照
して説明する。本考案は第２図に示す従来の混成
集積回路に於いてヒートシンク１３に設けた係止
溝１９の形状に特徴を有する。(e) Embodiment An embodiment of the present invention will be described with reference to FIGS. 2 and 5. The present invention is characterized by the shape of the locking groove 19 provided in the heat sink 13 in the conventional hybrid integrated circuit shown in FIG.
第５図に示す如く、正方形状のヒートシンク１
３の四角に円弧状の逆テーパー面を有する係止溝
１９を設ける。係止溝１９はヒートシンク１３の
各辺の中間部分には形成されないのが特徴であ
り、少くとも固着するパワートランジスタ１４の
一辺の長さより長く離間されている。係止溝１９
から中心方向に対角線上を延在するガイド溝２０
が設けられる。ガイド溝２０は通常の断面がＵ字
形状であれば良く、逆テーパー面を設ける必要が
ない。 As shown in FIG. 5, a square heat sink 1
A locking groove 19 having an arcuate inversely tapered surface is provided in the square of 3. A feature of the locking grooves 19 is that they are not formed in the middle of each side of the heat sink 13, and are spaced apart from each other by at least a length longer than the length of one side of the power transistor 14 to which it is fixed. Locking groove 19
A guide groove 20 extending diagonally toward the center from
is provided. The guide groove 20 only needs to have a normal U-shaped cross section, and there is no need to provide an inverted tapered surface.
斯上したヒートシンク１３では点線で示すとこ
ろにパワートランジスタ１４を固着する場合、パ
ワートランジスタ１３を往復移動させて良好なろ
う付を行うとき係止溝１９は四角に分離して配置
されているので全く障害とならない。また封止樹
脂層１５を中央部のパワートランジスタ１４上に
滴下すると同心円状に周辺に広がつて行くが、ガ
イド溝２０にすぐに封止樹脂層１５が到達するの
で係止溝１９に容易且つ確実に充填できる。 In the above-mentioned heat sink 13, when the power transistor 14 is fixed to the area shown by the dotted line, the locking grooves 19 are arranged in squares, so when the power transistor 13 is moved back and forth to achieve good brazing, it is completely Not a hindrance. Furthermore, when the sealing resin layer 15 is dropped onto the power transistor 14 in the center, it spreads concentrically around the periphery, but since the sealing resin layer 15 immediately reaches the guide groove 20, it can easily fit into the locking groove 19. Can be reliably filled.
(ヘ) 考案の効果
本考案に依れば溝１９の逆テーパー面１８によ
りパワートランジスタ１４の封止樹脂層１５のヒ
ートサイクルによる剥離を未然に防止できるの
で、良好な封止構造を実現できる。また封止樹脂
層１５はガイド溝２０を介して係止溝１９に導く
ことができるので、確実に良好な封止を行なえ
る。更に係止溝１９を四角に分離して配置するの
で、ヒートシンク１３を小型化してもパワートラ
ンジスタ１４の固着が容易である。(f) Effects of the invention According to the invention, the inverted tapered surface 18 of the groove 19 can prevent the sealing resin layer 15 of the power transistor 14 from peeling off due to heat cycles, so a good sealing structure can be realized. Moreover, since the sealing resin layer 15 can be guided to the locking groove 19 via the guide groove 20, good sealing can be reliably performed. Further, since the locking grooves 19 are arranged in a square manner, it is easy to fix the power transistor 14 even if the heat sink 13 is downsized.
第１図および第２図は従来の混成集積回路を説
明する断面図、第３図および第４図は従来用いた
ヒートシンクを説明する断面図および上面図、第
５図は本考案にヒートシンクを説明する上面図で
ある。
主な図番の説明、１３はヒートシンク、１４は
パワートランジスタ、１５は封止樹脂層、１６は
接着シート、１７は封止蓋、１８は逆テーパー
面、１９は係止溝、２０はガイド溝である。
1 and 2 are cross-sectional views illustrating a conventional hybrid integrated circuit, 3 and 4 are sectional views and top views illustrating conventional heat sinks, and 5 is a cross-sectional view illustrating a heat sink according to the present invention. FIG. Explanation of main drawing numbers: 13 is a heat sink, 14 is a power transistor, 15 is a sealing resin layer, 16 is an adhesive sheet, 17 is a sealing lid, 18 is a reverse tapered surface, 19 is a locking groove, 20 is a guide groove It is.
Claims (1)
ワートランジスタを具備する混成集積回路に於い
て、前記ヒートシンクの四角に逆テーパー面を有
する係止溝を設け、該係止溝より中央方向に延在
するガイド溝を設け、前記パワートランジスタを
被覆し前記両溝内に充填される封止樹脂層を具備
することを特徴とする混成集積回路。 In a hybrid integrated circuit comprising a power transistor fixed on an insulating substrate via a heat sink, a locking groove having a reversely tapered surface is provided in a square of the heat sink, and a guide extends from the locking groove toward the center. 1. A hybrid integrated circuit, comprising a groove, and a sealing resin layer covering the power transistor and filling both the grooves.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984062144U JPS60174252U (en) | 1984-04-25 | 1984-04-25 | hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984062144U JPS60174252U (en) | 1984-04-25 | 1984-04-25 | hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60174252U JPS60174252U (en) | 1985-11-19 |
| JPH025539Y2 true JPH025539Y2 (en) | 1990-02-09 |
Family
ID=30591078
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984062144U Granted JPS60174252U (en) | 1984-04-25 | 1984-04-25 | hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60174252U (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008262990A (en) * | 2007-04-10 | 2008-10-30 | ▲がい▼笛森光電股▲ふん▼有限公司 | Enclosed structure of light emitting diode, and method of manufacturing the same |
-
1984
- 1984-04-25 JP JP1984062144U patent/JPS60174252U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60174252U (en) | 1985-11-19 |
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