JPS62271458A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS62271458A JPS62271458A JP61115578A JP11557886A JPS62271458A JP S62271458 A JPS62271458 A JP S62271458A JP 61115578 A JP61115578 A JP 61115578A JP 11557886 A JP11557886 A JP 11557886A JP S62271458 A JPS62271458 A JP S62271458A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- mos transistor
- layer
- transistor
- load
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 239000012535 impurity Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000002513 implantation Methods 0.000 claims abstract description 4
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 claims description 3
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
〔発明の目的〕
（産業上の利用分野）
本発明は半導体基板上に構成された半導体集積回路に関
する。Detailed Description of the Invention 3. Detailed Description of the Invention [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit constructed on a semiconductor substrate.
（従来の技術）
第２図は第３図に示すような直列接続された２つのｎチ
ャネルＭＯＳトランジスタ２０および３０よりなるソー
スフォロア回路を集積化した例を示す断面図である。ｎ
型基板１上にｐウェル層２を形成し、このｐウェル層２
内にソースフォロア回路が形成される。通常ｐウェル層
２と基板１との間には逆バイアスＴｉａｉｏが接続され
ている。(Prior Art) FIG. 2 is a sectional view showing an example of an integrated source follower circuit consisting of two n-channel MOS transistors 20 and 30 connected in series as shown in FIG. n
A p-well layer 2 is formed on a mold substrate 1, and this p-well layer 2
A source follower circuit is formed inside. Normally, a reverse bias Tiaio is connected between the p-well layer 2 and the substrate 1.
入力ＭＯＳトランジスタ２０はゲート３とソース・ドレ
インを形成づるｎ＋半導体層６，７から構成され、負荷
ＭｏＳトランジスタ３０はゲート４とソース・ドレイン
な形成するｎ°半導体層７゜８とから構成される。負荷
ＭＯ８）−ランジスタ３０のゲート４とｎ＋半導体層８
とは共通接続されて接地されている。The input MOS transistor 20 is composed of a gate 3 and n+ semiconductor layers 6 and 7 forming a source and drain, and the load MoS transistor 30 is composed of a gate 4 and an n° semiconductor layer 78 forming a source and drain. . Load MO8) - gate 4 of transistor 30 and n+ semiconductor layer 8
and are commonly connected and grounded.
また入力ＭＯＳトランジスタ２ｏのｎ＋半導体層６には
正の電圧例えば＋１２Ｖが印加される。Further, a positive voltage, for example, +12V is applied to the n+ semiconductor layer 6 of the input MOS transistor 2o.
ゲート３は入力端子Ｖ１Ｎとして、ｎ＋半導体層７は出
力端子Ｖ。Ｕｌとして取り出される。このような従来構
成されてきたソースフォロア回路においては、入力Ｍｏ
Ｓトランジスタ２ｏの入力ゲート３の直下には不純物拡
散層は形成されていないのが通常であり、負荷ＭＯＳト
ランジスタ３０のゲート４の直下にはディプレッション
領域を形成するためのイオンインプランテーションを行
なって、ｎ−半導体層５を形成するのが通常であった。The gate 3 serves as an input terminal V1N, and the n+ semiconductor layer 7 serves as an output terminal V. It is taken out as Ul. In such a conventionally configured source follower circuit, the input Mo
Normally, no impurity diffusion layer is formed directly under the input gate 3 of the S transistor 2o, and ion implantation is performed to form a depletion region directly under the gate 4 of the load MOS transistor 30. It was usual to form an n-semiconductor layer 5.
またＭＯＳトランジスタのゲート長とゲート幅との比は
入力ＭＯＳトランジスタ２０と負荷ＭＯＳトランジスタ
とで異なっているのが一般的である。これはゲート長と
ゲート幅との比は通常のソースフォロア回路の周波数特
性や消費電力が所望の値になるように設定するように選
ばれるためである。Further, the ratio between the gate length and gate width of the MOS transistor is generally different between the input MOS transistor 20 and the load MOS transistor. This is because the ratio of gate length to gate width is selected so that the frequency characteristics and power consumption of a normal source follower circuit are set to desired values.
このような半導体装置において、入力ゲート３に電圧を
印加し、その時できるボテフシ１フル井戸との間の変調
度をｍとするとゲート３に入力電圧■ を印加した時の
ポテンシャル井戸はｍＶＩＮとＮ
なる。また負荷ＭＯＳトランジスタ３０のゲート４は接
地されているため、このゲート４の直下にできるポテン
シャル井戸を■ＰＷＩ！ニジてソースフォロア回路の動
作を説明する。ｎ＋半導体層（ソース）８を接地したこ
とにより、その電源から供給された電荷は負荷ＭＯＳト
ランジスタ３０のゲート４を通りさらに入力ＭＯＳトラ
ンジスタ２０のゲート３を通って、正電圧例えば１２Ｖ
を印加したｎ＋半導体層（ドレイン）６に流れこむ。In such a semiconductor device, when a voltage is applied to the input gate 3, and the degree of modulation between the voltage and the full well formed at that time is m, the potential well when the input voltage ■ is applied to the gate 3 becomes mVIN and N. . Also, since the gate 4 of the load MOS transistor 30 is grounded, a potential well formed directly under the gate 4 is created by ■PWI! Next, the operation of the source follower circuit will be explained. By grounding the n+ semiconductor layer (source) 8, the charge supplied from the power supply passes through the gate 4 of the load MOS transistor 30, and further passes through the gate 3 of the input MOS transistor 20, and becomes a positive voltage, for example, 12V.
flows into the n+ semiconductor layer (drain) 6 to which is applied.
ここで負荷ＭＯＳトランジスタ３００ゲート４の長さを
Ｌ １幅をＷｌとし、入力ＭＯＳトランジスタ３０のゲ
ート３の長さをし 、幅をＷ２とすると負荷ＭＯＳトラ
ンジスタ３０のゲート４の下を流れる電流は、
と表わされる。なおＫは比例定数を表わす。またゲート
３直下の電圧降下をＸとするとゲート３直下に流れる電
流は、
と書ける。ここで負荷ＭＯＳトランジスタ３０のゲート
４と入力ＭＯＳトランジスタ２０のゲート３の直下を流
れる゛電流はそれぞれ等しい（１１＝１２）ので、
となる。したがって出力■。Ｕ、は、
と表わされる。（４）式より明らかなようにオフセット
電圧に２つのばらつき要素があることがわかる。その１
つは′ｆ！Ｌ″Ｊ１度ｍであり、もう１つはポテンシャ
ル井戸の深さｖ、Ｗｒ−ある。この両者は酸化膜厚や基
板抵抗あるいはプロセスのばらつき等により変動する。Here, if the length of the gate 4 of the load MOS transistor 300 is L, the width of the gate 4 is Wl, the length of the gate 3 of the input MOS transistor 30 is taken, and the width is W2, the current flowing under the gate 4 of the load MOS transistor 30 is , is expressed as . Note that K represents a proportionality constant. Also, if the voltage drop directly under the gate 3 is X, the current flowing directly under the gate 3 can be written as follows. Here, since the currents flowing directly under the gate 4 of the load MOS transistor 30 and the gate 3 of the input MOS transistor 20 are equal (11=12), the following equation is obtained. Therefore the output ■. U, is expressed as . As is clear from equation (4), there are two variation factors in the offset voltage. Part 1
One is 'f! L''J is 1 degree m, and the other is the potential well depth v, Wr-. Both of these vary depending on the oxide film thickness, substrate resistance, process variations, etc.
変調度ｍはボテンシｉ？ル井戸特性の勾配であるため変
動は小さい。しかしポテンシャル井戸の深さ■ＰＷはポ
テンシャル井戸特性の電圧値自体であるため変動が大き
く、ソースフォロア回路のオフセットのばらつきに大き
な影響を与えるという問題を生じている。Is the modulation degree m equal to the potency i? The fluctuation is small because it is a slope of the well characteristics. However, since the potential well depth (PW) is the voltage value itself of the potential well characteristics, it fluctuates greatly, causing a problem in that it has a large effect on the offset variation of the source follower circuit.
（発明が解決しようとする問題点）
このように従来の半導体集積回路ではボテンシＶル井戸
の深さｖＰ−影響によるオフセット電圧の変動が発生す
るため、ソースフォロア回路の出力信号を処理する後段
の回路のダイナミックレンジを大きく設計する必要が生
じ、回路全体が複雑化してしまうという欠点がある。(Problems to be Solved by the Invention) In this way, in conventional semiconductor integrated circuits, fluctuations in offset voltage occur due to the effect of the depth vP of the voltage well. This has the disadvantage that it is necessary to design a circuit with a large dynamic range, making the entire circuit complicated.
そこで本発明は負荷ＭＯＳトランジスタのゲート直下の
ポテンシャル井戸にばらつきが生じてもオフセット電圧
にバラツキを生じないソースフォロア回路を提供するこ
とを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a source follower circuit that does not cause variations in offset voltage even if variations occur in the potential well directly under the gate of a load MOS transistor.
（問題点を解決するための手段）
本発明にかかる半導体集積回路では動作ＭＯＳトランジ
スタと負荷ＭＯＳトランジスタとを結合した回路を半導
体基板上に集積化してなる半導体集積回路において、ゲ
ート長とゲート幅との比を両ＭＯ８ｌ−ランジスタ間で
同一とし、かつ両ＭＯＳトランジスタのゲート直Ｆに同
−状態量の不純物注入層を形成したことを特徴としてい
る。(Means for Solving the Problems) In a semiconductor integrated circuit according to the present invention, a gate length and a gate width are The ratio of MOS transistors is the same between both MO8l transistors, and an impurity implantation layer with the same state amount is formed directly at the gates of both MOS transistors.
（作 用）
このようにゲート長とゲート幅との比を負荷ＭＯＳトラ
ンジスタと動作ＭＯ８ｔ−ランジスタとで同一とし、両
ＭＯ３ｔ−ランジスタのゲート直下に同一状態の不１Ｉ
ＩＩｖＡ注入層を形成すると、出力ｖｏｕｔがポテンシ
ャル井戸の深さＶｐｔ４に関係しない式として表わされ
る。したがってポテンシャル井戸の深さがばらついても
ソースフォロア回路においてはオフセット電圧のばらつ
きに大きな影響を与えない。(Function) In this way, the ratio of the gate length to the gate width is made the same for the load MOS transistor and the operating MO8t-transistor, and an inverter in the same state is placed directly under the gate of both MO3t-transistors.
When the IIvA injection layer is formed, the output vout can be expressed as an equation that is not related to the depth Vpt4 of the potential well. Therefore, even if the depth of the potential well varies, it does not significantly affect the variation in offset voltage in the source follower circuit.
（実施例）
以下本発明の一実施例を第１図に示す図面を参照して詳
細に説明する。(Embodiment) An embodiment of the present invention will be described in detail below with reference to the drawing shown in FIG.
第１図は本発明の一実施例にかかる集積化ソースフォロ
ア回路の断面図である。なお第２図に示した従来の構成
と同一部分には同一符号を付しその説明は省略する。FIG. 1 is a cross-sectional view of an integrated source follower circuit according to an embodiment of the present invention. Note that the same parts as those in the conventional configuration shown in FIG. 2 are given the same reference numerals, and the explanation thereof will be omitted.
この集積化ソースフォロア回路においてはゲート長とゲ
ート幅との比を入力ＭＯＳトランジスタ２０と負荷ＭＯ
８ｌ−ランジスタ３０と同一となるように構成する。さ
らに負荷ＭＯＳトランジスタ３０のゲート４の直下に形
成されるｎ−１５と同一状態になったｎ一層９を入力Ｍ
Ｏ８ｌ−ランジスタ２０のゲート３の直下にも形成して
いる。すなわちゲート４直下に形成されるｎ−半導体５
とゲート３直下に形成されるｎ−半導体層９とは同一工
程で形成され不純物ドーズ吊が同一であり濃度が同一と
なっている。In this integrated source follower circuit, the ratio of the gate length to the gate width is determined between the input MOS transistor 20 and the load MO.
The configuration is the same as that of the 8l-transistor 30. Furthermore, input M
It is also formed directly under the gate 3 of the O8l-transistor 20. In other words, the n-semiconductor 5 formed directly under the gate 4
The n-semiconductor layer 9 formed immediately below the gate 3 is formed in the same process, has the same impurity dose, and has the same concentration.
この不純物拡散層の形成はイオンインプランテーション
によりゲート酸化膜を介して同時に注入し、熱処理によ
り拡散を行なえばよい。他の構成は第２図に示す従来の
装置と同様である。This impurity diffusion layer may be formed by simultaneously implanting the impurity through the gate oxide film by ion implantation, and then performing the diffusion by heat treatment. The other configurations are similar to the conventional device shown in FIG.
このように同一の状態量の不純物層を入力ＭＯＳトラン
ジスタ２０と負荷ＭＯ８ｔ−ランジスタ３０のゲート直
下に注入したことにより、人力ゲート３に入力ｖＩＭを
印加した時のポテンシャル井戸はｍ・■ＩＨに、負荷Ｍ
Ｏ８ｌ−ランジスタ３０のゲート４を接地した時のポテ
ンシャル井戸■ＢＷを加えたものとなる。接地電位から
ゲート４．３を介して流れる電流は、
と書ける。なおここでＫは比例定数、Ｌはゲート長、Ｗ
はゲート幅を示す。By injecting the impurity layer with the same state amount directly under the gates of the input MOS transistor 20 and the load MO8t-transistor 30 in this way, the potential well when the input vIM is applied to the human-powered gate 3 becomes m·■IH, Load M
O8l - Potential well BW when the gate 4 of the transistor 30 is grounded. The current flowing from the ground potential through the gate 4.3 can be written as. Note that here, K is a proportionality constant, L is the gate length, and W
indicates the gate width.
ここでトランジスタ２０とトランジスタ３０とのゲート
長とゲート幅との比は同一であるのでＷ／Ｌは一定値と
なり、ゲート３およびゲート４とを流れる電流は等しく
なる。そしてその出力ｖｏｕ℃は・
Ｖ ＝ （ｍ−Ｖ ＋Ｖ ）−ＶＰ、＝ｍ−Ｖ
ＩＮＯＵＴ ＩＮ ＰＷ
・・・・・・（６）
と書ける。（６）式かられかるように負荷ＭＯＳトラン
ジスタ３０のゲート４の直下に形成されるボテンシｔ！
ル井戸の深さｖＰＷがばらついてもその影響は出力■。Here, since the gate length and gate width ratios of transistors 20 and 30 are the same, W/L is a constant value, and the currents flowing through gates 3 and 4 are equal. And its output vou℃ is V = (m-V +V)-VP, = m-V
It can be written as INOUT IN PW (6). As can be seen from equation (6), the potential t! formed directly below the gate 4 of the load MOS transistor 30!
Even if the well depth vPW varies, the effect is on the output ■.
ｏｌにまったく表わされることはない。It is never expressed in ol.
以上の実施例ではＭｏ８ ｌ−ランジスタの回路として
ソースフォロア回路を取り上げているが、動作トランジ
スタと負荷トランジスタよりなる他の回路でもよい。In the above embodiment, a source follower circuit is used as the circuit of the Mo8 l-transistor, but other circuits consisting of operating transistors and load transistors may be used.
またソースフォロア回路の場合第４図に示すような入力
トランジスタ２０，４０．１１５よび負荷トランジスタ
３０．５０を有する２段のソースフォロア回路にも本発
明を適用することができる。In the case of a source follower circuit, the present invention can also be applied to a two-stage source follower circuit having input transistors 20, 40, 115 and load transistors 30, 50 as shown in FIG.
（発明の効果）
以上実施例に基づいて詳細に説明したように本発明では
負荷ＭｏＳトランジスタのゲート直下のポテンシャル井
戸にばらつきがあってもそれがトランジスタ回路の特性
には全り影響を与えることがない。したがって回路の安
定した動作が可能となる。(Effects of the Invention) As described above in detail based on the embodiments, in the present invention, even if there is variation in the potential well directly under the gate of the load MoS transistor, it does not affect the characteristics of the transistor circuit at all. do not have. Therefore, stable operation of the circuit is possible.
第１図は本発明の一実施例を示す集積化ソースフォロア
回路の構成断面図、第２図は従来の構成断面図、第３図
および第４図は本発明を適用すべき回路を示す回路図で
ある。
３・・・入力ＭＯＳトランジスタのゲート、４・・・負
荷ＭｏＳトランジスタのゲート、５・・・ｎ−半導体層
、９・・・ｎ−半導体層、２０・・・入力ＭＯＳトラン
ジスタ、３０・・・負荷ＭＯＳトランジスタ。FIG. 1 is a sectional view of the structure of an integrated source follower circuit showing an embodiment of the present invention, FIG. 2 is a sectional view of a conventional structure, and FIGS. 3 and 4 are circuits showing circuits to which the present invention is applied. It is a diagram. 3... Gate of input MOS transistor, 4... Gate of load MoS transistor, 5... n-semiconductor layer, 9... n-semiconductor layer, 20... input MOS transistor, 30... Load MOS transistor.
Claims (1)
とを結合した回路を半導体基板上に集積化してなる半導
体集積回路において、ゲート長とゲート幅との比が前記
両ＭＯＳトランジスタ間で同一であり、かつ前記両ＭＯ
Ｓトランジスタのゲート直下に同一状態の不純物注入層
を形成してなる半導体集積回路。 ２、不純物注入層が同一工程のイオンインプランテーシ
ョンにより形成されたものである特許請求の範囲第１項
記載の半導体集積回路。 ３、動作ＭＯＳトランジスタと負荷ＭＯＳトランジスタ
の結合回路がソースフォロア回路である特許請求の範囲
第１項または第２項記載の半導体集積回路。[Claims] 1. In a semiconductor integrated circuit formed by integrating a circuit in which an operating MOS transistor and a load MOS transistor are combined on a semiconductor substrate, the ratio of gate length to gate width is the same between the two MOS transistors. and both MOs
A semiconductor integrated circuit in which an impurity implantation layer in the same state is formed directly under the gate of an S transistor. 2. The semiconductor integrated circuit according to claim 1, wherein the impurity implantation layer is formed by ion implantation in the same process. 3. The semiconductor integrated circuit according to claim 1 or 2, wherein the coupling circuit of the operating MOS transistor and the load MOS transistor is a source follower circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61115578A JP2557846B2 (en) | 1986-05-20 | 1986-05-20 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61115578A JP2557846B2 (en) | 1986-05-20 | 1986-05-20 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62271458A true JPS62271458A (en) | 1987-11-25 |
| JP2557846B2 JP2557846B2 (en) | 1996-11-27 |
Family
ID=14666049
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61115578A Expired - Lifetime JP2557846B2 (en) | 1986-05-20 | 1986-05-20 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2557846B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016009838A1 (en) * | 2014-07-15 | 2016-01-21 | ソニー株式会社 | Amplifying device, semiconductor device, production method and electronic device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55151365A (en) * | 1979-05-14 | 1980-11-25 | Semiconductor Res Found | Insulated gate type transistor and semiconductor integrated circuit |
-
1986
- 1986-05-20 JP JP61115578A patent/JP2557846B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55151365A (en) * | 1979-05-14 | 1980-11-25 | Semiconductor Res Found | Insulated gate type transistor and semiconductor integrated circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016009838A1 (en) * | 2014-07-15 | 2016-01-21 | ソニー株式会社 | Amplifying device, semiconductor device, production method and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2557846B2 (en) | 1996-11-27 |
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| EXPY | Cancellation because of completion of term |